BibTeX record conf/vdat/RSVB17

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@inproceedings{DBLP:conf/vdat/RSVB17,
  author    = {Thilagavathy R and
               Susmitha Settivari and
               B. Venkataramani and
               M. Bhaskar},
  title     = {{FPGA} Implementation of a Novel Area Efficient {FFT} Scheme Using
               Mixed Radix {FFT}},
  booktitle = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  pages     = {75--80},
  year      = {2017},
  crossref  = {DBLP:conf/vdat/2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7\_9},
  doi       = {10.1007/978-981-10-7470-7\_9},
  timestamp = {Sat, 06 Jan 2018 18:41:43 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/vdat/RSVB17},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/vdat/2017,
  editor    = {Brajesh Kumar Kaushik and
               Sudeb Dasgupta and
               Virendra Singh},
  title     = {{VLSI} Design and Test - 21st International Symposium, {VDAT} 2017,
               Roorkee, India, June 29 - July 2, 2017, Revised Selected Papers},
  series    = {Communications in Computer and Information Science},
  volume    = {711},
  publisher = {Springer},
  year      = {2017},
  url       = {https://doi.org/10.1007/978-981-10-7470-7},
  doi       = {10.1007/978-981-10-7470-7},
  isbn      = {978-981-10-7469-1},
  timestamp = {Sat, 06 Jan 2018 18:41:28 +0100},
  biburl    = {https://dblp.org/rec/bib/conf/vdat/2017},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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