BibTeX record journals/jssc/Briseno-Vidrios17

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@article{DBLP:journals/jssc/Briseno-Vidrios17,
  author       = {Carlos Briseno{-}Vidrios and
                  Alexander Edward and
                  Ayman Shafik and
                  Samuel Palermo and
                  Jos{\'{e}} Silva{-}Mart{\'{\i}}nez},
  title        = {A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband
                  Low-Power Highly Efficient Common-Gate Summing Stage},
  journal      = {{IEEE} J. Solid State Circuits},
  volume       = {52},
  number       = {3},
  pages        = {657--668},
  year         = {2017},
  url          = {https://doi.org/10.1109/JSSC.2016.2634700},
  doi          = {10.1109/JSSC.2016.2634700},
  timestamp    = {Sun, 30 Aug 2020 00:13:11 +0200},
  biburl       = {https://dblp.org/rec/journals/jssc/Briseno-Vidrios17.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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