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BibTeX record journals/tcad/LoweG98
@article{DBLP:journals/tcad/LoweG98, author = {Kerry S. Lowe and P. Glenn Gulak}, title = {A joint gate sizing and buffer insertion method for optimizing delay and power in {CMOS} and BiCMOS combinational logic}, journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.}, volume = {17}, number = {5}, pages = {419--434}, year = {1998}, url = {https://doi.org/10.1109/43.703932}, doi = {10.1109/43.703932}, timestamp = {Thu, 24 Sep 2020 11:27:29 +0200}, biburl = {https://dblp.org/rec/journals/tcad/LoweG98.bib}, bibsource = {dblp computer science bibliography, https://dblp.org} }
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