BibTeX record journals/tvlsi/HsiehWCC16

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@article{DBLP:journals/tvlsi/HsiehWCC16,
  author       = {Tong{-}Yu Hsieh and
                  Chih{-}Hao Wang and
                  Tsung{-}Liang Chih and
                  Ya{-}Hsiu Chi},
  title        = {A Performance Degradation Tolerable Cache Design by Exploiting Memory
                  Hierarchies},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {24},
  number       = {2},
  pages        = {784--788},
  year         = {2016},
  url          = {https://doi.org/10.1109/TVLSI.2015.2410218},
  doi          = {10.1109/TVLSI.2015.2410218},
  timestamp    = {Wed, 11 Mar 2020 18:18:42 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/HsiehWCC16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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