BibTeX record journals/tvlsi/ParkZEO16

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@article{DBLP:journals/tvlsi/ParkZEO16,
  author       = {Jaeyoung Park and
                  Tianhao Zheng and
                  Mattan Erez and
                  Michael Orshansky},
  title        = {Variation-Tolerant Write Completion Circuit for Variable-Energy Write
                  {STT-RAM} Architecture},
  journal      = {{IEEE} Trans. Very Large Scale Integr. Syst.},
  volume       = {24},
  number       = {4},
  pages        = {1351--1360},
  year         = {2016},
  url          = {https://doi.org/10.1109/TVLSI.2015.2449739},
  doi          = {10.1109/TVLSI.2015.2449739},
  timestamp    = {Mon, 05 Feb 2024 20:25:48 +0100},
  biburl       = {https://dblp.org/rec/journals/tvlsi/ParkZEO16.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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