BibTeX record journals/vlsisp/BanerjeeD13

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@article{DBLP:journals/vlsisp/BanerjeeD13,
  author       = {Ayan Banerjee and
                  Anindya Sundar Dhar},
  title        = {Pipelined {VLSI} Architecture using {CORDIC} for Transform Domain
                  Equalizer},
  journal      = {J. Signal Process. Syst.},
  volume       = {70},
  number       = {1},
  pages        = {39--48},
  year         = {2013},
  url          = {https://doi.org/10.1007/s11265-012-0657-7},
  doi          = {10.1007/S11265-012-0657-7},
  timestamp    = {Mon, 21 Aug 2023 15:51:20 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BanerjeeD13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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