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ORCID14th IEEE Symposium on Computer Arithmetic 1999: Adelaide, Australia
- 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 14-16 April 1999, Adelaide, Australia. IEEE Computer Society 1999, ISBN 0-7695-0116-8
Invited Talk
- Richard P. Brent:
Computer Arithmetic - A Programmer's Perspective. 2-
Processor Enhancements
- Shane Story, Ping Tak Peter Tang:
New Algorithms for Improved Transcendental Functions on IA-64. 4-11 - Martin S. Schmookler, Michael Putrino, Anh Mather, Jon Tyler, Huy Van Nguyen, Charles Roth, Mukesh Sharma, Mydung N. Pham, Jeff Lent:
A Low-Power, High-Speed Implementation of a PowerPC(tm) Microprocessor Vector Extension. 12-
Addition
- Dhananjay S. Phatak, Israel Koren:
Intermediate Variable Encodings that Enable Multiplexor-Based Implementations of Two Operand Addition. 22-29 - Simon Knowles:
A Family of Adders. 30-34 - Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim
:
Reduced Latency IEEE Floating-Point Standard Adder Architectures. 35-
Division
- Alexandre F. Tenca, Milos D. Ercegovac:
On the Design of High-Radix On-Line Division for Long Precision. 44-51 - Paolo Montuschi, Tomás Lang:
Boosting Very-High Radix Division with Prescaling and Selection by Rounding. 52-59 - Alberto Nannarelli, Tomás Lang:
Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. 60-
Cryptography and Graphics
- Thomas Blum:
Montgomery Modular Exponentiation on Reconfigurable Hardware. 70-77 - Colin D. Walter:
Moduli for Testing Implementations of the RSA Cryptosystem. 78-85 - Naofumi Takagi, Seiji Kuwahara:
Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector. 86-
Divide and Square Root
- Marius A. Cornea-Hasegan, Roger A. Golliver, Peter W. Markstein:
Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms. 96-105 - Stuart F. Oberman:
Floating Point Division and Square Root Algorithms and Implementation in the AMD-K7 Microprocessor. 106-115 - Martin S. Schmookler, Ramesh C. Agarwal, Fred G. Gustavson:
Series Approximation Methods for Divide and Square Root in the Power3(TM) Processor. 116-123 - Michael J. Schulte, Kent E. Wires:
High-Speed Inverse Square Roots. 124-
Number Systems
- Aryan Saed, Majid Ahmadi, Graham A. Jullien:
Arithmetic with Signed Analog Digits. 134-141 - John N. Coleman, E. I. Chester:
A 32-Bit Logarithmic Arithmetic Unit and its Performance Compared to Floating-Point. 142-151 - Peter Kornerup:
Necessary and Sufficient Conditions for Parallel, Constant Time Conversion and Addition. 152-
Residue Number Systems
- Reto Zimmermann:
Efficient VLSI Implementation of Modulo (2^n=B11) Addition and Multiplication. 158-167 - Manish Bhardwaj, Thambipillai Srikanthan, Christopher T. Clarke:
A Reverse Converter for the 4-moduli Superset {2n-1, 2n, 2n+1, 2n+1+1}. 168-175 - Manish Bhardwaj, Thambipillai Srikanthan, Christopher T. Clarke:
VLSI Costs of Arithmetic Parallelism: A Residue Reverse Conversion Perspectiv. 176-
CORDIC Algorithms
- Javier Hormigo, Julio Villalba, Emilio L. Zapata:
Interval Sine and Cosine Functions Computation Based on Variable-Precision CORDIC Algorithm. 186-193 - David Lewis:
Complex Logarithmic Number System Arithmetic Using High-Radix Redundant CORDIC Algorithms. 194-203 - Elisardo Antelo, Tomás Lang, Javier D. Bruguera:
Very-High Radix CORDIC Vectoring with Scalings and Selection by Rounding. 204-
Multiplication and Rounding
- Jeng-Jong J. Lue, Dhananjay S. Phatak:
Area x Delay (A T) Efficient Multiplier Based on an Intermediate Hybrid Signed-Digit (HSD-1) Representation. 216-224 - Guy Even, Peter-Michael Seidel:
A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication. 225-232 - Cristina Iordache, David W. Matula:
On Infinitely Precise Rounding for Division, Square Root, Reciprocal and Square Root Reciprocal. 233-240 - Michael Parks:
Number-Theoretic Test Generation for Directed Rounding. 241-
Floating Point
- Marc Daumas:
Multiplications of Floating Point Expansions. 250-257 - Eric M. Schwarz, Ronald M. Smith, Christopher A. Krygowski:
The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures. 258-265 - Guenter Gerwig, Michael Kroener:
Floating-Point Unit in Standard Cell Design with 116 Bit Wide Dataflow. 266-
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