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10th ASICON 2013: Shenzhen, China
- IEEE 10th International Conference on ASIC, ASICON 2013, Shenzhen, China, October 28-31, 2013. IEEE 2013, ISBN 978-1-4673-6415-7
- Wenhua Qiang, Qi Zhang, Wei Miao, Guohong Li, Hui Wang, Songlin Feng:
A power-constrained contrast enhancement algorithm for AMOLED display using histogram segmentation. 1-4 - Wei Zhou, Jianming Yu, Jie Lin, Zhiyi Yu, Xiaoyang Zeng:
A 2D mesh NoC with self-configurable and shared-FIFOs routers. 1-4 - Haopeng Liu, Weiguang Sheng, Weifeng He, Zhigang Mao:
Delay hidden techniques based on configuration contexts reuse and differential reconfiguration in coarse-grained reconfigurable processor. 1-4 - You Li, Feng Zhang, Yumei Zhou:
A novel equalizer for the high-loss backplane at Nyquist frequency. 1-4 - Shengyou Zhong, Libin Yao, Jiqing Zhang:
A small-area low-power ADC array for image sensor applications. 1-4 - Peng Chen, Rui Guan, Dongpo Chen:
AVCO with F-V linearization techniques for CNS application. 1-4 - Zhaoyang Pi, Lun Zhu, Jingwei Zhang, Dongping Wu, David Wei Zhang, Zhi-Bin Zhang, Shi-Li Zhang:
Ultra-low frequency P(VDF-TrFE) piezoelectric energy harvester on flexible substrate. 1-4 - Xuelong Zhang, Pengjun Wang, Yuejun Zhang:
Highly stable data SRAM-PUF in 65nm CMOS process. 1-4 - Zongyan Wang, Dexue Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A fast multi-core virtual platform and its application on software development. 1-4 - Jian Li, Xiangyu Zeng, Jia Zhou:
Simulation design for continuous separating and 3D focusing of particles based on inertial microfluidics. 1-4 - Yan Zhao, Xiaofang Zhou, Chao Lu:
A new channel emulator for low voltage broadband power line communication. 1-4 - Yuanyuan Li, Ning Xu, Yuchun Ma, Jinian Bian:
Incremental 3D NoC synthesis based on physical-aware router merging algorithm. 1-4 - Shikai Zhu, Zheng Yu, Shile Cui, Zhiyi Yu, Xiaoyang Zeng:
H.264 video parallel decoder on a 24-core processor. 1-4 - Xuan Yang, Xiaole Cui, Chao Wang, Chung Len Lee:
A test pattern selection method for dynamic burn-in of logic circuits based on ATPG technique. 1-4 - Nan Wang, Cong Hao, Nan Liu, Haoran Zhang, Takeshi Yoshimura:
Timing and resource constrained leakage power aware scheduling in high-level synthesis. 1-4 - Huatao Zhao, Jiongyao Ye, Yuxin Sun, Takahiro Watanabe:
Pseudo Dual Path Processing to reduce the branch misprediction penalty in embedded processors. 1-4 - Tianlong Ma, Cong Liu, Yibo Fan, Xiaoyang Zeng:
A fast 8×8 IDCT algorithm for HEVC. 1-4 - Xiaozong Huang, Luncai Liu, Liu Fan, Jing Zhang, Wengang Huang, Yanlin Zhang, Lei Yu:
A proposed data converter for current signal with temperature-compensated sample resistor. 1-3 - Jixuan Xiang, Jian Mei, Hao Chang, Fan Ye:
A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC. 1-4 - Xinsheng Wang, Mingyang Hu, Mingyan Yu:
Robust current-mode on-chip interconnect signaling scheme in deep submicron. 1-4 - Xiaohao Gao, Takeshi Yoshimura:
Genetic Algorithm based pipeline scheduling in high-level synthesis. 1-4 - Dexue Zhang, Xiaoyang Zeng, Zongyan Wang, Weike Wang, Xinhua Chen:
MCVP-NoC: Many-Core Virtual Platform with Networks-on-Chip support. 1-4 - Hong-Wun Gao, Te-Kuang Chiang:
A novel scaling theory for fully-depleted omega-gate (ΩG) MOSFETs. 1-3 - Fei Sun, Pengjun Wang, Haizhen Yu:
Best polarity searching for ternary FPRM logic circuit area based on whole annealing genetic algorithm. 1-4 - Yong Xu, Fei Zhao, Chen Hu, Zheng Sun, Yuanliang Wu, Jianwen Lu:
Design of frequency synthesizer in frequency-hopping transceiver. 1-4 - Jian Lv, Simon S. Ang:
Design philosophy of hysteretic controller for DC-DC switching converters. 1-4 - Shengye Wang, Wei Cao, Lingli Wang, Na Wang, Ping Tao:
A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly. 1-4 - Bing Jing, Hao Chen, Fan Ye, Ning Li, Junyan Ren:
Low-complexity synchronizer used in DC-OFDM UWB system. 1-4 - Renfeng Dou, Yifan Bo, Jun Han, Xiaoyang Zeng:
Design of a high throughput configurable variable-length FFT processor based on switch network architecture. 1-4 - Maoqiang Duan, Xiaoli Huang, Zhijia Yang:
A GFSK transceiver for IEEE Std. 802.15.4g used in China. 1-4 - Jiajia Shao, Liji Wu, Xiangmin Zhang:
Design and implementation of RSA for dual interface bank IC card. 1-4 - Daying Sun, Weifeng Sun, Qing Wang, Shen Xu, Shengli Lu:
A novel digital controller for boost PFC converter with high power factor and fast dynamic response. 1-4 - Makoto Ikeda:
Self-synchronous circuit designs, SSFPGA and SSRSA for low voltage autonomous control and tamper resistivity. 1-4 - Yang Zhao, Bill Yang Liu, Zhiliang Hong:
Design of a time-interleaved band-pass ΣΔ modulator for Class-S power amplifier. 1-4 - Haofan Yang, Kedong Chen, Shengqiong Xie, Ming-e Jing, Zhiyi Yu, Xiaoyang Zeng:
Efficient implementation of 3780-point FFT on a 16-core processor. 1-4 - Zhe Chen, Jie Yang, Cong Shi, Nanjian Wu:
A novel architecture of local memory for programmable SIMD vision chip. 1-4 - Yingrui Chen, Teng Wang, Xin'an Wang, Ziyi Hu:
Implementation of an embedded dual-core processor for portable medical electronics applications. 1-4 - Jian Mei, Jixuan Xiang, Huabin Chen, Fan Ye, Junyan Ren:
A 4-mW8-b 600-MS/s 2-b-per-cycle SAR ADC with a capacitive DAC. 1-4 - Minoru Fujishima:
Low-power high-speed communication with short-millimeter-wave CMOS transceivers. 1-4 - Shota Matsuno, Masashi Tawada, Masao Yanagisawa, Shinji Kimura, Nozomu Togawa, Tadahiko Sugibayashi:
Energy evaluation for two-level on-chip cache with non-volatile memory on mobile processors. 1-4 - Kaidi Zhang, Guowei Tao, Xiangyu Zeng, Wenjie Sheng, Jia Zhou:
Compact and portable chemiluminescence detector for glucose. 1-4 - He Tang, Yong Peng, Xiang Lu, Hai Wang, Albert Z. Wang:
Quantitative analysis for high speed interpolated/averaging ADC. 1-4 - Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai:
Variation-aware subthreshold logic circuit design. 1-4 - Qi Wang, Quanquan Li, Shi Chen, Tiejun Zhang, Chaohuan Hou:
An optimized hardware architecture for intra prediction in H.264 decoder. 1-4 - Zhengxiong Hou, Yipeng Wang, Quan Pan, C. Patrick Yue:
A 25-Gb/s 32.1-dB CMOS limiting amplifier for integrated optical receivers. 1-4 - Xiantuo Rao, Teng Wang, Xin'an Wang, Yinhui Wang:
A low-power and high-efficiency cache design for embedded bus-based symmetric multiprocessors. 1-4 - Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Liji Wu, Zhihua Wang:
A 10-Gb/s simplified transceiver with a quarter-rate 4-tap decision feedback equalizer in 0.18-μm CMOS technology. 1-4 - Masataka Miyake, Kai Matsuura, Akifumi Ueno:
Compact modeling of the diode reverse recovery effect for leading developments of power electronic applications. 1-4 - Zitao Shi, Xin Wang, Albert Z. Wang, Yuhua Cheng:
A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique. 1-4 - Rui He, Jianfei Xu, Na Yan, Min Hao:
A 20 Gb/s Limiting Amplifier in 65nm CMOS technology. 1-4 - Siqiang Fan, Albert Z. Wang, Bin Zhao:
Folding and interpolation ADC design methodology. 1-4 - Di Wu, Yun Chen, Yuebin Huang, Yeong-Luh Ueng, Li-Rong Zheng, Xiaoyang Zeng:
A high-throughput LDPC decoder for optical communication. 1-4 - Guangyi Lu, Yuan Wang, Jian Cao, Song Jia, Ganggang Zhang, Xing Zhang:
Novel gate-voltage-bias techniques for gate-coupled MOS (GCMOS) ESD protection circuits. 1-4 - Nagarajan Mahalingam, Yisheng Wang, Kaixue Ma, Shouxian Mou, Kiat Seng Yeo:
A 24 GHz reconfigurable frequency synthesizer for 60 GHz WPAN. 1-4 - Ze-kun Zhou, Haiwu Xie, Yue Shi, Chuankui Wu, Jiangang Huang, Xin Ming, Bo Zhang:
A high-performance current sensing circuit with full-phase sampling capability. 1-4 - Sen Li, Jinguang Jiang, Xifeng Zhou, Zeyu Zhang:
Current-mode square-wave converter with current-rectifying function employing MOCCII. 1-4 - Jianguo Yang, Ying Meng, Xiaoyong Xue, Ryan Huang, Q. T. Zhou, J. G. Wu, Yinyin Lin:
A 2Mb ReRAM with two bits error correction codes circuit for high reliability application. 1-4 - Shuang Yu, Fen Ge, Gui Feng, Ning Wu:
A two-phase floorplanning approach for Application-specific Network-on-Chip. 1-4 - Shili Wu, Xiaowei He, Yuwei Liu, Guoan Chen:
Polarity dependent of gate oxide breakdown from measurements. 1-2 - Chaojie Fan, Wenjie Pan, Ke Wang, Jianjun Zhou:
Digital calibration techniques for interstage gain nonlinearity in pipelined ADCs. 1-4 - Jiajia Jiao, Yuzhuo Fu:
A cost-effective method for masking transient errors in NoC flit type. 1-4 - Meng-Chou Chang, Shih-Ju Tsai:
A low-power ternary content-addressable memory using pulse current based match-line sense amplifiers. 1-4 - Frank Schwierz:
Transition metal dichalcogenides - A new material class for semiconductor electronics? 1-4 - Gui Feng, Fen Ge, Shuang Yu, Ning Wu:
A thermal-aware mapping algorithm for 3D Mesh Network-on-Chip architecture. 1-4 - Chenlu Wu, Wei Cao, Xuegong Zhou, Lingli Wang, Fang Wang, Baodi Yuan:
A reconfigurable floating-point FFT architecture. 1-4 - Sujuan Liu, Meihui Zhang, Wenshu Jiang, Junshan Wang, Peipei Qi:
Theory and hardware implementation of an analog-to-Information Converter based on Compressive Sensing. 1-4 - Alvin Joseph, Randy Wolf:
Integrated silicon RF front-end solutions for mobile communications. 1-4 - Wenjian Yu:
RWCap2: Advanced floating random walk solver for the capacitance extraction of VLSI interconnects. 1-4 - Dian Zhou, Guanming Huang:
Design automation of analog circuit considering the process variations. 1-4 - Jifa Hao, T. E. Kopley:
Building-in reliability in BCD (Bipolar-CMOS-DMOS) technologies. 1-4 - Wenjian Yu, Siyu Yang, Qingqing Zhang:
Analytical model of the coupling capacitance between cylindrical through silicon via and horizontal interconnect in 3D IC. 1-4 - Liwei Gong, Yuan Xu, Zhi Zhang, Weiwei Shi, Robert K. F. Teng:
An open 45nm PD-SOI standard cell library based on verified BSIM SOI spice model with predictive technology. 1-4 - Baoguang Liu, Yuan Wang, Guangliang Guo, Song Jia, Xing Zhang:
A novel dynamic element match technique in current-steering DAC. 1-4 - Yanzhao Ma, Shaoxi Wang, Shengbing Zhang, Xiaoya Fan:
An automatic peak-valley current mode step-up/step-down DC-DC converter with smooth transition. 1-4 - Jung-Hun Seo, Weidong Zhou, Zhenqiang Ma:
Toward microwave integrated circuits on flexible substrates (invited). 1-4 - Yunpu Hu, Songping Mai, Yixin Zhao, Chun Zhang:
Low-resistance wide-voltage-range analog switch for implantable neural stimulators. 1-4 - Zhengyu Qian, Xiaole Cui, Bo Wang, Xiangrong Zhang, Chung Len Lee:
A folded current-reused CMOS power amplifier for low-voltage 3.0-5.0 GHz UWB applications. 1-4 - Hao Zhuang, Shih-Hung Weng, Chung-Kuan Cheng:
Power grid simulation using matrix exponential method with rational Krylov subspaces. 1-4 - Nan-Xiong Huang, Hsi Rong Han, Wen Tui Liao, Chih-Hung Huang, Wen Chun Wang, Miin-Shyue Shiau, Ching-Hwa Cheng, Hong-Chong Wu, Heng-Shou Hsu, Juin J. Liou, Shry-Sann Liao, Ruei-Cheng Sun, Guang-Bao Lu, Don-Gey Liu:
Integrated amorphous-Si TFT circuits for gate drivers on LCD panels. 1-4 - Wenqing Lu, Gerald E. Sobelman, Xiaofang Zhou, Junyan Ren:
FFT design for OFDM-based cognitive radio using a reconfigurable baseband processing architecture. 1-4 - Liuxi Qian, Dian Zhou, Xuan Zeng, Fan Yang, Shengguo Wang:
A parallel sparse linear system solver for large-scale circuit simulation based on Schur Complement. 1-4 - Ting Li, Dongbing Fu, Yong Zhang, Yan Wang, Lu Liu, Xu Wang:
A high-speed front-end circuit used in a 16bit 250MSPS pipelined ADC. 1-4 - Weijie Chen, Hailong Yao, Yici Cai, Qiang Zhou:
Analog routing considering min-area constraint. 1-4 - Yuan Xu, Jinsong Liu, Liwei Gong, Zhi Zhang, Robert K. F. Teng:
A high performance VLSI architecture for integer motion estimation in HEVC. 1-4 - Hengzhou Yuan, Zhuo Ma, Yang Guo:
An adaptive multi-modulus frequency divider. 1-4 - Lele Jiang, Song Wen, Wei Tai, Wang Lei, Lifu Chang, Yuhua Cheng:
Device parameter variations of n-MOSFETS with dog-bone layouts in 65nm and 40nm technologies. 1-3 - Takashi Sato:
Statistical simulation methods for circuit performance analysis. 1-4 - Jianfeng Chen, Yuhua Yu, Xiangyu Zeng, Jian Li, Jia Zhou:
Evaluation of Cyanoethyl Pullulan material as the dielectric layer for EWOD devices. 1-4 - Tao Cheng, Tao Yang, Xin Wang, Zhangwen Tang:
A wideband CMOS variable-gain low noise amplifier with novel attenuator. 1-4 - Chong Huang, Xiaochen Gu, Lei Cai, Cong Li, Dun Yan, Bingbing Zhang, Qin Qin, Hongyi Wang, Jiancheng Li:
A high conversion coefficient RF front end of ultra-low power RFID tag. 1-4 - Zuochang Ye:
Pmm: A Matlab toolbox for passive macromodeling in RF/mm-wave circuit design. 1-4 - Zhiyuan Xue, Huan Ying, Yingke Gao, Tiejun Zhang, Donghui Wang, Chaohuan Hou:
A design of configurable image enhancement unit. 1-4 - Tongning Hu, Bo Wang, Ke Lin, Yi Peng, Xin'an Wang:
A three-stage LDO with active feedback frequency compensation and slew-rate enhancement. 1-4 - Leiou Wang:
A new fast median filtering algorithm based on FPGA. 1-4 - Hui Li, Wei Zhu, Ningxi Liu, Cunlin Dong, Chao Meng, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu:
Novel operation scheme and technological optimization for 1T bulk capacitor-less DRAM. 1-3 - Yingke Gao, Diancheng Wu, Quanquan Li, Tiejun Zhang, Chaohuan Hou:
Design and implementation of transaction level processor based on UVM. 1-4 - Huagang Li, Jian Wang, Jinmei Lai:
Weight-based FPGA placement algorithm with wire effect considered. 1-4 - Richard Wong, Rita Fung, Shi-Jie Wen:
Networking industry trends in ESD protection for high speed IOs. 1-4 - Weijing Shi, Yi Li, Jun Han, Xu Cheng, Xiaoyang Zeng:
An extensible and real-time compressive sensing reconstruction hardware for WBANs using OMP. 1-4 - Jieliang Lu, Qin Wang, Jing Xie, Zhigang Mao:
TSVs-aware floorplanning for 3D integrated circuit. 1-4 - Peng-Fei Nan, Xu Wang, Xin-Ping Qu:
Ag dendrite formed on the Cu pyramids as SERS substrate. 1-3 - Haoran Zhang, Cong Hao, Nan Wang, Song Chen, Takeshi Yoshimura:
Power and resource aware scheduling with multiple voltages. 1-4 - Lingzhi Fu, Xiao Yan, Junyu Wang:
A collision and tag number detector for UHF RFID reader conforming to EPC Gen2 protocol. 1-4 - Xiaofei Chen, Yading Shen, Xuecheng Zou, Shuang-Xi Lin, Wanghui Zou:
A new high performance RF LDMOS with vertical n+n-p-p+ drain structure. 1-4 - Qing Zhang, Xueqiu Yu, Zhiyi Yu, Xiaoyang Zeng:
A turbo decoder implementation for LTE downlink mapped on a multi-core processor platform. 1-4 - Wenzhe Zhao, Minjie Lv, Hongbin Sun, Nanning Zheng, Tong Zhang:
VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder. 1-4 - Yibo He, Xiaole Cui, Chung Len Lee, Xiaoxin Cui, Yufeng Jin:
New DfT architectures for 3D-SICs with a wireless test port. 1-4 - Ran Zhang, Xue Wei, Takahiro Watanabe:
A sorting-based IO connection assignment for flip-chip designs. 1-4 - Yangyang Guo, Liji Wu, Tengfei Zhai, Xiao Yu, Xiangmin Zhang:
Mixed-signal SoC design and low power research for tire pressure monitoring systems. 1-4 - Anwen Huang, Chao Song, Wei Guo, Peng Li, Minxuan Zhang:
An interference miss isolation mechanism based on skewed mapping for shared cache in Chip Multiprocessors. 1-4 - Shanshan Yong, Xin'an Wang, Ying Cao, Yawei Lu, Zheng Xie:
An integrated development environment for reconfigurable operators array. 1-4 - Xingpeng Pan, Rui Guan, Dongpo Chen:
A CMOS PGA with DCOC and I/Q mismatch calibration. 1-4 - D. Y. Lu, X. A. Tran, H. Y. Yu, D. M. Huang, Yung-Yang Lin, S. J. Ding, P. F. Wang, Ming-Fu Li:
Conduction mechanism of self-rectifying n+Si-HfO2-Ni RRAM. 1-4 - Chun-Min Zhang, Qing-Qing Sun, Peng-Fei Wang, David Wei Zhang:
PEALD Ru/RuOx films for ULSI applications and its transition control between metal and metal oxide. 1-4 - Jinmei Lai, Yanquan Luo, Qi Shao, Lichun Bao, Xueling Liu:
A high-resolution TDC implemented in a 90nm process FPGA. 1-3 - Si Chen, Xiaole Cui, Chung Len Lee:
A novel test scheme for NAND flash memory based on built-in oscillator ring. 1-4 - Thomas Wong, Tao Shen:
Network functions for characterization of elementary semiconductor nanostructures. 1-4