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ORCID7th ASYNC 2001: Salt Lake City, UT, USA
- 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 11-14 March 2001, Salt Lake City, UT, USA. IEEE Computer Society 2001, ISBN 0-7695-1034-5
Mark Greenstreet
- Bill Athas:
Asynchronous Design and the Pursuit of Low Power. 2-
Systems/Arithmetic
- Mike J. G. Lewis, L. E. M. Brackenbury:
Exploiting Typical DSP Data Access Patterns and Asynchrony for a Low Power Multiported Register Bank. 4-14 - Peter A. Riocreux, L. E. M. Brackenbury, J. Mike Cumpstey, Stephen B. Furber
:
A Low-Power Self-Timed Viterbi Decoder. 15-24 - Gianluca Cornetta, Jordi Cortadella:
A Multi-Radix Approach to Asynchronous Division. 25-
Experiments
- David W. Lloyd, Jim D. Garside:
A Practical Comparison of Asynchronous Design Styles. 36-45 - Ivan E. Sutherland, Scott Fairbanks:
GasP: A Minimal FIFO Control. 46-53 - Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri:
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. 54-
Synthesis and Verification
- Chris J. Myers, Hans M. Jacobson:
Efficient Exact Two-Level Hazard-Free Logic Minimization. 64-73 - Robert Berks, Radu Negulescu:
Partial-Order Correctness-Preserving Properties of Delay-Insensitive Circuits. 74-
Handshaking
- Ad M. G. Peeters, Kees van Berkel:
Synchronous Handshake Circuits. 86-95 - Rajit Manohar:
An Analysis of Reshuffled Handshaking Expansions. 96-
Communication
- Joep L. W. Kessels, Ad M. G. Peeters, Torsten Kramer, Markus Feuser, Klaus Ully:
Designing an Asynchronous Bus Interface. 108-117 - W. J. Bainbridge, Stephen B. Furber:
Delay Insensitive System-on-Chip Interconnect using 1-of-4 Data Encoding. 118-126 - Alexandre Yakovlev, Fei Xia, Delong Shang:
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism. 127-
Invited Session 2
- Kevin Normoyle:
Where are the Async Millionaires? 138-
Architecture
- Tony Werner, Venkatesh Akella:
An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. 140-151 - Daranee Hormdee, Jim D. Garside:
AMULET3i Cache Architecture. 152-161 - Motokazu Ozawa, Masashi Imai, Hiroshi Nakamura, Takashi Nanya, Yoichiro Ueno:
Performance Evaluation of Cascade ALU Architecture for Asynchronous Super-Scalar Processors. 162-172 - William S. Coates, Jon K. Lexau, Ian W. Jones, Scott M. Fairbanks, Ivan E. Sutherland:
FLEETzero: An Asynchronous Switching Experiment. 173-
Performance Analysis and Optimization
- Ivan E. Sutherland, Jon K. Lexau:
Designing Fast Asynchronous Circuits. 184-193 - Jo C. Ebergen:
Squaring the FIFO in GasP. 194-205 - Mark R. Greenstreet, Brian de Alwis:
How to Achieve Worst-Case Performance. 206-
Invited Session
- Ajay Koche:
Testing Asynchronous Circuits: Help is on the Way! 218-
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