default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDCASES 2018: Torino, Italy
- Tulika Mitra, Akash Kumar:
Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems, CASES 2018, Torino, Italy, September 30 - October 05, 2018. ACM 2018, ISBN 978-1-5386-5564-1 - Chao Wu, Cheng Ji, Qiao Li, Chenchen Fu, Chun Jason Xue:
Maximizing I/O throughput and minimizing performance variation via reinforcement learning based I/O merging for SSDs: work-in-progress. 1:1-1:2 - Junlong Wang, Wei Jiang, Jinyu Zhan, Jinghuan Yu, Haibo Hu, Liugen Xu:
Persistence improvement for distributed cache with NVM based storage system: work-in-progress. 2:1-2:3 - Gianvito Urgese, Luca Peres, Francesco Barchi, Enrico Macii, Andrea Acquaviva:
Multiple alignment of packet sequences for efficient communication in a many-core neuromorphic system: work-in-progress. 3:1-3:2 - Francesco Barchi, Gianvito Urgese, Enrico Macii, Andrea Acquaviva:
Impact of graph partitioning on SNN placement for a multi-core neuromorphic architecture: work-in-progress. 4:1-4:2 - Ilaria Scarabottolo, Giovanni Ansaloni, Laura Pozzi:
A partitioning strategy for exploring error-resilience in circuits: work-in-progress. 5:1-5:2 - Pengfei Yang, Quan Wang, Xiaokun Huang, Xin Mi:
An confidentiality and integrity scheme for the distributed shared memory of embedded multi-core system: work in progress. 6:1-6:2 - Julian Oppermann, Sebastian Vollbrecht, Melanie Reuter-Oppermann, Oliver Sinnen, Andreas Koch:
GeMS: a generator for modulo scheduling problems: work in progress. 7:1-7:3 - Kana Shimada, Ittetsu Taniguchi, Hiroyuki Tomiyama:
Communication-aware scheduling of data-parallel tasks: work-in-progress. 8:1-8:2 - Vanishree K, Madhura Purnaprajna:
Performance modeling for data distribution in heterogeneous computing systems: work in progress. 9:1-9:3 - Gaurav Chadha:
EPerf: energy-efficient execution of user-interactive event-driven applications: work in progress. 10:1-10:3 - Yixin Li, Jinyu Zhan, Wei Jiang, Ying Li:
Writing-aware data variable allocation on hybrid SRAM+NVM SPM: work-in-progress. 11:1-11:2 - Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy:
DRAM cache access optimization leveraging line locking in tag cache: work-in-progress. 12:1-12:3 - Sheng-Yu Fu, Chih-Min Lin, Ding-Yong Hong, Yu-Ping Liu, Jan-Jan Wu, Wei-Chung Hsu:
Exploiting SIMD capability in an ARMv7-to-ARMv8 dynamic binary translator. 14:1-14:3 - Ferdinand Brasser, Lucas Davi, Abhijitt Dhavlle, Tommaso Frassetto, Sai Manoj Pudukotai Dinakarrao, Setareh Rafatirad, Ahmad-Reza Sadeghi, Avesta Sasan, Hossein Sayadi, Shaza Zeitouni, Houman Homayoun:
Advances and throwbacks in hardware-assisted security: special session. 15:1-15:10
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2026-01-07 21:50 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
