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ORCIDCICC 2015: San Jose, California, USA
- 2015 IEEE Custom Integrated Circuits Conference, CICC 2015, San Jose, CA, USA, September 28-30, 2015. IEEE 2015, ISBN 978-1-4799-8682-8
- Dong-Uk Lee, Kang Seol Lee, Yongwoo Lee, Kyung Whan Kim, Jong-Ho Kang, Jaejin Lee, Jun Hyun Chun:
Design considerations of HBM stacked DRAM and the memory architecture extension. 1-8 - Junho Cheon, Insoo Lee, Changyong Ahn, Milos Stanisavljevic, Aravinthan Athmanathan, Nikolaos Papandreou, Haris Pozidis, Evangelos Eleftheriou, Min-Chul Shin, Taekseung Kim, Jong-Ho Kang, Jun Hyun Chun:
Non-resistance metric based read scheme for multi-level PCRAM in 25 nm technology. 1-4 - John K. DeBrosse, Thomas M. Maffitt, Yutaka Nakamura, Guenole Jan, Po-Kang Wang:
A fully-functional 90nm 8Mb STT MRAM demonstrator featuring trimmed, reference cell-based sensing. 1-3 - Haruki Mori, Tomoki Nakagawa, Yuki Kitahara, Yuta Kawamoto, Kenta Takagi
, Shusuke Yoshimoto, Shintaro Izumi, Koji Nii, Hiroshi Kawaguchi, Masahiko Yoshimoto:
A 298-fJ/writecycle 650-fJ/readcycle 8T three-port SRAM in 28-nm FD-SOI process technology for image processor. 1-4 - Yuan-Hung Chung, Che-Hung Liao, Chun-Wei Lin, Yi-Shing Shih, Chin-Fu Li, Meng-Hsiung Hung, Ming-Chung Liu, Pi-An Wu, Jui-Lin Hsu, Ming-Yeh Hsu, Sheng-Hao Chen, Po-Yu Chang, Chih-Hao Chen, Yu-Hsien Chang, Jun-Yu Chen, Tao-Yao Chang, George Chien:
A dual-band 802.11abgn/ac transceiver with integrated PA and T/R switch in a digital noise controlled SoC. 1-8 - Jong Seok Park, Song Hu, Yanjie Wang, Hua Wang:
A highly linear dual-band mixed-mode polar power amplifier in CMOS with an ultra-compact output network. 1-4 - Junlei Zhao, Matteo Bassi, Andrea Mazzanti, Francesco Svelto:
A 15 GHz-bandwidth 20dBm PSAT power amplifier with 22% PAE in 65nm CMOS. 1-4 - Seyed Yahya Mortazavi, Kwang-Jin Koh:
A 28-GHz inverse class-F power amplifier with coupled-inductor based harmonic impedance modulator. 1-4 - Thomas E. Sarvey, Yang Zhang, Li Zheng, Paragkumar Thadesar, Ravi Gutala, Colman Cheung, Arifur Rahman, Muhannad S. Bakir:
Embedded cooling technologies for densely integrated electronic systems. 1-8 - Vinay Vashishtha, Lawrence T. Clark, Srivatsan Chellappa, Anudeep R. Gogulamudi, Aditya Gujja, Chad Farnsworth:
A soft-error hardened process portable embedded microprocessor. 1-4 - Frank Hsiao, Adrian Tang, Y. Kim, Brian J. Drouin, Goutam Chattopadhyay, M.-C. Frank Chang:
A 2.2 GS/s 188mW spectrometer processor in 65nm CMOS for supporting low-power THz planetary instruments. 1-3 - Jeffrey Tyhach, Mike Hutton, Sean Atsatt, Arifur Rahman, Brad Vest, David M. Lewis, Martin Langhammer, Sergey Y. Shumarayev, Tim Hoang, Allen Chan, Dong-Myung Choi, Dan Oh, Hae-Chang Lee, Jack Chui, Ket Chiew Sia, Edwin Kok, Wei-Yee Koay, Boon-Jin Ang:
Arria™ 10 device architecture. 1-8 - Jinghua Yang, Joseph Davis, Niranjan Kulkarni, Jae-sun Seo, Sarma B. K. Vrudhula:
Dynamic and leakage power reduction of ASICs using configurable threshold logic gates. 1-4 - Ke Huang, Deng Luo, Ziqiang Wang, Xuqiang Zheng, Fule Li, Chun Zhang, Zhihua Wang:
A 190mW 40Gbps SerDes transmitter and receiver chipset in 65nm CMOS technology. 1-4 - Timothy O. Dickson, Yong Liu, Ankur Agrawal, John F. Bulzacchelli, Herschel A. Ainspan, Zeynep Toprak Deniz, Benjamin D. Parker, Mounir Meghelli, Daniel J. Friedman:
A 1.8-pJ/bit 16×16-Gb/s source synchronous parallel interface in 32nm SOI CMOS with receiver redundancy for link recalibration. 1-4 - Joon-Yeong Lee, Kwangseok Han, Taeho Kim, Sangeun Lee, Jeong-Sup Lee, Taehun Yoon, Jinho Park, Hyeon-Min Bae:
A power-and-area efficient 10 × 10 Gb/s bootstrap transceiver in 40 nm CMOS for reference-less and lane-independent operation. 1-4 - Wei-Han Cho, Yilei Li, Yanghyo Kim, Po-Tsang Huang, Yuan Du, Sheau Jiung Lee, Mau-Chung Frank Chang:
A 5.4-mW 4-Gb/s 5-band QPSK transceiver for frequency-division multiplexing memory interface. 1-4 - Hyosup Won, Kwangseok Han, Sangeun Lee, Jinho Park, Hyeon-Min Bae:
An on-chip stochastic sigma-tracking eye-opening monitor for BER-optimal adaptive equalization. 1-4 - Sagar Ray, Mona Mostafa Hella:
A 0.622-10Gb/s inductorless adaptive linear equalizer with spectral tracking for data rate adaptation in 0.13-μm CMOS. 1-4 - Ahmed Elkholy, Saurabh Saxena, Romesh Kumar Nandwana, Amr Elshazly, Pavan Kumar Hanumolu:
A 4mW wide bandwidth ring-based fractional-n DPLL with 1.9psrms integrated-jitter. 1-4 - Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, An Steegen:
Holisitic device exploration for 7nm node. 1-5 - Srinivasa Banna:
Scaling challenges of FinFET technology at advanced nodes and its impact on SoC design (Invited). 1-8 - Pieter Weckx, Ben Kaczer, Praveen Raghavan, Jacopo Franco, Marko Simicic, Philippe J. Roussel, Dimitri Linten, Aaron Thean, Diederik Verkest, Francky Catthoor, Guido Groeseneken:
Characterization and simulation methodology for time-dependent variability in advanced technologies. 1-8 - Jeffrey Fredenburg, Michael P. Flynn:
ADC trends and impact on SAR ADC architecture and analysis. 1-8 - Tzu-Fan Wu, Cheng-Ru Ho, Mike Shuo-Wei Chen:
A flash-based non-uniform sampling ADC enabling digital anti-aliasing filter in 65nm CMOS. 1-4 - Somnath Kundu, Bongjin Kim, Chris H. Kim:
Two-step beat frequency quantizer based ADC with adaptive reference control for low swing bio-potential signals. 1-4 - Aaron Buchwald:
Practical considerations for application specific time interleaved ADCs. 1-8 - Shuang Zhu, Benwei Xu, Bo Wu, Kiran Soppimath, Yun Chiu:
A 0.073-mm2 10-GS/s 6-bit time-domain folding ADC in 65-nm CMOS with inherent DEM. 1-4 - Jie Fang, Shankar Thirunakkarasu, Xuefeng Yu, Fabian Silva-Rivas, Kwang Young Kim, Chaoming Zhang, Frank Singor:
A 5GS/s 10b 76mW time-interleaved SAR ADC in 28nm CMOS. 1-4 - Dragan Maksimovic, Yuanzhe Zhang, Miguel Rodriguez:
Monolithic very high frequency GaN switched-mode power converters. 1-4 - Zhidong Liu, Hoi Lee:
A 5-115V efficiency-enhanced synchronous LED driver with adaptive resonant timing control. 1-4 - Yongjie Jiang, Ayman A. Fayed:
A 1A, 20MHz/100MHz dual-inductor 4-output buck converter with fully-integrated bond-wire-based output filters for ripple reduction. 1-4 - Fan Yang, Philip K. T. Mok:
Fast-transient asynchronous digital LDO with load regulation enhancement by soft multi-step switching and adaptive timing techniques in 65-nm CMOS. 1-4 - Xingyi Hua, Ramesh Harjani:
3.5-0.5V input, 1.0V output multi-mode power transformer for a supercapacitor power source with a peak efficiency of 70.4%. 1-4 - Cheng Huang, Toru Kawajiri, Hiroki Ishikuro:
A near-optimum 13.56 MHz active rectifier with circuit-delay real-time calibrations for high-current biomedical implants. 1-4 - Mario Lok, Xuan Zhang, Elizabeth Farrell Helbling, Robert J. Wood, David M. Brooks, Gu-Yeon Wei:
A power electronics unit to drive piezoelectric actuators for flying microrobots. 1-4 - Danzhu Lu, Suyi Yao, Bin Shao:
A 110nA quiescent current buck converter with zero-power supply monitor and near-constant output ripple. 1-4 - Peter R. Kinget:
Scaling analog circuits into deep nanoscale CMOS: Obstacles and ways to overcome them. 1-8 - Hui Wang, Patrick P. Mercier:
A 51 pW reference-free capacitive-discharging oscillator architecture operating at 2.8 Hz. 1-4 - Shanshan Dai, Jacob K. Rosenstein:
A 14.4nW 122KHz dual-phase current-mode relaxation oscillator for near-zero-power sensors. 1-4 - Seongjong Kim, Mingoo Seok:
A 30.1μm2, > ±1.1°C-3σ-error, 0.4-to-1.0V temperature sensor based on direct threshold-voltage sensing for on-chip dense thermal monitoring. 1-4 - D. K. Sadana, C.-W. Cheng, B. Wacaser, W. Spratt, K. T. Shiu, Stephen W. Bedell:
Materials challenges for III-V/Si co-integrated CMOS. 1-6 - Nicholas J. Kolias:
Recent advances in Ga N MMIC technology. 1-5 - Farhang Yazdani:
A novel low cost, high performance and reliable silicon interposer. 1-6 - Paul D. Franzon, Eric Rotenberg, James Tuck, W. Rhett Davis, Huiyang Zhou, Joshua Schabel, Zhenqian Zhang, J. Brandon Dwiel, Elliott Forbes, Joonmoo Huh, Steve Lipa:
Computing in 3D. 1-6 - Rakesh Kumar Palani, Ramesh Harjani:
A 4.6mW, 22dBm IIP3 all MOSCAP based 34-314MHz tunable continuous time filter in 65nm. 1-4 - Laya Mohammadi, Kwang-Jin Koh:
2-4 GHz Q-tunable LC bandpass filter with 172-dBHz peak dynamic range, resilient to +15-dBm out-of-band blocker. 1-4 - Dongil Lee, Taeho Lee, Yong-Hun Kim, Young-Ju Kim, Lee-Sup Kim:
An injection locked PLL for power supply variation robustness using negative phase shift phenomenon of injection locked frequency divider. 1-4 - SungWon Chung, Hae-Seung Lee:
A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT. 1-4 - Muhammad Ashraful Alam, Piyush Dak, Muhammad A. Wahab, Xingshu Sun:
Physics-based compact models for insulated-gate field-effect biosensors, landau-transistors, and thin-film solar cells. 1-8 - Jongyeon Kim, An Chen, Behtash Behin-Aein, Saurabh Kumar, Jianping Wang, Chris H. Kim:
A technology-agnostic MTJ SPICE model with user-defined dimensions for STT-MRAM scalability studies. 1-4 - Ning Lu, Sungjae Lee, Richard A. Wachnik:
Symmetry breaking in the drain current of multi-finger transistors. 1-4 - Shupeng Sun, Xin Li:
Fast statistical analysis of rare circuit failure events via Bayesian scaled-sigma sampling for high-dimensional variation space. 1-4 - Ali M. Niknejad, Siva V. Thyagarajan, Elad Alon, Yanjie Wang, Christopher D. Hull:
A circuit designer's guide to 5G mm-wave. 1-8 - Xue Wu, Kaushik Sengupta:
Dynamic waveform shaping for reconfigurable radiated periodic signal generation with picosecond time-widths. 1-4 - Hyung-Min Lee, Mehdi Kiani, Maysam Ghovanloo:
Advanced wireless power and data transmission techniques for implantable medical devices. 1-8 - Behzad Dehlaghi, Anthony Chan Carusone:
A 20 Gb/s 0.3 pJ/b single-ended die-to-die transceiver in 28 nm-SOI CMOS. 1-4 - Shuai Yuan, Liji Wu, Ziqiang Wang, Xuqiang Zheng, Wen Jia, Chun Zhang, Zhihua Wang:
A 4×20-Gb/s 0.86pJ/b/lane 2-tap-FFE source-series-terminated transmitter with far-end crosstalk cancellation and divider-less clock generation in 65nm CMOS. 1-4 - Mayank Raj, Manuel Monge, Azita Emami:
A 20Gb/s 0.77pJ/b VCSEL transmitter with nonlinear equalization in 32nm SOI CMOS. 1-4 - Takashi Takemoto, Hiroki Yamashita, Yasunobu Matsuoka, Yong Lee, Masaru Kokubo:
An electrical and optical concurrent design methodology for enlarging jitter margin of 25.8-Gb/s optical interconnects. 1-4 - Won Ho Choi, Hoon Ki Kim, Chris H. Kim:
Circuit techniques for mitigating short-term vth instability issues in successive approximation register (SAR) ADCs. 1-4 - Ahmed Benhassain, Florian Cacho, Vincent Huard, M. Saliva, Lorena Anghel, C. R. Parthasarathy, Abhishek Jain, Fabien Giner:
Timing in-situ monitors: Implementation strategy and applications results. 1-4 - Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. 1-4 - Xiang Gao, Eric A. M. Klumperink, Bram Nauta:
Sub-sampling PLL techniques. 1-8 - Tso-Wei Li, Jong Seok Park, Hua Wang:
A 2-24GHz 360° full-span differential vector modulator phase rotator with transformer-based poly-phase quadrature network. 1-4 - Alireza Imani, Hossein Hashemi:
A 3.9 mW, 35-44/41-59.5 GHz distributed injection locked frequency divider. 1-4 - Tso-Wei Li, Hua Wang:
A millimeter-wave fully differential transformer-based passive reflective-type phase shifter. 1-4 - Ramesh Harjani, Rakesh Kumar Palani:
Design of PVT tolerant inverter based circuits for low supply voltages. 1-8 - Bongjin Kim, Hoon Ki Kim, Chris H. Kim:
An 8bit, 2.6ps two-step TDC in 65nm CMOS employing a switched ring-oscillator based time amplifier. 1-4 - Jun Liu, Ahmed Fahmy, Taewook Kim, Nima Maghari:
A fully synthesized 0.4V 77dB SFDR reprogrammable SRMC filter using digital standard cells. 1-4 - Yu Jiang, Xu Liu, Xiwei Huang, Jing Guo, Mei Yan, Hao Yu, Jui-Cheng Huang, Kenny Cheng-Hsiang Hsieh, Tung-Tsun Chen:
A 201 mV/pH, 375 fps and 512×576 CMOS ISFET sensor in 65nm CMOS technology. 1-4 - Edward K. F. Lee:
A voltage doubling passive rectifier/regulator circuit for biomedical implants. 1-4 - Vahid Behravan, Shuo Li, Neil E. Glover, Chia-Hung Chen, Mohammed Shoaib, Gabor C. Temes, Patrick Yin Chiang:
A compressed-sensing sensor-on-chip incorporating statistics collection to improve reconstruction performance. 1-4 - Seyed Abdollah Mirbozorgi, Hadi Bahrami, Mohamad Sawan, Leslie A. Rusch, Benoit Gosselin:
A full-duplex wireless integrated transceiver for implant-to-air data communications. 1-4 - Tianshi Wang, Aadithya V. Karthik, Bichen Wu, Jian Yao, Jaijeet Roychowdhury:
MAPP: The Berkeley Model and Algorithm Prototyping Platform. 1-8 - Amr Lotfy, Syed Feruz Syed Farooq, Qi S. Wang, Soner Yaldiz, Praveen Mosalikanti, Nasser A. Kurd:
A system-verilog behavioral model for PLLs for pre-silicon validation and top-down design methodology. 1-4 - Zhimiao Chen, Zhixing Liu, Lei Liao, Ralf Wunderlich, Stefan Heinen:
A mixed-domain modeling method for RF systems. 1-4 - ChandraKanth R. Chappidi, Kaushik Sengupta:
Methods for finding globally maximum-efficiency impedance matching networks with lossy passives. 1-4 - Pavan Kumar Hanumolu:
Low dropout regulators. 1-37 - Jess Chen:
A few behavioral modeling options for balancing verification coverage and credibility. 1-115 - Bram Nauta:
Multiphase RF techniques in CMOS: Applied to beam-forming and full duplex receivers: CICC 2015 educational session. 1-147 - Woogeun Rhee:
Phase-locked frequency synthesis and modulation for modern wireless transceivers. 1-75 - Dan Oh, Yujeong Shim, Guang Chen:
Supply noise induced jitter modeling and optimization for high-speed interfaces. 1-42 - Ali Sadri:
MAA evolution: Common access/backhaul reference platform. 1-32 - Ron Kapusta:
SAR ADCs in parallel [time-interleaved] converter arrays. 1-86 - Francesco Carobolante:
Resonant wireless power transfer technology & integration roadmap. 1-96 - Derui Kong, Sang Min Lee, Shahin Mehdizad Taleie, Michael Joseph McGowan, Dongwon Seo:
A linear transconductance amplifier with differential-mode bandwidth extension and common-mode compensation. 1-4 - Jihoon Jeong, Francois Atallah, Hoan Nguyen, Josh Puckett, Keith A. Bowman, David Hansquine:
A 16nm configurable pass-gate bit-cell register file for quantifying the VMIN advantage of PFET versus NFET pass-gate bit cells. 1-4 - Henry Hsieh, Sang H. Dhong, Cheng-Chung Lin, Ming-Zhang Kuo, Kuo-Feng Tseng, Ping-Lin Yang, Kevin Huang, Min-Jer Wang, Wei Hwang:
Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology. 1-3 - Raveesh Magod, Naveen Suda, Vadim Ivanov, Ravi Balasingam, Bertan Bakkaloglu:
A 14.8μVRMS integrated noise output capacitor-less low dropout regulator with a switched-RC bandgap reference. 1-4 - Jie Lin, Shikai Zhu, Zhiyi Yu, Dongjun Xu, Sai Manoj P. D., Hao Yu:
A scalable and reconfigurable 2.5D integrated multicore processor on silicon interposer. 1-4 - Burak Erbagci, Nail Etkin Can Akkaya, Craig Teegarden, Ken Mai:
A 275 Gbps AES encryption accelerator using ROM-based S-boxes in 65nm. 1-4 - Aritra Banerjee, Rahmi Hezar, Lei Ding:
Efficiency improvement techniques for RF power amplifiers in deep submicron CMOS. 1-4 - Charles Chen, Aydin Babakhani:
Wireless synchronization of mm-wave arrays in 65nm CMOS. 1-4 - Xu Meng, Lianhong Zhou, Fujiang Lin, Chun-Huat Heng:
390-640MHz tunable oscillator based on phase interpolation with -120dBc/Hz in-band noise. 1-4 - Yun Yin, Yanqiang Gao, Zhihua Wang, Baoyong Chi:
A 0.1-5.0GHz self-calibrated SDR transmitter with -62.6dBc CIM3 in 65nm CMOS. 1-4 - Jianxun Zhu, Peter R. Kinget:
A field-programmable noise-canceling wideband receiver with high-linearity hybrid class-AB-C LNTAs. 1-4 - Praveen Mosalikanti, Nasser A. Kurd, Christopher Mozak, Takao Oshita:
Low power analog circuit techniques in the 5th generation intel coreTM microprocessor (broadwell). 1-4 - Deeksha Lal, Morteza Abbasi, David S. Ricketts:
A compact, high linearity 40GS/s track-and-hold amplifier in 90nm SiGe technology. 1-4 - Jintao Zhang, Liechao Huang, Zhuo Wang, Naveen Verma:
A seizure-detection IC employing machine learning to overcome data-conversion and analog-processing non-idealities. 1-4 - Golam R. Chowdhury, Arjang Hassibi:
A 550μm2 CMOS temperature sensor using self-discharging P-N diode with ±0.1°C (3σ) calibrated and ±0.5°C (3σ) uncalibrated inaccuracies. 1-4 - Chen Zhang, Muhammad Awais Bin Altaf, Jerald Yoo:
A 16-channel, 1-second latency patient-specific seizure onset and termination detection processor with dual detector architecture and digital hysteresis. 1-4 - Hundo Shin, Rakesh Kumar Palani, Anindya Saha, Fang-Li Yuan, Dejan Markovic, Ramesh Harjani:
An eight channel analog-FFT based 450MS/s hybrid filter bank ADC with improved SNDR for multi-band signals in 40nm CMOS. 1-4 - Anh Tuan Nguyen, Jian Xu, Zhi Yang:
A 14-bit 0.17mm2 SAR ADC in 0.13μm CMOS for high precision nerve recording. 1-4 - Yeonam Yoon, Kyoungtae Lee, Sungjin Hong, Xiyuan Tang, Long Chen, Nan Sun:
A 0.04-mm2 0.9-mW 71-dB SNDR distributed modular AS ADC with VCO-based integrator and digital DAC calibration. 1-4 - Shahrzad Naraghi, Alessandro Piovaccari:
Session 2 - Low power analog. 1 - Tetsuya Iizuka, Takahiro J. Yamaguchi:
Session 3 - Optical interconnect and reliability enhancement techniques. 1 - Fa Foster Dai, Swaminathan Sankaran:
Session 4 - Frequency and phase generation techniques. 1 - Jing Yang, Arijit Raychowdhury:
Session 6 - Analog circuits using digital cells. 1 - Christophe Antoine, Rikky Muller:
Session 7 - Advances in biomedial sensor systems. 1 - Colin C. McAndrew, Larry Nagel:
Session 9 - Advanced simulation techniques. 1 - Yanjie Wang, Hua Wang:
Session 11 - Advanced techniques for power amplifier transceiver front-ends. 1 - Robert C. Aitken, Tetsuya Iizuka:
Session 12 - Tutorial - beyond CMOS: Large area electronics-concepts and prospects. 1 - Arif Rahman, Aurangzeb Khan:
Session 14 - Emerging technology, power and cooling. 1-4 - John A. McNeill, Abhishek Bandyopadhyay:
Session 18 - Data converter techniques. 1 - Hoi Lee, Jeff Morroni:
Session 19 - Power management. 1-2 - Philippe Jansen, Ramnath Venkatraman:
Session 20 - Manufacturing beyond moore's law. 1 - Timothy M. Hancock, Jorge Grilo:
Session 22 - High frequency analog techniques. 1 - Chenjie Gu, Hidetoshi Onodera:
Session 23 - Modeling emerging devices. 1 - Jun Cao, Shahriar Mirabbasi:
Session 25 - 20 Gb/s transmitters and receivers. 1 - Mezyad Amourah, Morgan Whately:
A novel switched-capacitor-filter based low-area and fast-locking PLL. 1-6 - Adam Neale, Manoj Sachdev:
A low energy SRAM-based physically unclonable function primitive in 28 nm CMOS. 1-4 - Pavan Kumar, Vaibhav A. Vaidya, Harish Krishnamurthy, Stephen T. Kim, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De:
A 0.4V∼1V 0.2A/mm2 70% efficient 500MHz fully integrated digitally controlled 3-level buck voltage regulator with on-die high density MIM capacitor in 22nm tri-gate CMOS. 1-4 - Loai G. Salem, Patrick P. Mercier:
A single-inductor 7+7 ratio reconfigurable resonant switched-capacitor DC-DC converter with 0.1-to-1.5V output voltage range. 1-4 - Shouyi Yin, Peng Ouyang, Leibo Liu, Shaojun Wei:
A 83fps 1080P resolution 354 mW silicon implementation for computing the improved robust feature in affine space. 1-4 - Ahmed I. Hussein, Shadi Saberi, Jeyanandh Paramesh:
A 10 mW 60GHz 65nm CMOS DCO with 24% tuning range and 40 kHz frequency granularity. 1-4 - Sungmin Ock, Hyejeong Song, Ranjit Gharpurey:
A Cartesian feedback-feedforward transmitter IC in 130nm CMOS. 1-4 - Dongseok Shin, Sanjay Raman, Kwang-Jin Koh:
A 0.6-V, 30-GHz six-phase VCO with superharmonic coupling in 32-nm SOI CMOS technology. 1-4 - Amir Nikpaik, Abdolreza Nabavi, Amir Hossein Masnadi Shirazi, Sudip Shekhar, Shahriar Mirabbasi:
A dual-tank LC VCO topology approaching towards the maximum thermodynamically-achievable oscillator FoM. 1-4 - Jong-Hyeok Yoon, Soon-Won Kwon, Hyeon-Min Bae:
A DC-to-12.5Gb/s 4.88mW/Gb/s all-rate CDR with a single LC VCO in 90nm CMOS. 1-4 - Ahmad Sharkia, Sankaran Aniruddhan, Sudip Shekhar, Shahriar Mirabbasi:
A high-performance, yet simple to design, digital-friendly type-I PLL. 1-4 - Chundong Wu, Wang Ling Goh, Chiang Liang Kok, Wanlan Yang, Liter Siek:
A low TC, supply independent and process compensated current reference. 1-4 - Joo-Myoung Kim, Jae-Seung Lee, Sun-a Kim, Taeik Kim, Hojin Park, Sang-Gug Lee:
A 72μW, 2.4GHz, 11.7% tuning range, 212dBc/Hz FoM LC-VCO in 65nm CMOS. 1-4 - Mehdi Saligane, Mahmood Khayatzadeh, Yiqun Zhang, Seokhyeon Jeong, David T. Blaauw, Dennis Sylvester:
All-digital SoC thermal sensor using on-chip high order temperature curvature correction. 1-4 - Tan Yang, Junjie Lu, M. Shahriar Jahan, Kelly Griffin, Jeremy Langford, Jeremy Holleman:
A configurable 5.9 μW analog front-end for biosignal acquisition. 1-4 - Wenjuan Guo, Youngchun Kim, Ahmed H. Tewfik, Nan Sun:
Ultra-low power multi-channel data conversion with a single SAR ADC for mobile sensing applications. 1-4 - Long Chen, Xiyuan Tang, Arindam Sanyal, Yeonam Yoon, Jie Cong, Nan Sun:
A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction. 1-4 - Kareem Ragab, Nan Sun:
A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0-1 MASH ADC with direct digital background nonlinearity calibration. 1-4 - Arijit Banerjee, Jacob Breiholz, Benton H. Calhoun:
A 130nm canary SRAM for SRAM dynamic write VMIN tracking across voltage, frequency, and temperature variations. 1-4
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