default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID22nd COOL CHIPS 2019: Yokohama, Japan
- IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2019, Yokohama, Japan, April 17-19, 2019. IEEE 2019, ISBN 978-1-7281-1749-2
- Robert Wittig, Mattis Hasler, Emil Matús, Gerhard P. Fettweis:
Statistical Access Interval Prediction for Tightly Coupled Memory Systems. 1-3 - Masayuki Sato
, Yongcheng Chen, Haruya Kikuchi, Kazuhiko Komatsu, Hiroaki Kobayashi:
Perceptron-based Cache Bypassing for Way-Adaptable Caches. 1-3 - Yugo Yamauchi, Kazusa Musha, Hideharu Amano:
Implementing a large application(LSTM) on the multi-FPGA system: Flow-in-Cloud. 1-3 - Ken Nakamura, Yuya Omori, Daisuke Kobayashi, Tatsuya Osawa, Takayuki Onishi, Koyo Nitta, Hiroe Iwasaki, Atsushi Shimizu:
Low Delay 4K 120fps HEVC Decoder with Parallel Processing Architecture. 1-3 - Kyosuke Tanaka, Hayato Yamaki, Shinobu Miwa, Hiroki Honda:
Multi-Level Packet Processing Caches. 1-3 - Tomoya Itsubo, Mineto Tsukada, Hiroki Matsutani:
Performance and Cost Evaluations of Online Sequential Learning and Unsupervised Anomaly Detection Core. 1-3 - Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto:
Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR. 1-3 - Yusuke Shirota, Satoshi Shirai, Tatsunori Kanai:
Hybrid Access in Storage-class Memory-aware Low Power Virtual Memory System. 1-3 - Mulya Agung, Muhammad Alfian Amrizal, Ryusuke Egawa, Hiroyuki Takizawa:
The Impacts of Locality and Memory Congestion-aware Thread Mapping on Energy Consumption of Modern NUMA Systems. 1-3 - Yuta Tokusashi, Hiroki Matsutani, Hideharu Amano:
Key-value Store Chip Design for Low Power Consumption. 1-3 - Alberto Gianelli, Nick Iliev, Shamma Nasrin, Mariagrazia Graziano, Amit Ranjan Trivedi:
Low Power Speaker Identification using Look Up-free Gaussian Mixture Model in CMOS. 1-3 - Ravi Theja Gollapudi, Gokturk Yuksek, Kanad Ghose:
Cache-Aware Dynamic Classification and Scheduling for Linux. 1-3 - Shinichi Sasaki, Asuka Maki, Daisuke Miyashita, Jun Deguchi:
Post Training Weight Compression with Distribution-based Filter-wise Quantization Step. 1-3 - Eri Ogawa, Kazuaki Ishizaki, Hiroshi Inoue, Swagath Venkataramani, Jungwook Choi, Wei Wang, Vijayalakshmi Srinivasan, Moriyoshi Ohara, Kailash Gopalakrishnan:
A Compiler for Deep Neural Network Accelerators to Generate Optimized Code for a Wide Range of Data Parameters from a Hand-crafted Computation Kernel. 1-3
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-09-28 01:16 CEST by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
