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ORCID54th DAC 2017: Austin, TX, USA
- Proceedings of the 54th Annual Design Automation Conference, DAC 2017, Austin, TX, USA, June 18-22, 2017. ACM 2017, ISBN 978-1-4503-4927-7
- An Zou, Jingwen Leng, Yazhou Zu, Tao Tong, Vijay Janapa Reddi, David M. Brooks, Gu-Yeon Wei, Xuan Zhang
:
Ivory: Early-Stage Design Space Exploration Tool for Integrated Voltage Regulators. 1:1-1:6 - Yuan Xue, Chengmo Yang, Jingtong Hu:
Age-aware Logic and Memory Co-Placement for RRAM-FPGAs. 1:1-1:6 - Pietro Mercati, Raid Ayoub, Michael Kishinevsky, Eric Samson, Marc Beuchat, Francesco Paterna, Tajana Simunic Rosing:
Multi-variable Dynamic Power Management for the GPU Subsystem. 2:1-2:6 - Jing Li, Mengying Zhao, Lei Ju, Chun Jason Xue, Zhiping Jia:
Maximizing Forward Progress with Cache-aware Backup for Self-powered Non-volatile Processors. 2:1-2:6 - Dawei Li, Kaicheng Zhang, Akhil Guliani, Seda Ogrenci Memik:
Adaptive Thermal Management for 3D ICs with Stacked DRAM Caches. 3:1-3:6 - Xian Zhang, Guangyu Sun:
Toss-up Wear Leveling: Protecting Phase-Change Memories from Inconsistent Write Patterns. 3:1-3:6 - Seongwoo Hong, Suk-Won Kim, Young-Jin Kim:
3 Channel Dependency-Based Power Model for Mobile AMOLED Displays. 4:1-4:6 - Yi Wang, Mingxu Zhang, Jing Yang:
Exploiting Parallelism for Convolutional Connections in Processing-In-Memory Architecture. 4:1-4:6 - Chun-Hao Lai, Jishen Zhao, Chia-Lin Yang:
Leave the Cache Hierarchy Operation as It Is: A New Persistent Memory Accelerating Approach. 5:1-5:6 - Andrew Becker, Wei Hu, Yu Tai, Philip Brisk, Ryan Kastner, Paolo Ienne:
Arbitrary Precision and Complexity Tradeoffs for Gate-Level Information Flow Tracking. 5:1-5:6 - Andrew Ferraiuolo, Weizhe Hua, Andrew C. Myers, G. Edward Suh:
Secure Information Flow Verification with Mutable Dependent Types. 6:1-6:6 - Mohsen Imani, Saransh Gupta, Tajana Rosing:
Ultra-Efficient Processing In-Memory for Data Intensive Applications. 6:1-6:6 - Mehmet Kayaalp, Khaled N. Khasawneh, Hodjat Asghari Esfeden, Jesse Elwell, Nael B. Abu-Ghazaleh, Dmitry V. Ponomarev, Aamer Jaleel:
RIC: Relaxed Inclusion Caches for Mitigating LLC Side-Channel Attacks. 7:1-7:6 - Christian Krieg, Clifford Wolf, Axel Jantsch, Tanja Zseby:
Toggle MUX: How X-Optimism Can Lead to Malicious Hardware. 7:1-7:6 - Punit Khanna, Chester Rebeiro, Aritra Hazra:
XFC: A Framework for eXploitable Fault Characterization in Block Ciphers. 8:1-8:6 - Zimu Guo, Xiaolin Xu, Mark M. Tehranipoor, Domenic Forte:
FFD: A Framework for Fake Flash Detection. 8:1-8:6 - Yang Xie, Ankur Srivastava:
Delay Locking: Security Enhancement of Logic Locking against IC Counterfeiting and Overproduction. 9:1-9:6 - Mohamad Baker Alawieh, Fa Wang, Xin Li:
Efficient Hierarchical Performance Modeling for Integrated Circuits via Bayesian Co-Learning. 9:1-9:6 - Kai Bittner, Hans Georg Brachtendorf, Wim Schoenmaker, Pascal Reynier:
Coupled circuit/EM simulation for radio frequency circuits. 10:1-10:6 - Chen Zhou, Keshab K. Parhi, Chris H. Kim:
Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements. 10:1-10:6 - Mengshuo Wang, Fan Yang, Changhao Yan, Xuan Zeng, Xiangdong Hu:
Efficient Bayesian Yield Optimization Approach for Analog and SRAM Circuits. 11:1-11:6 - Joydeep Rakshit, Kartik Mohanram:
ASSURE: Authentication Scheme for SecURE Energy Efficient Non-Volatile Memories. 11:1-11:6 - Johann Knechtel, Ozgur Sinanoglu:
On Mitigation of Side-Channel Attacks in 3D ICs: Decorrelating Thermal Patterns from Power and Activity. 12:1-12:6 - Biying Xu, Shaolan Li, Nan Sun, David Z. Pan:
A Scaling Compatible, Synthesis Friendly VCO-based Delta-sigma ADC Design and Synthesis Methodology. 12:1-12:6 - Fabio Sebastiano, Harald Homulle, Bishnu Patra, Rosario M. Incandela, Jeroen P. G. van Dijk, Lin Song, Masoud Babaie, Andrei Vladimirescu, Edoardo Charbon:
Cryo-CMOS Electronic Control for Scalable Quantum Computing: Invited. 13:1-13:6 - Qi Zhu, Hengyi Liang, Licong Zhang, Debayan Roy, Wenchao Li, Samarjit Chakraborty:
Extensibility-Driven Automotive In-Vehicle Architecture Design: Invited. 13:1-13:6 - M. Sadegh Riazi, Ebrahim M. Songhori, Farinaz Koushanfar:
PriSearch: Efficient Search on Private Data. 14:1-14:6 - Sandip Ray, Wen Chen, Jayanta Bhadra, Mohammad Abdullah Al Faruque:
Extensibility in Automotive Security: Current Practice and Challenges: Invited. 14:1-14:6 - Alric Althoff, Ryan Kastner:
An Architecture for Learning Stream Distributions with Application to RNG Testing. 15:1-15:6 - Philipp Mundhenk, Ghizlane Tibba, Licong Zhang, Felix Reimann, Debayan Roy, Samarjit Chakraborty:
Dynamic Platforms for Uncertainty Management in Future Automotive E/E Architectures: Invited. 15:1-15:6 - Pascal Sasdrich, Tim Güneysu:
Cryptography for Next Generation TLS: Implementing the RFC 7748 Elliptic Curve448 Cryptosystem in Hardware. 16:1-16:6 - Jianping Wang, Sachin S. Sapatnekar, Chris H. Kim, Paul A. Crowell, Steven J. Koester, Supriyo Datta, Kaushik Roy, Anand Raghunathan, Xiaobo Sharon Hu, Michael T. Niemier, Azad Naeemi, Chia-Ling Chien, Caroline A. Ross, Roland Kawakami:
A Pathway to Enable Exponential Scaling for the Beyond-CMOS Era: Invited. 16:1-16:6 - Meng Li, Liangzhen Lai, Vikas Chandra, David Z. Pan:
Cross-level Monte Carlo Framework for System Vulnerability Evaluation against Fault Attack. 17:1-17:6 - Suman Datta, Alan C. Seabaugh, Michael T. Niemier, Arijit Raychowdhury, Darrell Schlom, Debdeep Jena, Huili Grace Xing, H.-S. Philip Wong, Eric Pop, Sayeef S. Salahuddin, Sumeet Kumar Gupta, Supratik Guha:
In Quest of the Next Information Processing Substrate: Extended Abstract: Invited. 17:1-17:6 - Ameya Patil, Naresh R. Shanbhag, Lav R. Varshney, Eric Pop, H.-S. Philip Wong, Subhasish Mitra, Jan M. Rabaey, Jeffrey A. Weldon, Larry T. Pileggi, Sasikanth Manipatruni, Dmitri E. Nikonov, Ian A. Young:
A Systems Approach to Computing in Beyond CMOS Fabrics: Invited. 18:1-18:2 - Derong Liu, Vinicius S. Livramento, Salim Chowdhury, Duo Ding, Huy Vo, Akshay Sharma, David Z. Pan:
Streak: Synergistic Topology Generation and Route Synthesis for On-Chip Performance-Critical Signal Groups. 18:1-18:6 - Daohang Shi, Azadeh Davoodi:
TraPL: Track Planning of Local Congestion for Global Routing. 19:1-19:6 - Amin Malekpour, Roshan G. Ragel, Aleksandar Ignjatovic, Sri Parameswaran:
TrojanGuard: Simple and Effective Hardware Trojan Mitigation Techniques for Pipelined MPSoCs. 19:1-19:6 - Fateme S. Hosseini, Pouya Fotouhi, Chengmo Yang, Guang R. Gao:
Leveraging Compiler Optimizations to Reduce Runtime Fault Recovery Overhead. 20:1-20:6 - Xiaoqing Xu, Yibo Lin, Vinicius S. Livramento, David Z. Pan:
Concurrent Pin Access Optimization for Unidirectional Routing. 20:1-20:6 - Abhishek Roy, Hakan Aydin, Dakai Zhu:
Energy-Aware Standby-Sparing on Heterogeneous Multicore Systems. 21:1-21:6 - Vivek Mishra, Palkesh Jain, Sravan K. Marella, Sachin S. Sapatnekar:
Incorporating the Role of Stress on Electromigration in Power Grids with Via Arrays. 21:1-21:6 - Tianshu Wei, Yanzhi Wang, Qi Zhu:
Deep Reinforcement Learning for Building HVAC Control. 22:1-22:6 - Xiao Zhu, Duo Liu, Kan Zhong, Jinting Ren, Tao Li:
SmartSwap: High-Performance and User Experience Friendly Swapping in Mobile Systems. 22:1-22:6 - Wenjian He, Sanjeev Das, Wei Zhang, Yang Liu:
No-Jump-into-Basic-Block: Enforce Basic Block CFI on the Fly for Real-world Binaries. 23:1-23:6 - Yajuan Du, Qiao Li, Liang Shi, Deqing Zou, Hai Jin, Chun Jason Xue:
Reducing LDPC Soft Sensing Latency by Lightweight Data Refresh for Flash Read Performance Improvement. 23:1-23:6 - Myungsuk Kim, Jaehoon Lee, Sungjin Lee, Jisung Park, Jihong Kim:
Improving Performance and Lifetime of Large-Page NAND Storages Using Erase-Free Subpage Programming. 24:1-24:6 - Ghada Dessouky, Shaza Zeitouni, Thomas Nyman, Andrew Paverd, Lucas Davi, Patrick Koeberl, N. Asokan, Ahmad-Reza Sadeghi:
LO-FAT: Low-Overhead Control Flow ATtestation in Hardware. 24:1-24:6 - Tseng-Yi Chen, Yuan-Hao Chang, Yuan-Hung Kuan, Yu-Ming Chang:
VirtualGC: Enabling Erase-free Garbage Collection to Upgrade the Performance of Rewritable SLC NAND Flash Memory. 25:1-25:6 - Nisarg Patel, Avesta Sasan, Houman Homayoun:
Analyzing Hardware Based Malware Detectors. 25:1-25:6 - Ming Cheng, Lixue Xia, Zhenhua Zhu, Yi Cai, Yuan Xie, Yu Wang, Huazhong Yang:
TIME: A Training-in-memory Architecture for Memristor-based Deep Neural Networks. 26:1-26:6 - Yeongpil Cho, Donghyun Kwon, Yunheung Paek:
Instruction-Level Data Isolation for the Kernel on ARM. 26:1-26:6 - Shuo Wang, Yun Liang, Wei Zhang:
FlexCL: An Analytical Performance Model for OpenCL Workloads on Flexible FPGAs. 27:1-27:6 - Aayush Ankit, Abhronil Sengupta, Priyadarshini Panda, Kaushik Roy:
RESPARC: A Reconfigurable and Energy-Efficient Architecture with Memristive Crossbars for Deep Spiking Neural Networks. 27:1-27:6 - Hokchhay Tann, Soheil Hashemi, R. Iris Bahar, Sherief Reda:
Hardware-Software Codesign of Accurate, Multiplier-free Deep Neural Networks. 28:1-28:6 - Shuo Wang, Yun Liang:
A Comprehensive Framework for Synthesizing Stencil Algorithms on FPGAs using OpenCL Model. 28:1-28:6 - Hyeon Uk Sim, Jongeun Lee:
A New Stochastic Computing Multiplier with Application to Deep Convolutional Neural Networks. 29:1-29:6 - Xuechao Wei, Cody Hao Yu, Peng Zhang, Youxiang Chen, Yuxin Wang, Han Hu, Yun Liang, Jason Cong:
Automated Systolic Array Architecture Synthesis for High Throughput CNN Inference on FPGAs. 29:1-29:6 - Love Singhal, Mahesh A. Iyer, Saurabh N. Adya:
LSC: A Large-Scale Consensus-Based Clustering Algorithm for High-Performance FPGAs. 30:1-30:6 - Ali Moin, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli, Jan M. Rabaey:
Optimized Design of a Human Intranet Network. 30:1-30:6 - Negar Reiskarimian, Linxiao Zhang, Harish Krishnaswamy:
Linear Periodically Time-Varying (LPTV) Circuits Enable New Radio Architectures for Emerging Wireless Communication Paradigms: Extended Abstract: Invited. 31:1-31:4 - Dmitrii Kirov, Pierluigi Nuzzo, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli:
ArchEx: An Extensible Framework for the Exploration of Cyber-Physical System Architectures. 31:1-31:6 - Boudewijn Braams, Sebastian Altmeyer, Andy D. Pimentel:
EDiFy: An Execution time Distribution Finder. 32:1-32:6 - Louis Lintereur:
INVITED Challenges and Potential for Incorporating Model-Based Design in Medical Device Development: Extended Abstract. 32:1 - Lixue Xia, Mengyun Liu, Xuefei Ning, Krishnendu Chakrabarty, Yu Wang:
Fault-Tolerant Training with On-Line Fault Detection for RRAM-Based Neural Computing Systems. 33:1-33:6 - Ying Wang, Huawei Li, Xiaowei Li:
Real-Time Meets Approximate Computing: An Elastic CNN Inference Accelerator with Adaptive Trade-off between QoS and QoR. 33:1-33:6 - Kuo-Kai Hsieh, Li-C. Wang, Wen Chen, Jayanta Bhadra:
Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery. 34:1-34:6 - Martin Barnasconi, Sumit Adhikari:
ESL Design in SystemC AMS: Introducing a top-down design methodology for mixed-signal systems: Invited. 34:1-34:5 - Rajdeep Mukherjee, Mitra Purandare, Raphael Polig, Daniel Kroening:
Formal Techniques for Effective Co-verification of Hardware/Software Co-designs. 35:1-35:6 - Christoph Grimm, Michael Rathmair:
Dealing with Uncertainties in Analog/Mixed-Signal Systems: Invited. 35:1-35:6 - Raviv Gal, Einat Kermany, Bilal Saleh, Avi Ziv, Michael L. Behm, Bryan G. Hickerson:
Template Aware Coverage: Taking Coverage Analysis to the Next Level. 36:1-36:6 - Vladimir Dubikhin, Chris J. Myers, Danil Sokolov, Ioannis Syranidis, Alexandre Yakovlev:
Advances in Formal Methods for the Design of Analog/Mixed-Signal Systems: Invited. 36:1-36:6 - Kuan-Yen Huang, Ting-Yu Shen, Chien-Mo James Li:
Test Methodology for Dual-rail Asynchronous Circuits. 37:1-37:6 - Alessandro Danese, Nicolò Dalla Riva, Graziano Pravadelli:
A-TEAM: Automatic template-based assertion miner. 37:1-37:6 - Chun-Ning Lai, Jie-Hong R. Jiang:
Path-Specific Functional Timing Verification under Floating and Transition Modes of Operation. 38:1-38:6 - Tianjian Li, Xiangyu Bi, Naifeng Jing, Xiaoyao Liang, Li Jiang:
Sneak-Path Based Test and Diagnosis for 1R RRAM Crossbar Using Voltage Bias Technique. 38:1-38:6 - Hyesun Hong, Hyunok Oh, Soonhoi Ha:
Hierarchical Dataflow Modeling of Iterative Applications. 39:1-39:6 - Emil Gizdarski, Peter Wohl, John A. Waicukauski:
A New Paradigm for Synthesis of Linear Decompressors. 39:1-39:6 - Moslem Didehban, Sai Ram Dheeraj Lokam, Aviral Shrivastava:
InCheck: An In-application Recovery Scheme for Soft Errors. 40:1-40:6 - Jiangyuan Gu, Shouyi Yin, Shaojun Wei:
Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging Effect. 40:1-40:6 - Hussam Amrouch, Behnam Khaleghi, Andreas Gerstlauer, Jörg Henkel:
Towards Aging-Induced Approximations. 41:1-41:6 - Arian Maghazeh, Unmesh D. Bordoloi, Usman Dastgeer, Alexandru Andrei, Petru Eles, Zebo Peng:
Latency-Aware Packet Processing on CPU-GPU Heterogeneous Systems. 41:1-41:6 - Muhammad Abdullah Hanif, Rehan Hafiz, Osman Hasan, Muhammad Shafique:
QuAd: Design and Analysis of Quality-Area Optimal Low-Latency Approximate Adders. 42:1-42:6 - Fan Gong, Lei Ju, Deshan Zhang, Mengying Zhao, Zhiping Jia:
Cooperative DVFS for energy-efficient HEVC decoding on embedded CPU-GPU architecture. 42:1-42:6 - Jason Cong, Peng Wei, Cody Hao Yu, Peipei Zhou:
Bandwidth Optimization Through On-Chip Memory Restructuring for HLS. 43:1-43:6 - Carlos Moreno, Sebastian Fischmeister:
Fast and Energy-Efficient Digital Filters for Signal Conditioning in Low-Power Microcontrollers. 43:1-43:6 - Tseng-Yi Chen, Yuan-Hao Chang, Shuo-Han Chen, Chih-Ching Kuo, Ming-Chang Yang, Hsin-Wen Wei, Wei-Kuan Shih:
Enabling Write-Reduction Strategy for Journaling File Systems over Byte-addressable NVRAM. 44:1-44:6 - Xianfeng Li, Guikang Chen, Wen Wen:
Energy-Efficient Execution for Repetitive App Usages on big.LITTLE Architectures. 44:1-44:6 - Sergi Alcaide, Carles Hernández, Antoni Roca, Jaume Abella:
DIMP: A Low-Cost Diversity Metric Based on Circuit Path Analysis. 45:1-45:6 - Manupa Karunaratne, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh:
HyCUBE: A CGRA with Reconfigurable Single-cycle Multi-hop Interconnect. 45:1-45:6 - Zhiyuan Yang, Caleb Serafy, Tiantao Lu, Ankur Srivastava:
Phase-driven Learning-based Dynamic Reliability Management For Multi-core Processors. 46:1-46:6 - Raj Gautam Dutta, Xiaolong Guo, Teng Zhang, Kevin A. Kwiat, Charles A. Kamhoua, Laurent Njilla, Yier Jin:
Estimation of Safe Sensor Measurements of Autonomous System Under Attack. 46:1-46:6 - Manish Chauhan, Rodolfo Pellizzoni, Krzysztof Czarnecki:
Modeling the Effects of AUTOSAR Overheads on Application Timing and Schedulability. 47:1-47:6 - Sebastian Haas, Tobias Seifert, Benedikt Nöthen, Stefan Scholze, Sebastian Höppner, Andreas Dixius, Esther Pérez Adeva, Thomas R. Augustin, Friedrich Pauls, Sadia Moriam, Mattis Hasler, Erik Fischer, Yong Chen, Emil Matús, Georg Ellguth, Stephan Hartmann, Stefan Schiefer, Love Cederström, Dennis Walter, Stephan Henker, Stefan Hänzsche, Johannes Uhlig, Holger Eisenreich, Stefan Weithoffer, Norbert Wehn, René Schüffny, Christian Mayr, Gerhard P. Fettweis:
A Heterogeneous SDR MPSoC in 28 nm CMOS for Low-Latency Wireless Applications. 47:1-47:6 - Fedor Smirnov, Michael Glaß, Felix Reimann, Jürgen Teich:
Optimizing Message Routing and Scheduling in Automotive Mixed-Criticality Time-Triggered Networks. 48:1-48:6 - Tianyu Jia, Russ Joseph, Jie Gu:
Greybox Design Methodology: A Program Driven Hardware Co-optimization with Ultra-Dynamic Clock Management. 48:1-48:6 - Maryam Hemmati, Morteza Biglari-Abhari, Smaïl Niar, Stevan Berber:
Real-Time Multi-Scale Pedestrian Detection for Driver Assistance Systems. 49:1-49:6 - Chunfeng Liu, Bing Li, Hailong Yao, Paul Pop, Tsung-Yi Ho, Ulf Schlichtmann:
Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. 49:1-49:6 - Edward Andert, Mohammad Khayatian, Aviral Shrivastava:
Crossroads: Time-Sensitive Autonomous Intersection Management Technique. 50:1-50:6 - Andreas Grimmer, Werner Haselmayr, Andreas Springer, Robert Wille:
A Discrete Model for Networked Labs-on-Chips: Linking the Physical World to Design Automation. 50:1-50:6 - Peter Debacker, Kwangsoo Han, Andrew B. Kahng, Hyein Lee, Praveen Raghavan, Lutong Wang:
Vertical M1 Routing-Aware Detailed Placement for Congestion and Wirelength Reduction in Sub-10nm Nodes. 51:1-51:6 - Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho, Ulf Schlichtmann:
Component-Oriented High-level Synthesis for Continuous-Flow Microfluidics Considering Hybrid-Scheduling. 51:1-51:6 - Jianli Chen, Ziran Zhu, Wenxing Zhu, Yao-Wen Chang:
Toward Optimal Legalization for Mixed-Cell-Height Circuit Designs. 52:1-52:6 - Chengwen Xu, Xiangyu Wu, Wenqi Yin, Qiang Xu, Naifeng Jing, Xiaoyao Liang, Li Jiang:
On Quality Trade-off Control for Approximate Computing Using Iterative Training. 52:1-52:6 - Shrikanth Ganapathy, John Kalamatianos, Keith Kasprak, Steven Raasch:
On Characterizing Near-Threshold SRAM Failures in FinFET Technology. 53:1-53:6 - Yu-Chen Huang, Yao-Wen Chang:
Fogging Effect Aware Placement in Electron Beam Lithography. 53:1-53:6 - Jun Tao, Handi Yu, Dian Zhou, Yangfeng Su, Xuan Zeng, Xin Li:
Correlated Rare Failure Analysis via Asymptotic Probability Evaluation. 54:1-54:6 - Jaewoo Seo, Jinwook Jung, Sangmin Kim, Youngsoo Shin:
Pin Accessibility-Driven Cell Layout Redesign and Placement Optimization. 54:1-54:6 - Seungwon Kim, SangGi Do, Seokhyeong Kang:
Fast Predictive Useful Skew Methodology for Timing-Driven Placement Optimization. 55:1-55:6 - Mungyu Son, Hyunsun Park, Junwhan Ahn, Sungjoo Yoo:
Making DRAM Stronger Against Row Hammering. 55:1-55:6 - Anshuman Verma, Huiyang Zhou, Skip Booth, Robbie King, James Coole, Andy Keep, John Marshall, Wu-chun Feng:
Developing Dynamic Profiling and Debugging Support in OpenCL for FPGAs. 56:1-56:6 - Ioannis Seitanidis, Giorgos Dimitrakopoulos, Pavlos M. Mattheakis, Laurent Masse-Navette, David G. Chinnery:
Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. 56:1-56:6 - Qiang Wang, Leibo Liu, Wenping Zhu, Huiyu Mo, Chenchen Deng, Shaojun Wei:
A 700fps Optimized Coarse-to-Fine Shape Searching Based Hardware Accelerator for Face Alignment. 57:1-57:6 - Ankur Agrawal, Chia-Yu Chen, Jungwook Choi, Kailash Gopalakrishnan, Jinwook Oh, Sunil Shukla, Viji Srinivasan, Swagath Venkataramani, Wei Zhang:
Accelerator Design for Deep Learning Training: Extended Abstract: Invited. 57:1-57:2 - Xiaowei Xu, Dewen Zeng, Wenyao Xu, Yiyu Shi, Yu Hu:
An Efficient Memristor-based Distance Accelerator for Time Series Data Mining on Data Centers. 58:1-58:6 - Wei-Yu Tsai, Jinhang Choi, Tulika Parija, Priyanka Gomatam, Chita R. Das, John Sampson, Vijaykrishnan Narayanan:
Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks. 58:1-58:6 - Shiqi Lian, Yinhe Han, Ying Wang, Yungang Bao, Hang Xiao, Xiaowei Li, Ninghui Sun:
Dadu: Accelerating Inverse Kinematics for High-DOF Robots. 59:1-59:6 - Jong Hwan Ko, Burhan Ahmad Mudassar, Taesik Na, Saibal Mukhopadhyay:
Design of an Energy-Efficient Accelerator for Training of Convolutional Neural Networks using Frequency-Domain Computation. 59:1-59:6 - Muhammad Adeel Pasha, Momin Uppal, Muhammad Hassan Ahmed, Muhammad Aimal Rehman, Muhammad Awais Bin Altaf:
Towards Design and Automation of Hardware-Friendly NOMA Receiver with Iterative Multi-User Detection. 60:1-60:6 - Hyeonuk Kim, Jaehyeong Sim, Yeongjae Choi, Lee-Sup Kim:
A Kernel Decomposition Architecture for Binary-weight Convolutional Neural Networks. 60:1-60:6 - Jian Kuang, Evangeline F. Y. Young:
Fixed-Parameter Tractable Algorithms for Optimal Layout Decomposition and Beyond. 61:1-61:6 - Bita Darvish Rouhani, Azalia Mirhoseini, Farinaz Koushanfar:
Deep3: Leveraging Three Levels of Parallelism for Efficient Deep Learning. 61:1-61:6 - Qingcheng Xiao, Yun Liang, Liqiang Lu, Shengen Yan, Yu-Wing Tai:
Exploring Heterogeneous Algorithms for Accelerating Deep Convolutional Neural Networks on FPGAs. 62:1-62:6 - Haoyu Yang, Jing Su, Yi Zou, Bei Yu, Evangeline F. Y. Young:
Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning. 62:1-62:6 - Peng Ouyang, Shouyi Yin, Shaojun Wei:
A Fast and Power Efficient Architecture to Parallelize LSTM based RNN for Cognitive Intelligence Applications. 63:1-63:6 - Kuan-Jung Chen, Yu-Kai Chuang, Bo-Yi Yu, Shao-Yun Fang:
Minimizing Cluster Number with Clip Shifting in Hotspot Pattern Classification. 63:1-63:6 - Wei-Lun Chiu, Iris Hui-Ru Jiang, Chien-Pang Lu, Yu-Tung Chang:
Power and Area Efficient Hold Time Fixing by Free Metal Segment Allocation. 64:1-64:6 - Wei-Chun Chang, Iris Hui-Ru Jiang, Yen-Ting Yu, Wei-Fang Liu:
iClaire: A Fast and General Layout Pattern Classification Algorithm. 64:1-64:6 - Manish Gupta, Daniel Lowell, John Kalamatianos, Steven Raasch, Vilas Sridharan, Dean M. Tullsen, Rajesh K. Gupta:
Compiler Techniques to Reduce the Synchronization Overhead of GPU Redundant Multithreading. 65:1-65:6 - Tin-Yin Lai, Tsung-Wei Huang, Martin D. F. Wong:
LibAbs: An Efficient and Accurate Timing Macro-Modeling Algorithm for Large Hierarchical Designs. 65:1-65:6 - Nicola Bombieri, Federico Busato, Franco Fummi:
Power-aware Performance Tuning of GPU Applications Through Microbenchmarking. 66:1-66:6 - Song Bian, Michihiro Shintani, Masayuki Hiromoto, Takashi Sato:
LSTA: Learning-Based Static Timing Analysis for High-Dimensional Correlated On-Chip Variations. 66:1-66:6 - Niranjan Kulkarni, Aykut Dengi, Sarma B. K. Vrudhula:
A Clock Skewing Strategy to Reduce Power and Area of ASIC Circuits. 67:1-67:6 - Haeseung Lee, Muhammad Shafique, Mohammad Abdullah Al Faruque:
Low-overhead Aging-aware Resource Management on Embedded GPUs. 67:1-67:6 - Xiaoming Chen, Jianxu Chen, Danny Z. Chen, Xiaobo Sharon Hu:
Optimizing Memory Efficiency for Convolution Kernels on Kepler GPUs. 68:1-68:6 - Zhiqiang Zhao, Zhuo Feng:
A Spectral Graph Sparsification Approach to Scalable Vectorless Power Grid Integrity Verification. 68:1-68:6 - Ya Wang, Wenrui Zhang, Peng Li, Jian Gong:
Convergence-Boosted Graph Partitioning using Maximum Spanning Trees for Iterative Solution of Large Linear Circuits. 69:1-69:6 - Aviral Shrivastava, Mohammadreza Mehrabian, Mohammad Khayatian, Patricia Derler, Hugo A. Andrade, Kevin B. Stanton, Ya-Shian Li-Baboud, Edward R. Griffor, Marc Weiss, John C. Eidson:
A Testbed to Verify the Timing Behavior of Cyber-Physical Systems: Invited. 69:1-69:6 - Hsiao-Lun Wang, Minghe Zhang, Peter A. Beerel:
Retiming of Two-Phase Latch-Based Resilient Circuits. 70:1-70:6 - Gengjie Chen, Jian Kuang, Zhiliang Zeng, Hang Zhang, Evangeline F. Y. Young, Bei Yu:
Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design. 70:1-70:6 - Yanan Lu, Leibo Liu, Yangdong Deng, Jian Weng, Zhaoshi Li, Chenchen Deng, Shaojun Wei:
Minimizing Pipeline Stalls in Distributed-Controlled Coarse-Grained Reconfigurable Arrays with Triggered Instruction Issue and Execution. 71:1-71:6 - Chau-Chin Huang, Bo-Qiao Lin, Hsin-Ying Lee, Yao-Wen Chang, Kuo-Sheng Wu, Jun-Zhi Yang:
Graph-Based Logic Bit Slicing for Datapath-Aware Placement. 71:1-71:6 - Rickard Ewetz:
A Clock Tree Optimization Framework with Predictable Timing Quality. 72:1-72:6 - Deepashree Sengupta, Farhana Sharmin Snigdha, Jiang Hu, Sachin S. Sapatnekar:
SABER: Selection of Approximate Bits for the Design of Error Tolerant Circuits. 72:1-72:6 - Cheng-Yu Shih, Chun-Hong Shih, Jie-Hong R. Jiang:
Closing the Accuracy Gap of Static Performance Analysis of Asynchronous Circuits. 73:1-73:6 - Ren Chen, Viktor K. Prasanna:
Optimal Circuits for Parallel Bit Reversal. 73:1-73:6 - Rafael Trapani Possignolo, Jose Renau:
LiveSynth: Towards an Interactive Synthesis Flow. 74:1-74:6 - Arnab Raha, Vijay Raghunathan:
Towards Full-System Energy-Accuracy Tradeoffs: A Case Study of An Approximate Smart Camera System. 74:1-74:6 - Muhammad Kamran Ayub, Osman Hasan, Muhammad Shafique:
Statistical Error Analysis for Low Power Approximate Adders. 75:1-75:6 - Alfio Di Mauro, Francesco Conti, Luca Benini:
An Ultra-Low Power Address-Event Sensor Interface for Energy-Proportional Time-to-Information Extraction. 75:1-75:6 - Mohsen Imani, Daniel Peroni, Tajana Rosing:
CFPU: Configurable Floating Point Multiplier for Energy-Efficient Computing. 76:1-76:6 - Leon Riesebos, Xiang Fu, Savvas Varsamopoulos, Carmen G. Almudéver, Koen Bertels:
Pauli Frames for Quantum Computer Architectures. 76:1-76:6 - Anteneh Gebregiorgis, Saman Kiamehr, Mehdi Baradaran Tahoori:
Error Propagation Aware Timing Relaxation For Approximate Near Threshold Computing. 77:1-77:6 - Juexiao Su, Lei He:
Fast Embedding of Constrained Satisfaction Problem to Quantum Annealer with Minimizing Chain Length. 77:1-77:6 - Mathias Soeken, Martin Roetteler, Nathan Wiebe, Giovanni De Micheli:
Hierarchical Reversible Logic Synthesis Using LUTs. 78:1-78:6 - Wei Zuo, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Chung-Wei Lin, Shinichi Shiraishi, Deming Chen:
Accurate High-level Modeling and Automated Hardware/Software Co-design for Effective SoC Design Space Exploration. 78:1-78:6 - Zhi-Wen Lin, Yao-Wen Chang:
Detailed Placement for Two-Dimensional Directed Self-Assembly Technology. 79:1-79:6 - Tim Schmidt, Guantao Liu, Rainer Dömer:
Exploiting Thread and Data Level Parallelism for Ultimate Parallel SystemC Simulation. 79:1-79:6 - Qinghang Zhao, Yongpan Liu, Wenyu Sun, Jiaqing Zhao, Hailong Yao, Xiaojun Guo, Huazhong Yang:
Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. 80:1-80:6 - Kenneth O'Neal, Philip Brisk, Emily Shriver, Michael Kishinevsky:
HALWPE: Hardware-Assisted Light Weight Performance Estimation for GPUs. 80:1-80:6 - Reena Panda, Xinnian Zheng, Jiajun Wang, Andreas Gerstlauer, Lizy K. John:
Statistical Pattern Based Modeling of GPU Memory Access Streams. 81:1-81:6 - Siting Liu, Jie Han:
Hardware ODE Solvers using Stochastic Circuits. 81:1-81:6 - Yang Zhang, Dan Feng, Jingning Liu, Wei Tong, Bing Wu, Caihua Fang:
A Novel ReRAM-based Main Memory Structure for Optimizing Access Latency and Reliability. 82:1-82:6 - Nikhil Gupta, Fei Chen, Nektarios Georgios Tsoutsos, Michail Maniatakos:
ObfusCADe: Obfuscating Additive Manufacturing CAD Models Against Counterfeiting: Invited. 82:1-82:6 - S. Ramesh, Birgit Vogel-Heuser, Wanli Chang, Debayan Roy, Licong Zhang, Samarjit Chakraborty:
Specification, Verification and Design of Evolving Automotive Software: Invited. 83:1-83:6 - Shuo-Han Chen, Yen-Ting Chen, Hsin-Wen Wei, Wei-Kuan Shih:
Boosting the Performance of 3D Charge Trap NAND Flash with Asymmetric Feature Process Size Characteristic. 83:1-83:6 - Meng Wu, Haibo Zeng, Chao Wang, Huafeng Yu:
Safety Guard: Runtime Enforcement for Safety-Critical Cyber-Physical Systems: Invited. 84:1-84:6 - Shouyi Yin, Zhicong Xie, Shaojun Wei:
Disturbance Aware Memory Partitioning for Parallel Data Access in STT-RAM. 84:1-84:6 - Cédric Killian, Daniel Chillet, Sébastien Le Beux, Van-Dung Pham, Olivier Sentieys, Ian O'Connor:
Energy and Performance Trade-off in Nanophotonic Interconnects using Coding Techniques. 85:1-85:6 - Yandan Wang, Wei Wen, Beiye Liu, Donald M. Chiarulli, Hai (Helen) Li:
Group Scissor: Scaling Neuromorphic Computing Design to Large Neural Networks. 85:1-85:6 - Zhehui Wang, Zhengbin Pang, Peng Yang, Jiang Xu, Xuanqi Chen, Rafael K. V. Maeda, Zhifei Wang, Luan H. K. Duong, Haoran Li, Zhe Wang:
MOCA: an Inter/Intra-Chip Optical Network for Memory. 86:1-86:6 - M. Amimul Ehsan, Hongyu An, Zhen Zhou, Yang Yi:
Adaptation of Enhanced TSV Capacitance as Membrane Property in 3D Brain-inspired Computing System. 86:1-86:6 - Chenchen Liu, Miao Hu, John Paul Strachan, Hai (Helen) Li:
Rescuing Memristor-based Neuromorphic Design with High Defects. 87:1-87:6 - Bhavya K. Daya, Li-Shiuan Peh, Anantha P. Chandrakasan:
Low-Power On-Chip Network Providing Guaranteed Services for Snoopy Coherent and Artificial Neural Network Systems. 87:1-87:6 - Lei Yang, Weichen Liu, Peng Chen, Nan Guan, Mengquan Li:
Task Mapping on SMART NoC: Contention Matters, Not the Distance. 88:1-88:6 - Karthi Duraisamy, Hao Lu, Partha Pratim Pande, Ananth Kalyanaraman:
Accelerating Graph Community Detection with Approximate Updates via an Energy-Efficient NoC. 89:1-89:6 - Andrea Lottarini, Stephen A. Edwards, Kenneth A. Ross, Martha A. Kim:
Network Synthesis for Database Processing Units. 90:1-90:6
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