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ORCIDDFT 1999: Albuquerque, NM, USA
- 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), November 1-3, 1999, Albuquerque, NM, USA, Proceedings. IEEE Computer Society 1999, ISBN 0-7695-0325-X
Session 1: Yield I
- Arunshankar Venkataraman, Israel Koren:
Determination of Yield Bounds Prior to Routing. 4-13 - Julie D. Segal, Sergei Bakarian, Ron Ross:
Impact of Simulation Parameters on Critical Area Analysis. 14-
Session 2: Yield II
- Glenn H. Chapman, Yves Audet:
Creating 35 mm Camera Active Pixel Sensors. 22-30 - Markus Rudack, Dirk Niggemeyer:
Yield Enhancement Considerations for a Single-Chip Multiprocessor System with Embedded DRAM. 31-39 - Nobuhiro Tomabechi:
Multi-Dimensional Subsystem-Dividing for Yield Enhancement in Defect-Tolerant WSI Systems. 40-45 - Stuart L. Riley:
Limitations to Estimating Yield Based on In-Line Defect Measurements. 46-54 - Witold A. Pleskacz:
Yield Estimation of VLSI Circuits with Downscaled Layouts. 55-60 - Frederic Duvivier:
Automatic Detection of Spatial Signature on Wafermaps in a High Volume Production. 61-
Session 3: Testing Techniques
- James F. Plusquellic, Amy Germida, Zheng Yan:
8-Bit Multiplier Simulation Experiments Investigating the Use of Power Supply Transient Signals for the Detection of CMOS Defects. 68-76 - Ching-Hwa Cheng, Shih-Chieh Chang, Jinn-Shyan Wang, Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits. 77-85 - Spyros Tragoudas, N. Denny:
Testing for Path Delay Faults Using Test Points. 86-94 - Y. Tsiatouhas, Th. Haniotakis:
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. 95-100 - Sule Ozev, Alex Orailoglu:
Low-Cost Test for Large Analog IC's. 101-
Session 4: Built-In Self-Test Architectures
- Wenyi Feng, Fred J. Meyer, Fabrizio Lombardi:
Novel Control Pattern Generators for Interconnect Testing with Boundary Scan. 112-120 - Xrysovalantis Kavousianos, Dimitris Bakalis, Haridimos T. Vergos, Dimitris Nikolos, George Alexiou:
Low Power Dissipation in BIST Schemes for Modified Booth Multipliers. 121-129 - Dimitrios Kagaris, Spyros Tragoudas:
LFSR/SR Pseudo-Exhaustive TPG in Fewer Test Cycles. 130-138 - Marco Brazzarola, Franco Fummi:
Power Characterization of LFSRs. 139-147 - Xiaodong Zhang, Kaushik Roy:
Design and Synthesis of Low Power Weighted Random Pattern Generator Considering Peak Power Reduction. 148-
Session 5: Fault Modeling and Simulation
- Stefano Bertazzoni, Gian Carlo Cardarilli, D. Piergentili, Marcello Salmeri, Adelio Salsano, Domenico Di Giovenale, G. C. Grande, P. Marinucci, S. Sperandei, S. Bartalucci, G. Mazzenga, Marco Ricci, V. Bidoli, D. de Francesco, Piergiorgio Picozza, A. Rovelli:
Failure Tests on 64 Mb SDRAM in Radiation Environment. 158-164 - Chi-Feng Wu, Chih-Tsun Huang, Cheng-Wen Wu
:
RAMSES: A Fast Memory Fault Simulator. 165-173 - Marco Brera, Fabrizio Ferrandi, Donatella Sciuto, Franco Fummi:
Increase the Behavioral Fault Model Accuracy Using High-Level Synthesis Information. 174-180 - Firas Khadour, Xiaoling Sun:
Fast Signature Simulation for PPSFP Simulators. 181-
Session 6: Design for Testing
- Nohpill Park, Fabrizio Lombardi:
Stratified Testing of Multichip Module Systems under Uneven Known-Good-Yield. 192-200 - Jin-Fu Li, Cheng-Wen Wu:
Testable and Fault Tolerant Design for FFT Networks. 201-209 - Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante:
Soft-Error Detection through Software Fault-Tolerance Techniques. 210-218 - Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante:
Optimal Vector Selection for Low Power BIST. 219-226 - Markus Seuring, Michael Gössel:
A Structural Approach for Space Compaction for Sequential Circuits. 227-
Session 7: Self-Checking Processing Units and Systems
- Parag K. Lala, Anup Singh, Alvernon Walker:
A CMOS-Based Logic Cell for the Implementation of Self-Checking FPGAs. 238-246 - Cristiana Bolchini, Luigi Pomante, Donatella Sciuto, Fabio Salice:
A Synthesis Methodology Aimed at Improving the Quality of TSC Devices. 247-255 - W. Lynn Gallagher, Earl E. Swartzlander Jr.:
Power Consumption in Fast Dividers Using Time Shared TMR. 256-264 - Vincenzo Piuri, Earl E. Swartzlander Jr.:
Time-Shared Modular Redundancy for Fault-Tolerant FFT Processors. 265-273 - Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Vincenzo Piuri:
Implementing a Self-Checking Neural System for Photon Event Identification by SRAM-Based FPGAs. 274-
Session 8: Self-Checking Memories and Interconnections
- Kiattichai Saowapa, Haruhiko Kaneko, Eiji Fujiwara:
Systematic Deletion/Insertion Error Correcting Codes with Random Error Correction Capability. 284-292 - William D. Armitage, Jien-Chung Lo:
Erasure Error Correction with Hardware Detection. 293-301 - Gian Carlo Cardarilli, Stefano Bertazzoni, Marcello Salmeri, Adelio Salsano, P. Marinucci:
Design of Fault-Tolerant Solid State Mass Memory. 302-310 - Yasunao Katayama, Eric J. Stuckey, Sumio Morioka, Zhao Wu:
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention. 311-318 - C. Wickman, Duncan G. Elliott, Bruce F. Cockburn:
Cost Models for Large File Memory DRAMs with ECC and Bad Block Marking. 319-
Session 9: Diagnosis
- Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra:
Transient and Permanent Fault Diagnosis for FPGA-Based TMR Systems. 330-338 - Yiorgos Makris, Alex Orailoglu:
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths. 339-347 - Fred J. Meyer, Fabrizio Lombardi, Jun Zhao:
Good Processor Identification in Two-Dimensional Grids. 348-356 - Sasikumar Cherubal, Abhijit Chatterjee:
A Methodology for Efficient Simulation and Diagnosis of Mixed-Signal Systems Using Error Waveforms. 357-
Session 10: Reconfiguration
- Wenyi Feng, Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi:
Reconfiguration of One-Time Programmable FPGAs with Faulty Logic Resources. 368-376 - Abderrahim Doumar, Satoshi Kaneko, Hideo Ito:
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. 377-385 - John C. Lach, William H. Mangione-Smith, Miodrag Potkonjak:
Algorithms for Efficient Runtime Fault Recovery on Diverse FPGA Architectures. 386-394 - Sumito Nakano, Naotake Kamiura, Yutaka Hata, Nobuyuki Matsui:
Reconfiguration of Two-Dimensional Meshes Embedded in Faulty Hypercubes. 395-403
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