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ORCIDDFT 2017: Cambridge, United Kingdom
- IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2017, Cambridge, United Kingdom, October 23-25, 2017. IEEE Computer Society 2017, ISBN 978-1-5386-0362-8
- Rishad A. Shafik, Qiaoyan Yu, S. Saqib Khursheed, Antonio Miele
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Welcome Message. - Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai:
A dynamic test compaction method on low power test generation based on capture safe test vectors. 1-6 - Mert Atamaner, Oguz Ergin, Marco Ottavi, Pedro Reviriego:
Detecting errors in instructions with bloom filters. 1-4 - Amir Mahdi Hosseini Monazzah, Hamed Farbeh, Seyed Ghassem Miremadi:
Investigating the effects of process variations and system workloads on endurance of non-volatile caches. 1-6 - Shoba Gopalakrishnan, Virendra Singh:
REMORA: A hybrid low-cost soft-error reliable fault tolerant architecture. 1-6 - Jyothish Soman, Timothy M. Jones:
High performance fault tolerance through predictive instruction re-execution. 1-4 - Lucas Weigel, Fernando Fernandes, Philippe O. A. Navaux, Paolo Rech:
Kernel vulnerability factor and efficient hardening for histogram of oriented gradients. 1-6 - Alexander Schneider, Paul Pop, Jan Madsen:
Volume management for fault-tolerant continuous-flow microfluidics. 1 - Nguyen T. H. Nguyen, Ediz Cetin, Oliver Diessel:
Scheduling voter checks to detect configuration memory errors in FPGA-based TMR systems. 1-4 - Kedar Janardan Dhori, Hitesh Chawla, Ashish Kumar, Prashant Pandey, Promod Kumar, Lorenzo Ciampolini, Florian Cacho, Damien Croain:
High-yield design of high-density SRAM for low-voltage and low-leakage operations. 1-6 - Vasileios Tenentes, Charles Leech, Graeme M. Bragg, Geoff V. Merrett, Bashir M. Al-Hashimi, Hussam Amrouch, Jörg Henkel, Shidhartha Das:
Hardware and software innovations in energy-efficient system-reliability monitoring. 1-5 - Marco Restifo, Paolo Bernardi, Sergio de Luca, Alessandro Sansonetti:
On-line software-based self-test for ECC of embedded RAM memories. 1-6 - Andrea Fedi, Marco Ottavi, Gianluca Furano, Antimo Bruno, Roberto Senesi, Carla Andreani, Carlo Cazzaniga:
High-energy neutrons characterization of a safety critical computing system. 1-4 - Gokulkrishnan Vadakkeveedu, V. Kamakoti, Nitin Chandrachoodan, Seetal Potluri:
A scalable pseudo-exhaustive search for fault diagnosis in microfluidic biochips. 1-4 - Yu Xie, Chen Yang, Chuang-An Mao, He Chen, Yizhuang Xie:
A novel low-overhead fault tolerant parallel-pipelined FFT design. 1-4 - Yu-Wei Lee, Nur A. Touba:
Improving test compression with multiple-polynomial LFSRs. 1-4 - R. Cantora, Ernesto Sánchez, Matteo Sonza Reorda, Giovanni Squillero, Emanuele Valea:
On the optimization of SBST test program compaction. 1-4 - H. Junqi, T. Nandha Kumar, Haider Abbas, Fabrizio Lombardi:
Simulation-based evaluation of frequency upscaled operation of exact/approximate ripple carry adders. 1-6 - Frank Sill Torres, Pedro Fausto Rodrigues Leite, Rolf Drechsler:
Unintrusive aging analysis based on offline learning. 1-4 - Prashant D. Joshi, Arunabha Sen, D. Frank Hsu, Said Hamdioui, Koen Bertels:
Region based containers - A new paradigm for the analysis of fault tolerant networks. 1-4 - Lake Bu, Hien D. Nguyen, Michel A. Kinsy:
RASSS: A perfidy-aware protocol for designing trustworthy distributed systems. 1-6 - Harshad Dhotre, Stephan Eggersglüß, Mehdi Dehbashi, Ulrike Pfannkuchen, Rolf Drechsler:
Machine learning based test pattern analysis for localizing critical power activity areas. 1-6 - Jain-De Li, Sying-Jyan Wang, Katherine Shu-Min Li, Tsung-Yi Ho:
Design-for-testability for paper-based digital microfluidic biochips. 1 - Xin Fan, Jan Stuijt, Tobias Gemmeke:
Towards SRAM leakage power minimization by aggressive standby voltage scaling - Experiments on 40nm test chips. 1-4 - Bing Li, Ulf Schlichtmann:
Reliability-aware synthesis and fault test of fully programmable valve arrays (FPVAs). 1 - Chiara Sandionigi, Maurício Altieri, Olivier Héron:
Early estimation of aging in the design flow of integrated circuits through a programmable hardware module. 1-6 - Tiago A. O. Alves, Sandip Kundu, Leandro A. J. Marzulo, Felipe M. G. França:
A resilient scheduler for dataflow execution. 1-4 - Sina Boroumand, Hadi Parandeh-Afshar, Philip Brisk, Siamak Mohammadi:
CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. 1-6 - Glenn H. Chapman, Parham Purbakht, Peter Le, Israel Koren, Zahava Koren:
Exploring soft errors (SEUs) with digital imager pixels ranging from 7 to 1.3 μm. 1-4 - Leandro Santiago, Vinay C. Patil, Charles B. Prado, Tiago A. O. Alves, Leandro A. J. Marzulo, Felipe M. G. França, Sandip Kundu:
Realizing strong PUF from weak PUF via neural computing. 1-6 - Taniya Siddiqua, Vilas Sridharan, Steven E. Raasch, Nathan DeBardeleben, Kurt B. Ferreira, Scott Levy, Elisabeth Baseman, Qiang Guan:
Lifetime memory reliability data from the field. 1-6 - Sebastian Huhn, Stephan Eggersglüß, Rolf Drechsler:
Reconfigurable TAP controllers with embedded compression for large test data volume. 1-6 - Michiya Kanda, Masaki Hashizume, Hiroyuki Yotsuyanagi, Shyue-Kung Lu:
A defective level monitor of open defects in 3D ICs with a comparator of offset cancellation type. 1-4 - Satyadev Ahlawat, Darshit Vaghani, Virendra Singh:
Preventing scan-based side-channel attacks through key masking. 1-4 - Alessandro Baldassari, Cristiana Bolchini, Antonio Miele:
A dynamic reliability management framework for heterogeneous multicore systems. 1-6 - Mihalis Psarakis, Aitzan Sari:
A scrubbing scheduling approach for reliable FPGA multicore processors with real-time constraints. 1-4 - Mauricio D. Gutierrez, Vasileios Tenentes, Tom J. Kazmierski, Daniele Rossi:
Low cost error monitoring for improved maintainability of IoT applications. 1-6 - Pai-Shun Ting, John P. Hayes:
Eliminating a hidden error source in stochastic circuits. 1-6 - Haider Alrudainy, Rishad A. Shafik, Andrey Mokhov, Alex Yakovlev:
Lifetime reliability characterization of N/MEMS used in power gating of digital integrated circuits. 1-6
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last updated on 2024-09-25 00:32 CEST by the dblp team
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