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20th FDL 2017: Verona, Italy

Name: dblp XML data dump
Creator: Schloss Dagstuhl - Leibniz Center for Informatics
Published: 1993
License: https://creativecommons.org/publicdomain/zero/1.0/
Keywords: dblp, XML, computer science, scholarly publications, metadata

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Daniel Große, Sara Vinco, Hiren D. Patel:
Languages, Design Methods, and Tools for Electronic System Design - Selected Contributions from FDL 2017 [Verona, Italy, September 18-20, 2017]. Lecture Notes in Electrical Engineering 530, Springer 2019, ISBN 978-3-030-02214-3
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Stefano Centomo, Michele Lora, Antonio Portaluri, Francesco Stefanni, Franco Fummi:
Automatic Integration of HDL IPs in Simulink Using FMI and S-Function Interfaces. 1-23
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Vladimir Herdt, Hoang M. Le, Daniel Große, Rolf Drechsler:
Towards Early Validation of Firmware-Based Power Management Using Virtual Prototypes: A Constrained Random Approach. 25-44
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Guillaume Baudart, Timothy Bourke, Marc Pouzet:
Symbolic Simulation of Dataflow Synchronous Programs with Timers. 45-70
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Andrey Mokhov, Alessandro de Gennaro, Ghaith Tarawneh, Jonny Wray, Georgy Lukyanov, Sergey Mileiko, Joe Scott, Alex Yakovlev, Andrew D. Brown:
Language and Hardware Acceleration Backend for Graph Processing. 71-88
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Enrico Fraccaroli, Francesco Stefanni, Franco Fummi, Mark Zwolinski:
Fault Analysis in Analog Circuits Through Language Manipulation and Abstraction. 89-105
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Arthur Kalsing, Laurent Fesquet, Chouki Aktouf:
A Methodology for Automated Consistency Checking Between Different Power-Aware Descriptions. 107-127

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