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ORCID26th FPL 2016: Lausanne, Switzerland
- Paolo Ienne, Walid A. Najjar, Jason Helge Anderson, Philip Brisk, Walter Stechele:
26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. IEEE 2016, ISBN 978-2-8399-1844-2 - Paolo Ienne, Walid A. Najjar
, Jason Helge Anderson, Philip Brisk, Walter Stechele:
Preface. 1 - Chin Hau Hoo, Yajun Ha, Akash Kumar:
ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioning. 1-11 - Dries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt:
Runtime-quality tradeoff in partitioning based multithreaded packing. 1-9 - Aaron Stoddard, Ammon Gruwell, Peter Zabriskie, Michael J. Wirthlin:
High-speed PCAP configuration scrubbing on Zynq-7000 All Programmable SoCs. 1-8 - Que Yanghua, Harnhua Ng, Nachiket Kapre:
Boosting convergence of timing closure using feature selection in a Learning-driven approach. 1-9 - Elias Vansteenkiste, Seppe Lenders, Dirk Stroobandt:
Liquid: Fast placement prototyping through steepest gradient descent movement. 1-4 - Weina Lu, Yu Hu, Jing Ye, Xiaowei Li:
TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAs. 1-4 - Zdenek Vasícek, Lukás Sekanina:
Search-based synthesis of approximate circuits implemented into FPGAs. 1-4 - Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko:
Fast hierarchical NPN classification. 1-4 - Shrikant Vyas, Naveen Kumar Dumpala, Russell Tessier, Daniel E. Holcomb:
Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placement. 1-4 - Huimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang:
A high performance FPGA-based accelerator for large-scale convolutional neural networks. 1-9 - Xitian Fan, Huimin Li, Wei Cao, Lingli Wang:
DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applications. 1-9 - Onur Ulusel, Christopher B. Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar:
Hardware acceleration of feature detection and description algorithms on low-power embedded platforms. 1-9 - Xiaoyin Ma, Jose M. Rodriguez Borbon, Walid A. Najjar, Amit K. Roy-Chowdhury:
Optimizing hardware design for Human Action Recognition. 1-11 - Hugo Fernandes, M. Awais Aslam, Jorge Lobo, João Filipe Ferreira, Jorge Dias:
Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robot. 1-4 - Jose Canilho, Mário P. Véstias, Horácio C. Neto:
Multi-core for K-means clustering on FPGA. 1-4 - Eriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Krishnan Srivatsan, Debbie Marr:
Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASIC. 1-4 - Yongming Shen, Michael Ferdman, Peter A. Milder:
Overcoming resource underutilization in spatial CNN accelerators. 1-4 - Jungwook Choi, Rob A. Rutenbar:
Configurable and scalable belief propagation accelerator for computer vision. 1-4 - Kumar H. B. Chethan, Nachiket Kapre:
Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAs. 1-10 - Mohamed S. Abdelfattah, Vaughn Betz:
LYNX: CAD for FPGA-based networks-on-chip. 1-10 - David Sidler, Zsolt István, Gustavo Alonso:
Low-latency TCP/IP stack for data center applications. 1-4 - Mario Ruiz, Javier Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna:
Harnessing Programmable SoCs to develop cost-effective network quality monitoring devices. 1-4 - Furkan Turan, Ruan de Clercq, Pieter Maene, Oscar Reparaz, Ingrid Verbauwhede:
Hardware acceleration of a software-based VPN. 1-9 - Luke Newmeyer, Doran Wilde, Brent E. Nelson, Michael J. Wirthlin:
Efficient processing of phased array radar in sense and avoid application using heterogeneous computing. 1-8 - Benjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser:
Modeling considerations for the hardware-software co-design of flexible modern wireless transceivers. 1-4 - Esam El-Araby, Nader M. Namazi:
Chaotic architectures for secure free-space optical communication. 1-5 - Farheen Fatima Khan, Andy Gean Ye:
An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architectures. 1-11 - Oleg Petelin, Vaughn Betz:
The speed of diversity: Exploring complex FPGA routing topologies for the global metal layer. 1-10 - Jotham Vaddaboina Manoranjan, Kenneth S. Stevens:
Reconfigurable circuit for implementation of family of 4-phase latch protocols. 1-4 - Mohammad Naouss, François Marc:
Modelling delay degradation due to NBTI in FPGA Look-up tables. 1-4 - Zeke Wang, Johns Paul, Hui Yan Cheah, Bingsheng He, Wei Zhang:
Relational query processing on OpenCL-based FPGAs. 1-10 - Raphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama:
Annotation-based finite-state transducers on reconfigurable devices. 1-9 - Yubin Li, Yuliang Sun, Guohao Dai, Qiang Xu, Yu Wang, Huazhong Yang:
Approximate Frequent Itemset Mining for streaming data on FPGA. 1-4 - Hao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk:
Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modules. 1-8 - Ren Chen, Viktor K. Prasanna:
Optimizing interconnection complexity for realizing fixed permutation in data and signal processing algorithms. 1-9 - Malte Vesper, Dirk Koch, Kizheppatt Vipin, Suhaib A. Fahmy:
JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communication. 1-9 - Jacob Couch, John Arkoian:
An investigation into a circuit based supply chain analyzer for FPGAs. 1-9 - Ammon Gruwell, Peter Zabriskie, Michael J. Wirthlin:
High-speed programmable FPGA Configuration through JTAG. 1-4 - Junshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto:
A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switch. 1-4 - Antonios Prodromakis, Nikolaos Papandreou, Eleni Bougioukou, Urs Egger, Nikos Toulgaridis, Theodore Antonakopoulos, Haralampos Pozidis, Evangelos Eleftheriou:
Controller architecture for low-latency access to phase-change memory in OpenPOWER systems. 1-4 - Dimitris Agiakatsikas, Ediz Çetin, Oliver Diessel:
FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCs. 1-4 - Pierre-Henri Horrein, Benoit Porteboeuf, André Lalevee:
Ouessant: Microcontroller approach for flexible accelerator integration and control in System-on-Chip. 1-4 - Behnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi:
Stress-aware routing to mitigate aging effects in SRAM-based FPGAs. 1-8 - Ibrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz:
Measure twice and cut once: Robust dynamic voltage scaling for FPGAs. 1-11 - Ilya Ganusov, Benjamin Devlin:
Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCs. 1-9 - Ilya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das:
Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAs. 1-10 - Daisuke Suzuki, Takahiro Hanyu:
A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure. 1-4 - Yusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano:
Body bias grain size exploration for a coarse grained reconfigurable accelerator. 1-4 - Ismail San, Nicole Fern, Çetin Kaya Koç, Kwang-Ting Cheng:
Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreams. 1-4 - Petter Kallstrom, Oscar Gustafsson:
Fast and area efficient adder for wide data in recent Xilinx FPGAs. 1-4 - Zhenzhong Xiao, Dirk Koch, Mikel Luján:
A partial reconfiguration controller for Altera Stratix V FPGAs. 1-4 - Heiner Giefers, Peter W. J. Staar, Raphael Polig:
Energy-efficient stochastic matrix function estimator for graph analytics on FPGA. 1-9 - Srikanth Sridharan, Paolo Durante, Christian Faerber, Niko Neufeld:
Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architectures. 1-7 - Paul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer J. Sherwin:
Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGA. 1-9 - Kaan Kara, Gustavo Alonso:
Fast and robust hashing for database operators. 1-4 - Charalabos Kritikakis, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos:
An FPGA-based high-throughput stream join architecture. 1-4 - Wei Liang, Wenbo Yin, Ping Kang, Lingli Wang:
Memory efficient and high performance key-value store on FPGA using Cuckoo hashing. 1-4 - Yufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula:
Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGA. 1-8 - M. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich:
FPGA-based accelerator design from a domain-specific language. 1-9 - Charles Lo, Paul Chow:
Model-based optimization of High Level Synthesis directives. 1-10 - Xinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk:
EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits. 1-4 - Nina Engelhardt, Hayden Kwok-Hay So:
GraVF: A vertex-centric distributed graph processing framework on FPGAs. 1-4 - Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre:
Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. 1-4 - Burak Unal, Ali Akoglu:
Resource efficient real-time processing of Contrast Limited Adaptive Histogram Equalization. 1-8 - Xijie Jia, Kaiyuan Guo, Wenqiang Wang, Yu Wang, Huazhong Yang:
SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGA. 1-8 - Sichao Wang, Tsutomu Maruyama:
An implementation method of the box filter on FPGA. 1-8 - Konstantinos Boikos, Christos-Savvas Bouganis:
Semi-dense SLAM on an FPGA SoC. 1-4 - Yanzhe Li, Kai Huang, Luc Claesen:
SoC and FPGA oriented high-quality stereo vision system. 1-4 - Jori Winderickx, Joan Daemen, Nele Mentens:
Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAs. 1-4 - Malik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski:
Hardware-software codesign of RSA for optimal performance vs. flexibility trade-off. 1-4 - Pietro Fezzardi, Fabrizio Ferrandi:
Automated bug detection for pointers and memory accesses in High-Level Synthesis compilers. 1-9 - Dong Liu, Benjamin Carrión Schäfer:
Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAs. 1-8 - Jeffrey Goeders, Steven J. E. Wilton:
Quantifying observability for in-system debug of high-level synthesis circuits. 1-11 - Ioannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas:
SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On Chip. 1-4 - Bajaj Ronak, Suhaib A. Fahmy:
Improved resource sharing for FPGA DSP blocks. 1-4 - Martin Kumm, Marco Kleinlein, Peter Zipf:
Efficient sum of absolute difference computation on FPGAs. 1-4 - Bruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi:
Runtime reconfigurable beamforming architecture for real-time sound-source localization. 1-4 - Christophe Huriaux, Olivier Sentieys, Russell Tessier:
Effects of I/O routing through column interfaces in embedded FPGA fabrics. 1-9 - Hadi Mardani Kamali, Shaahin Hessabi:
AdapNoC: A fast and flexible FPGA-based NoC simulator. 1-8 - Tuan D. A. Nguyen, Akash Kumar:
XNoC: A non-intrusive TDM circuit-switched Network-on-Chip. 1-11 - Oto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer, Lilian Bossuet:
A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devices. 1-10 - Nachiket Kapre, Samuel Bayliss:
Survey of domain-specific languages for FPGA computing. 1-12 - Christoforos Kachris, Dimitrios Soudris:
A survey on reconfigurable accelerators for cloud computing. 1-10 - Baptiste Delporte, Anthony Convers, Roberto Rigamonti, Alberto Dassatti:
Transparent FPGA flow. 1 - Bruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi:
A runtime reconfigurable FPGA-based microphone array for sound source localization. 1 - Arief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau:
Demonstration of a context-switch method for heterogeneous reconfigurable systems. 1 - Thomas Townsend, Brent E. Nelson, Michael J. Wirthlin:
An XDL alternative for interfacing RapidSmith and Vivado. 1 - Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang:
HeteroSim: A heterogeneous CPU-FPGA simulator. 1 - Ahmet Caner Yuzuguler, William Andrew Simon, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
Single-FPGA 3D ultrasound beamformer. 1 - Fellipe Montero, Guy Bois, Eric Jenn, Kevin Duplantier:
Architectural exploration and implementation of an image processing chain with SpaceStudio™. 1 - Mikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne:
Designing a virtual runtime for FPGA accelerators in the cloud. 1-2 - Fraser D. Robinson, Louise H. Crockett, William H. Nailon, Robert W. Stewart:
High-level synthesis for medical image processing on Systems on Chip: A case study. 1-2 - William Andrew Simon, Ahmet Caner Yuzuguler, Aya Ibrahim, Federico Angiolini, Marcel Arditi, Jean-Philippe Thiran, Giovanni De Micheli:
Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer. 1-2 - Size Xiao, Adam Postula, Neil W. Bergmann:
Optimal random sampling based path planning on FPGAs. 1-2 - Leandro Andrade Martinez, Eduardo Marques:
A hardware/software codesign framework for vision-based ADAS. 1-2 - Daniel Fenzandez, Carlos González, Daniel Mozos:
Dimensionality reduction of hyperspectral images using reconfigurable hardware. 1-2 - Jan Viktorin, Jan Korenek:
Packet processing on FPGA SoC with DPDK. 1-2 - Muhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat:
Towards a hardware-assisted information flow tracking ecosystem for ARM processors. 1-2 - Daniel Da Costa Dinis, Rui Fiel Cordeiro, Arnaldo S. R. Oliveira, José M. N. Vieira:
Towards an all-digital antenna array transmitter. 1-2
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