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ORCIDFPT 2009: Sydney, Australia
- Neil W. Bergmann, Oliver Diessel, Lesley Shannon:
Proceedings of the 2009 International Conference on Field-Programmable Technology, FPT 2009, Sydney, Australia, December 9-11, 2009. IEEE Computer Society 2009, ISBN 978-1-4244-4377-2 - Gordon J. Brebner
:
Packets everywhere: The great opportunity for field programmable technology. 1-10 - Jürgen Teich:
From dynamic reconfiguration to self-reconfiguration: Invasive algorithms and architectures. 11-12 - John D. Bunton:
ASKAP beamformer. 13 - Oliver Sander, Benjamin Glas, Christoph Roth, Jürgen Becker, Klaus D. Müller-Glaser:
Design of a Vehicle-to-Vehicle communication system on reconfigurable hardware. 14-21 - Donald G. Bailey, Christos-Savvas Bouganis:
Implementation of a foveal vision mapping. 22-29 - Lifan Yao, Hao Feng, Yiqun Zhu, Zhiguo Jiang, Danpei Zhao, Wenquan Feng:
An architecture of optimised SIFT feature detection for an FPGA implementation of an image matcher. 30-37 - Muhammad Shafiq, Miquel Pericàs, Raúl de la Cruz, Mauricio Araya-Polo, Nacho Navarro, Eduard Ayguadé:
Exploiting memory customization in FPGA for 3D stencil computations. 38-45 - Paul Beckett:
Towards a balanced ternary FPGA. 46-53 - Alastair M. Smith, George A. Constantinides, Steven J. E. Wilton, Peter Y. K. Cheung:
Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design. 54-61 - Chia-Ching Tung, Ruchi B. Rungta, Eric Peskin:
Simulation of a QCA-based CLB and a multi-CLB application. 62-69 - Hadi Parandeh-Afshar, Alessandro Cevrero, Panagiotis Athanasopoulos, Philip Brisk, Yusuf Leblebici, Paolo Ienne:
A flexible DSP block to enhance FPGA arithmetic performance. 70-77 - Benjamin Gojman, André DeHon:
VMATCH: Using logical variation to counteract physical variation in bottom-up, nanoscale systems. 78-87 - Xiao Dong, Guy G. F. Lemieux:
PGR: Period and glitch reduction via clock skew scheduling, delay padding and GlitchLess. 88-95 - Eddie Hung, Steven J. E. Wilton, Haile Yu, Thomas C. P. Chau, Philip Heng Wai Leong:
A detailed delay path model for FPGAs. 96-103 - Keiichiro Hirai, Masaru Kato, Yoshiki Saito, Hideharu Amano:
Leakage power reduction for coarse-grained dynamically reconfigurable processor arrays using Dual Vt cells. 104-111 - Husain Parvez, Zied Marrakchi, Habib Mehrez:
ASIF: Application Specific Inflexible FPGA. 112-119 - Daniel Le Ly, Manuel Saldaña, Paul Chow:
The challenges of using an embedded MPI for hardware-based processing nodes. 120-127 - Tim Güneysu, Christof Paar:
Transforming write collisions in block RAMs into security applications. 128-134 - Abdulazim Amouri, Farhadur Arifin, Frank Hannig, Jürgen Teich:
FPGA implementation of an invasive computing architecture. 135-142 - Neil Hockert, Katherine Compton:
FFPU: Fractured floating point unit for FPGA soft processors. 143-150 - David Grant, Graeme Smecher, Guy Lemieux, Rosemary Francis:
Rapid synthesis and simulation of computational circuits in an MPPA. 151-158
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