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ORCIDHLDVT 2008: Incline Village, NV, USA
- IEEE International High Level Design Validation and Test Workshop, HLDVT 2008, Incline Village, NV, USA, November 19-21, 2008. IEEE Computer Society 2008, ISBN 978-1-4244-2922-6
SOC Verification Methodologies
- Xiaoxi Xu, Cheng-Chew Lim
, Michael J. Liebelt:
Positioning test-benches and test-programs in interaction-oriented system-on-chip verification. 3-10 - Daniel Geist, Oded Vaida:
A method for hunting bugs that occur due to system conflicts. 11-17 - Farzin Karimi:
Applications of decorator and observer design patterns in functional verification. 18-22
Test
- Wei-Lin Li, Tsung-Tang Chen, Po-Han Wu, Jiann-Chyi Rau:
Test slice difference technique for low power encoding. 25-32
Panel - Software Practices for Verification/ Testbench Management
- Shireesh Verma, Srinath Atluri, Valeria Bertacco, Mark Glasser, Badri Gopalan, Sharon Rosenberg:
Panel: Software practices for verification/testbench management. 35-37
Formal Verification
- Ankur Parikh, Michael S. Hsiao:
On dynamic switching of navigation for semi-formal design validation. 41-48 - Tasuku Nishihara, Takeshi Matsumoto, Masahiro Fujita:
Multi-level Bounded Model Checking to detect bugs beyond the bound. 49-55 - Katell Morin-Allory, Marc Boule, Dominique Borrione, Zeljko Zilic:
Proving and disproving assertion rewrite rules with automated theorem provers. 56-63 - Prakash Math, David Hoenig:
Janus: A novel use of Formal Verification for targeted behavioral equivalence. 64-70
Invited Session: On-Chip Instrumentation for Silicon Validation and Debug
- Miron Abramovici:
In-system silicon validation using a reconfigurable platform. 73 - Neal Stollon:
On Chip Instrument application to SoC analysis. 74
Functional Testing and Verification
- Kapila Udawatta, Sergey Maidanov, Mehdi Ehsanian, Surya Musunuri:
Test and validation of a non-deterministic system - True Random Number Generator. 77-84 - Homa Alemzadeh, Zainalabedin Navabi, Stefano Di Carlo, Alberto Scionti, Paolo Prinetto:
Functional testing approaches for "BIFST-able" tlm_fifo. 85-92 - Torsten Schober, Shimon Landa, Bodo Hoppe, Ronny Morad:
IBM system z functional and performance verification using X-Gen. 93-100 - Hassan Hatefi-Ardakani, Amir Masoud Gharehbaghi, Shaahin Hessabi:
Timing verification of distributed network systems at higher levels of abstraction. 101-107
Simulation
- Dusung Kim, Maciej J. Ciesielski, Kyuho Shim, Seiyang Yang:
Temporal parallel gate-level timing simulation. 111-116 - Giuseppe Di Guglielmo, Franco Fummi, Mark Hampton, Graziano Pravadelli, Francesco Stefanni:
The role of parallel simulation in functional verification. 117-124 - Stefano Cordibella, Franco Fummi, Giovanni Perbellini, Davide Quaglia:
A HW/SW co-simulation framework for the verification of multi-CPU systems. 125-131
Panel - SoC Power Management Implications on Validation and Testing
- Bhanu Kapoor, John Goodenough, Shankar Hemmady, Shireesh Verma, Manuel A. d'Abreu, Kaushik Roy:
Panel: SoC power management implications on validation and testing. 135-137
Special Session: What's So Intelligent about Testbenches?
- Avi Ziv, Chris Wilson, Adnan Hamid, Joerg Grosse:
Special session - What's so intelligent about testbenches? 141-142
Coverage and Metrics
- Íñigo Ugarte, Pablo Sanchez:
Optimized coverage-directed random simulation. 145-152 - Kiran Ramineni, Shireesh Verma, Ian G. Harris:
Evaluation of an efficient control-oriented coverage metric. 153-157
Defect and Fault Models and Test
- Kenneth M. Zick, John P. Hayes:
High-level vulnerability over space and time to insidious soft errors. 161-168 - Stefano Di Carlo, Paolo Prinetto, Alberto Scionti, Zaid Al-Ars:
Automating defects simulation and fault modeling for SRAMs. 169-176 - Daniel Gil, Luis J. Saiz, Joaquin Gracia, Juan Carlos Baraza, Pedro J. Gil:
Injecting intermittent faults for the dependability validation of commercial microcontrollers. 177-184
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