default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID27th Hot Chips Symposium 2015: Cupertino, CA, USA
- 2015 IEEE Hot Chips 27 Symposium (HCS), Cupertino, CA, USA, August 22-25, 2015. IEEE 2015, ISBN 978-1-4673-8885-6
- Vamsi Boppana, Sagheer Ahmad
, Ilya Ganusov, Vinod Kathail, Vidya Rajagopalan, Ralph Wittig:
UltraScale+ MPSoC and FPGA families. 1-37 - Hiroe Iwasaki, Takayuki Onishi, Ken Nakamura, Koyo Nitta, Takashi Sano, Yukikuni Nishida, Kazuya Yokohari, Jia Su, Naoki Ono, Ritsu Kusaba, Atsushi Sagata, Mitsuo Ikeda, Atsushi Shimizu:
Professional H.265/HEVC encoder LSI toward high-quality 4K/8K broadcast infrastructure. 1-24 - Venkat Mattela:
IoT device development challenges and solutions. 1-19 - Kalin Ovtcharov, Olatunji Ruwase, Joo-Young Kim, Jeremy Fowers, Karin Strauss, Eric S. Chung:
Toward accelerating deep learning at scale using specialized hardware in the datacenter. 1-38 - May Wu, Ravi Iyer, Yatin Hoskote, Steven Zhang, Julio Zamora-Esquivel, German Fabila Garcia, Ilya Klotchkov, Mukesh Bhartiya:
Design of a low power SoC testchip for wearables and IoTs. 1-27 - John W. Lockwood:
Comparison of Key/Value Store (KVS) in software and programmable hardware. 1-8 - Zhimin Ding:
Ultra-low-light CMOS biosensor helps tackle infectious diseases. 1-23 - Joe Macri:
AMD's next generation GPU and high bandwidth memory architecture: FURY. 1-26 - Roland Memisevic:
Deep learning: Architectures, algorithms, applications. 1-127 - Gyeonghoon Kim, Hoi-Jun Yoo:
A low-power and real-time augmented reality processor for the next generation smart glasses. 1 - Vrajesh Bhavsar:
Current trends for hardware and software developers. 1-36 - Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Brandon H. Dwiel, Rangeen Basu Roy Chowdhury, Vinesh Srinivasan, Steve Lipa, Eric Rotenberg, W. Rhett Davis, Paul D. Franzon:
Under 100-cycle thread migration latency in a single-ISA heterogeneous multi-core processor. 1 - Ian Bratt:
The ARM® Mali-T880 Mobile GPU. 1-27 - Adrian Tang, John Demme, Simha Sethumadhavan, Salvatore J. Stolfo:
A silicon anti-virus engine. 1 - Zoran Nikolic, Rama Venkatasubramanian, Jason A. T. Jones, Peter Labaziewicz:
A scalable heterogeneous multicore architecture for ADAS: Presented at HOT CHIPS: A symposium on high performance chips Flint Center, Cupertino, CA. 1-32 - Avinash Sodani:
Knights landing (KNL): 2nd Generation Intel® Xeon Phi processor. 1-24 - Basant Vinaik, Rahoul Puri:
Oracle's Sonoma processor: Advanced low-cost SPARC processor for enterprise workloads. 1-23 - Yunsup Lee, Brian Zimmer, Andrew Waterman, Alberto Puggelli, Jaehwa Kwak, Ruzica Jevtic, Ben Keller, Stevo Bailey, Milovan Blagojevic, Pi-Feng Chiu, Henry Cook, Rimas Avizienis, Brian C. Richards, Elad Alon, Borivoje Nikolic, Krste Asanovic:
Raven: A 28nm RISC-V vector processor with integrated switched-capacitor DC-DC converters and adaptive clocking. 1-45 - Dheemanth Nagaraj, Chris Gianos:
Intel® Xeon® Processor D: The First Xeon processor optimized for dense solutions. 1-22 - Yann LeCun:
Deep learning & convolutional networks. 1-95 - Charles Zhang:
Mars: A 64-core ARMv8 processor. 1-23 - Davide Rossi, Francesco Conti, Andrea Marongiu, Antonio Pullini, Igor Loi, Michael Gautschi, Giuseppe Tagliavini, Alessandro Capotondi, Philippe Flatresse, Luca Benini:
PULP: A parallel ultra low power platform for next generation IoT applications. 1-39 - Zheng John Xu:
LS2085/8A Freescale's new QorlQ Layerscape communications processor. 1-25 - Benoît Dupont de Dinechin:
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor. 1-27 - Vinay Gangadhar, Raghuraman Balasubramanian, Mario Drumond, Ziliang Guo, Jai Menon, Cherin Joseph, Robin Prakash, Sharath Prasad, Pradip Vallathol, Karu Sankaralingam:
MIAOW: An open source GPGPU. 1-43 - Matt Grob:
The road to 5G: Providing the connectivity fabric for everything. 1-26 - Andreas Olofsson:
Implementing software defined radio on the paralella. 1-32 - Lucian Codrescu:
Architecture of the Hexagon™ 680 DSP for mobile imaging and computer vision. 1-26 - Sukjin Kim, Young-Hwan Park, Jaehyun Kim, Minsoo Kim, Wonchang Lee, Shihwa Lee:
Flexible video processing platform for 8K UHD TV. 1 - Benton H. Calhoun, David D. Wentzloff:
Ultra-low power wireless SoCs enabling a batteryless IoT. 1-45 - Steven Tu:
Atom™ - x5/x7 Series processor, codenamed Cherry Trail. 1-28 - David Roberts, Amin Farmahini Farahani, Kevin Cheng, Nathan Hu, David Mayhew, Michael Ignatowski:
NMI: A new memory interface to enable innovation. 1 - Christopher Nitta:
Makers from Hobbyists to professionals. 1-5 - Mike Hutton:
Stratix® 10: 14nm FPGA delivering 1GHz. 1-24 - Pete Dokter:
Maker trends: The path of least resistance. 1-21 - Michael Gschwind:
I/O virtualization and system acceleration in POWER8. 1-26 - Koji Yamazaki, Yoshihiro Nakajima, Takahiro Hatano, Akihiko Miyazaki:
Lagopus FPGA - A reprogrammable data plane for high-performance software SDN switches. 1 - Guhan Krishnan, Dan Bouvier, Louis Zhang, Praveen Dongara:
Energy efficient graphics and multimedia in 28NM Carrizo APU. 1-34 - Ramin Shirani, Ramin Farjad-Rad:
10G | 5G | 2.5G | 1G | 100M physical layer PHY: HOT CHIPS 2015 conference. 1-27
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-11 22:55 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
