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ORCIDICCAD 2025: Munich, Germany
- IEEE/ACM International Conference On Computer Aided Design, ICCAD 2025, Munich, Germany, October 26-30, 2025. IEEE 2025, ISBN 979-8-3315-1560-7
- Xuesi Chen, Leo Han, Anvita Bhagavathula, Udit Gupta:
CarbonClarity: Understanding and Addressing Uncertainty in Embodied Carbon for Sustainable Computing. 1-9 - Cheng-Yu Tsai, Suwan Kim, Sung-Kyu Lim:
Capacitance Extraction via Machine Learning with Application to Interconnect Geometry Exploration. 1-9 - Huangxu Chen, Yingbo Hao, Yi Zou, Xinyu Chen:
OA-LAMA: An Outlier-Adaptive LLM Inference Accelerator with Memory-Aligned Mixed-Precision Group Quantization. 1-9 - Hyunje Jo, Han-Sok Suh, Hyun-Seok Heo, Jinseok Kim, Hyunsung Kim, Boeui Hong, Jungju Oh, Sunghyun Park, Jinwook Oh, Sunghwan Jo, Kangwook Lee, Jae-Sun Seo:
CTDM: Resource-Efficient FPGA-Accelerated Simulation of Large-Scale NPU Designs. 1-9 - Fuping Li, Ying Wang, Yinghao Yang, Jingxuan Li, Yibo Du, Huawei Li, Yinhe Han, Hang Lu, Xiaowei Li:
RTPU: Unifying Non-Private and Private Inference with Reconfigurable Architecture. 1-9 - Weijie Peng, Youwei Xiao, Yuyang Zou
, Zizhang Luo, Yun (Eric) Liang:
Clay: High-level ASIP Framework for Flexible Microarchitecture-Aware Instruction Customization. 1-9 - Haoyang Sang, Changhao Yan, Zhaori Bi, Keren Zhu, Xuan Zeng:
BAGNet: A Boundary-Aware Graph Neural Network for SRAM Yield Analysis in Post-LayoutSimulation. 1-9 - Robert Wille, Philipp Ebner, Maria Emmerich, Michel Takken:
The Munich Microfluidics Toolkit: Design Automation and Simulation Tools for Microfluidic Devices. 1-8 - Jiahui Xu, Jordi Cortadella, Lana Josipovic:
Promise: Property Mining for Sequential Synthesis. 1-9 - Qian Jin, Yumeng Liu, Yuqi Jiang, Qi Sun, Cheng Zhuo:
Invited Paper: Unitho: A Unified Multi-Task Framework for Computational Lithography. 1-9 - Sehyeon Chung, Hyunbae Seo, Taewhan Kim:
Synthesis of Standard Cells of Minimum Delay. 1-8 - Shan Shen, Shenglu Hua, Jiajun Zou, Jiawei Liu, Jianwang Zhai, Chuan Shi, Wenjian Yu:
Transferable Parasitic Estimation via Graph Contrastive Learning and Label Rebalancing in AMS Circuits. 1-9 - Bojun Zhang, Jinkai Wang, Xianan Zhu, Ziyuan Guo, Zhengkun Gu, Kaili Zhang, Zhizhong Zhang, Kun Zhang, Weisheng Zhao, Yue Zhang:
HRAMTran: A Hybrid-RAM Transformer Accelerator With Dynamic Sparsity Floating-Point CIM and Written-Back Transpose Array. 1-9 - Jiun-Hao Chen, Jie-Hong R. Jiang, Alan Mishchenko:
Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization. 1-9 - Hongjian Zhou, Haoyu Yang, Nicholas Gangi, Zhaoran Rena Huang, Haoxing Ren, Jiaqi Gu:
Apollo: Automated Routing-Informed Placement for Large-Scale Photonic Integrated Circuits. 1-9 - Yifei Zhu, Dawei Feng, Zhenxuan Luan, Lei Ren, Weiwei Chen, Zhangxi Tan:
Open3DFlow: An Open-Source EDA Platform for 3D Chip Design with AI Enhancement. 1-9 - Junling Fan, David Selasi Koblah, Domenic Forte:
Designing with Deception: ML- and Covert Gate-Enhanced Camouflaging to Thwart IC Reverse Engineering. 1-9 - Zijun Jiang, Yangdi Lyu:
MiCo: End-to-End Mixed Precision Neural Network Co-Exploration Framework for Edge AI. 1-9 - Jihe Wang, Yulu Liu, Yubin Zhang, Danghui Wang:
SCArmor: Layer-Bit Joint Hardening with a Fast Genetic Optimization for Cost-Efficient and High-Reliable SC-DCNN Circuits. 1-9 - Jaekyung Im, Seokhyeong Kang:
A Parallel Analytical Legalization Algorithm via Alternating Direction Method of Multipliers. 1-8 - Xin Hong, Chenjian Li, Aochu Dai, Sanjiang Li, Shenggang Ying, Mingsheng Ying:
Quantum State Preparation Based on LimTDD. 1-8 - Farshad Firouzi, Bahareh J. Farahani, Polykarpos Vergos, Deepesh Sahoo, Nathaniel Bleier, Krishnendu Chakrabarty:
Prompt, Fab, Flex: Agentic LLMs for Flexible Electronics Design. 1-9 - Ferris Prima Nugraha, Yuhan Huang, Jiacheng Liu, Qiming Shao:
Simulation Framework and Optimization of Superconducting Transmon-Tunable Coupler-Transmon System for Qudit Gates. 1-8 - Yuzheng Lin, Lizhou Wu, Chixiao Chen, Xiaoyang Zeng, Haozhe Zhu:
GauPRE: A Pattern-based Rendering Engine for Gaussian Splatting on Edge Device. 1-9 - Samuel Coulon, Jinjun Xiong, Jiafeng Xie:
LEAF: Lightweight and Efficient Hardware Accelerator for Signature Verification of FALCON. 1-9 - Wanli Chang, Yili Guo, Weijie Wang, Yaqi Yao, Fuyang Zhao, Yinjie Fang, Kuan Jiang, Liyun Shang:
Invited Paper: Resource Management on Heterogeneous Chiplets Systems. 1-8 - Marco Ronzani, Cristina Silvano:
QuickFlow: An Efficient Local Search Method to Map Convolutions on Spatial Architectures. 1-9 - Han Zhang, Zhenyu Xue, Wente Yi, Tianshuo Bai, Lehao Tan, Jingcheng Gu, Weijie Ding, Wang Kang, Biao Pan:
PAR-CIM: A Precise/Approximate Reconfigurable Digital CIM Macro with 0.35-4b Fractional Mixed-Bitwidth Quantization. 1-9 - Khurram Khalil, Khaza Anuarul Hoque:
TOGGLE: Temporal Logic-Guided Large Language Model Compression for Edge. 1-9 - Sizhao Li, Chenyu Zhai, Xinhua Wang, Zhujun Guo, Shan He, Donghui Guo:
RePM: Reconfigurable Elastic Computing for Polynomial Multiplier with Hybrid NTT Algorithm. 1-9 - Qiuran Li, Jingkui Yang, Fanjin Xu, Fei Zhang, Xingyu Zhang, Zhe Li, Jinjin Shao, Yaohua Wang:
Secure Token Pruning Mechanism and Accelerator for Vision Transformer. 1-9 - Youran Wu, Shunjie Chang, Jianli Chen, Jun Yu, Kun Wang:
3D CoSim: Coupled Operator Learning-Based Co-Simulator for Transferable 3D-IC Analysis. 1-9 - Zhonghao Chen, Hongtao Zhong, Jianhe Deng, Mulin Shi, Yongpan Liu, Huazhong Yang, Xueqing Li:
DANCE: Dual-Side Agile N:M Sparse Compressed Digital CiM Accelerator for Efficient Compound AI. 1-9 - Seongwoo Choi, Hyunsu Moh, Changjae Yi, Joon Choi, Soonhoi Ha:
Enabling Decoder-only Language Model Inference on a CNN Accelerator. 1-9 - Farbin Fayza, Cansu Demirkiran, Satyavolu Papa Rao, Darius Bunandar, Udit Gupta, Ajay Joshi:
EPiCarbon: A Carbon Modeling Tool for Electro-Photonic Accelerators. 1-9 - Ruiyang Ma, Daikang Kuang, Ziqian Liu, Jiaxi Zhang, Ping Fan, Guojie Luo:
Wit-HW: Bug Localization in Hardware Design Code via Witness Test Case Generation. 1-9 - Christoph Schorn, Axel Sauer, Marius Fischer, Ingo Feldner, Thomas Schamm, Falk Rehm:
Invited Paper: Rapid Performance Evaluation and Optimized AI Inference for Heterogeneous Automotive Chiplets. 1-8 - Thorben Schey, Khaled Karoonlatifi, Michael Weyrich, Andrey Morozov:
Uncertainty-Guided Live Measurement Sequencing for Fast SAR ADC Linearity Testing. 1-9 - Xinyu Qu, Zehua Zhang, Runnan Xu, Yufei Ma:
3D-MoE: Accelerating Multi-Expert Activated LLMs on 3D In/Near-Memory Computing Architecture via Hybrid Parallelism. 1-9 - Salim Ullah, Siva Satyendra Sahoo, Can Li, Chao Li, Liu Liu, Tomas Sousa Pereira, Bo Wen, Xunzhao Yin, Armin Darjani, Nima Kavand, Chakravarthy Bodla, Rupa Yashaswi Panduga, Aniruddh Holemadlu, Johannes Maly, Jonathan Förste, Samarth Vadia, Xiaobo Sharon Hu, Akash Kumar:
Invited Paper: Circuit and Architecture Design with Emerging Computing Paradigms. 1-9 - Chaofang Ma, Lin Jiang, Zeyu Li, Hanwei Fan, Maolin Wang, Jiang Xu, Wei Zhang:
ScanNow: A Scan Window-Based Sparse Matrix Multiplication Accelerator Design. 1-9 - Qingsheng Qiu, Ziwen Zheng, Boyu Shi, Chao Wang:
GeoFA: A Geometric Finite Automaton Engine for Efficient Layout Pattern Matching. 1-9 - Hang Zhou, Zhenjie Lu, Quan Chen:
EI-TR: A Versatile Exponential Integrator Framework for Transient Analysis of Generic Nonlinear Circuits. 1-9 - Yuhang Hao, Yun Wu, Minmin Jiang, Máire O'Neill, Chongyan Gu:
Invited Paper: Rowhammer Mitigation by Approximate Computing: A Compressed Sensing Case Study. 1-8 - Xicheng Xu, Yinghao Yang, Fuyao Liu, Xiaowei Li, Hang Lu:
Uranus: Ultra-efficient Acceleration Architecture for the Privacy Inference of Graph Neural Networks. 1-9 - Shaoqiang Lu, Yangbo Wei, Junhong Qian, Chen Wu, Xiao Shi, Lei He:
MoE-OPU: An FPGA Overlay Processor Leveraging Expert Parallelism for MoE-based Large Language Models. 1-9 - Sangkyu Jeon, Gisan Ji, Yeonggeon Kim, Youngjun Park, Sangyeon Kim, Sungju Ryu:
OptiRange: An Efficient ReRAM-Based PIM Accelerator with ADC Resolution Optimization. 1-9 - Xingyu Chen, Xiangrui Zhang, Sirui Peng, Zhiwang Guo, Haidong Tian, Xiankui Xiong, Xiaoyong Xue, Xiaoyang Zeng:
LsCMM-H: A TCO-Optimized Hybrid CXL Memory Expansion Architecture with Log Structure. 1-7 - Yiyang Zhao, Xuyang Zhao, Zhaori Bi, Ming Zhu, Qiwei Zhan, Keren Zhu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng:
Seeing Through Designs: Attention-Based Knowledge Transfer for Preference-Guided Microarchitecture Search. 1-9 - Rakin Muhammad Shadab, Sanjay Gandham, Mingjie Lin:
FlexTEE: Dynamically Enhancing Metadata Locality Through Affine Address Transformation for Heterogeneous & Secure AI Platforms. 1-9 - Rongchao Dong, Zewei Mo, Yingheng Li, Aditya Pawar, Jun Yang, Youtao Zhang, Xulong Tang:
STMC: Small-Tile Multiple-Copy Compilation for Reliable Measurement-Based Quantum Computing. 1-9 - Hangyu Zhang, Divya Yogi, Ramesh Harjani, Sachin S. Sapatnekar:
Optimal Selection and Placement of Voltage Regulators in 2.5D Heterogeneously Integrated Systems. 1-9 - Chen Chen, Jiaqi Yin, Cunxi Yu:
Revisit Choice Network for Synthesis and Technology Mapping. 1-9 - Ching-Yao Huang, Wai-Kei Mak:
An Efficient Routing Optimization Framework for Silicon-Based Spin-Qubit Devices. 1-9 - Maha Shatta, Konstantinos Balaskas, Paula Carolina Lozano Duarte, Georgios Panagopoulos, Mehdi B. Tahoori, Georgios Zervakis:
Invited Paper: Feature-to-Classifier Co-Design for Mixed-Signal Smart Flexible Wearables for Healthcare at the Extreme Edge. 1-9 - Lidong Guo, Zhenhua Zhu, Qiushi Lin, Yuan Xie, Huazhong Yang, Wangyang Fu, Yu Wang:
How Do Errors Impact NN Accuracy on Non-Ideal Analog PIM? Fast Evaluation via an Error-Injected Robustness Metric. 1-9 - Vairavan Palaniappan, Adam H. Ross, Amit Ranjan Trivedi, Debjit Pal:
Hercules: Hardware accElerator foR stoChastic schedULing in hEterogeneous Systems. 1-9 - Yuxuan Zhao, Feng Gu, Siting Liu, Peiyu Liao, Bei Yu:
H3D: Heterogeneous Resources Aware Global Router for Face-to-Face Bonded 3D ICs. 1-9 - Karthik Somayaji N. S, Peng Li:
AI Analog Circuit Design Agents : On Knowledge Extraction and Transfer with Knowledge Graphs. 1-9 - Sangwoo Seo, Jimin Seo, Yoonho Lee, Donghyeon Kim, Hyejin Shin, Banghyun Sung, Chanyoung Park:
Target Circuit Matching in Large-Scale Netlists Using GNN-Based Region Prediction. 1-9 - Zhiyuan Luo, Le Zhou, Zenghui Zhang, Jie Zhou, Zhien Li, Huiqing You, Feng Yao, Zhenyu Zhao:
ProtoCellLayout: Prototype-Guided Graph Learning for Accurate and Generalizable Standard Cell Layout PPA Estimation. 1-9 - Kang Eun Jeon, Sangheum Yeon, Jinhee Kim, Hyeonsu Bang, Johnny Rhe, Jong Hwan Ko:
Row-Column Hybrid Grouping for Fault-Resilient Multi-Bit Weight Representation on IMC Arrays. 1-9 - Federico Nicolás Peccia, Frederik Haxel, Oliver Bringmann:
Tensor Program Optimization for the RISC-V Vector Extension Using Probabilistic Programs. 1-9 - Mohammad Akyash, Kimia Zamiri Azar, Hadi Mardani Kamali:
DecoRTL: A Run-Time Decoding Framework for RTL Code Generation with LLMs. 1-9 - Joonyoung Seo, Jonghyeon Nam, Howoo Jang, Yoonseok Jung, Seokhyeong Kang:
Enhancing Timing Closure via Spatially Embedded Graph Transformer with Low Power/Area Overhead. 1-9 - Hanwei Fan, Ya Wang, Xiaofeng Zhou, Sicheng Li, Binguang Zhao, Yangdi Lyu, Jiang Xu, Wei Zhang:
Invited Paper: CURE-Fuzz: Curiosity-Driven Reinforcement Learning for Agile Hardware Testing. 1-9 - Weiran Liu, Shixuan Chen, Chun Yang, Xianhua Liu:
Software-Style Hardware Debugging: A Hardware Generation, Simulation and Debugging Framework. 1-9 - Xingyang Li, Jie Jiang, Yu Feng, Yiming Gan, Jieru Zhao, Zihan Liu, Jingwen Leng, Minyi Guo:
SLTarch: Towards Scalable Point-Based Neural Rendering by Taming Workload Imbalance and Memory Irregularity. 1-9 - Yu-Kang Lin, Zhili Xiong, David Z. Pan:
Differentiable Timing-Driven FPGA Placement with Smooth Optimization and ML-Based Delay Calibration. 1-9 - Shadi Matinizadeh, M. Lakshmi Varshika, Anup Das:
Optimizing Memory Latency and Bandwidth of Spiking Neural Network Accelerators on FPGA via Sparse Hashing. 1-9 - Omin Kwon, Kyungjun Oh, Jaeyong Lee, Myungsuk Kim, Jihong Kim:
STAR: Improving Lifetime and Performance of High-Capacity Modern SSDs Using State-Aware Randomizer. 1-9 - Davide Zoni, Andrea Galimberti, Adriano Guarisco:
Rhea: a Framework for Fast Design and Validation of RTL Cache-Coherent Memory Subsystems. 1-9 - Tianxiang Zhu, Qipan Wang, Yibo Lin, Runsheng Wang:
High-Resolution Full-Chip Thermal Resistance Extraction of BEOL Interconnects in 3-D ICs Considering Detailed Via Connectivity. 1-9 - Keyu Peng, Yinuo Wu, Zhengzhe Zheng, Hao Gu, Ziran Zhu, Chao Wang, Jun Yang:
DiSPlace: Diffusion-Sharing-Driven Transistor-Level Placement Beyond Standard-Cell Boundaries for DTCO. 1-9 - Qitao Tan, Sung-En Chang, Rui Xia, Huidong Ji, Chence Yang, Ci Zhang, Jun Liu, Zheng Zhan, Zhenman Fang, Zhuo Zou, Yanzhi Wang, Jin Lu, Geng Yuan:
Perturbation-efficient Zeroth-order Optimization for Hardware-friendly On-device Training. 1-9 - Kaushik Sengupta, Jonathan Zhou, Emir Ali Karahan, Juho Park:
Invited Paper: End-to-end RFIC Topology Synthesis and Design combining Reinforcement learning and Inverse Design. 1-8 - Yuqian Huo, Jinbiao Wei, Christopher Kverne, Mayur Akewar, Janki Bhimani, Tirthak Patel:
Revisiting Noise-adaptive Transpilation in Quantum Computing: How Much Impact Does it Have? 1-9 - Yen-Hsiang Huang, Sung Kyu Lim:
Snake-3D: Differentiable Learning for Cross-Tier Logic Path Snaking Optimization in 3D ICs. 1-9 - Min Gyu Park, Pruek Vanna-Iampikul, Sung Kyu Lim:
Closing the Gap: Advantages of Block-Level over Gate-Level in 3D IC Design for Advanced Nodes. 1-9 - Jaehoon Ahn, Sehyeon Chung, Taewhan Kim:
Adaptive Pin Pattern Modification on Standard Cells Towards ECO Routing. 1-9 - Jindong Tu, Yapeng Li, Peng Xu, Tuo Li, Guoqing Li, Zushuai Xie, Bei Yu, Tinghuan Chen:
RSizing: Robust Bayesian Optimization for Analog Circuit Sizing Under Process Variations. 1-8 - Songchen Ma, Junyi Wu, Yonghao Tan, Pingcheng Dong, Peng Luo, Di Pang, Yu Liu, Xuejiao Liu, Luhong Liang, Kwang-Ting Cheng, Fengbin Tu:
CoXplorer: Multi-Staged Co-Exploration Framework for AI Model Compression and Accelerator Design. 1-9 - Yuntao Lu, Mingjun Wang, Yihan Wen, Boyu Han, Jianan Mu, Huawei Li, Bei Yu:
VIRTUAL: Vector-based Dynamic Power Estimation via Decoupled Multi-Modality Learning. 1-9 - Hsin-Ying Tsai, Chung-Kai Wu, Chih-Cheng Hsu, Jie-Hong R. Jiang:
GradMap: A Gradient-Descent Approach to Simultaneous Technology Mapping, Buffer Insertion, and Gate Sizing. 1-9 - Priyanjana Pal, Alexander Studt, Tara Gheshlaghi, Michael Hefenbrock, Michael Beigl, Mehdi Baradaran Tahoori:
SpikeSynth: Energy-Efficient Adaptive Analog Printed Spiking Neural Networks. 1-9 - Hamed Sajadinia, Zhuo Feng:
HyperEF 2.0: Spectral Hypergraph Coarsening via Krylov Subspace Expansion and Resistance-Based Local Clustering. 1-9 - Hyunsung Yoon, Jehun Lee, Jae-Joon Kim:
Energy-Efficient Accelerator for Scalable Point Transformer Networks with Reduced Data Access. 1-9 - Dekang Zhang, Dan Niu, Yichao Cao, Yichao Dong, Zhenya Zhou, Zhou Jin:
A Geometry-Material Aware Point Cloud Transformer for Large-scale Unstructured Thermal Analysis in 2.5D ICs. 1-9 - Jiaping Tang, Jianan Mu, Zizhen Liu, Ge Yu, Tenghui Hua, Bin Sun, Silin Liu, Jing Ye, Huawei Li:
RIROS: A Parallel RTL Fault SImulation FRamework with TwO-Dimensional Parallelism and Unified Schedule. 1-9 - Haochen Huang, Shuzhang Zhong, Zhe Zhang, Shuangchen Li, Dimin Niu, Hongzhong Zheng, Runsheng Wang, Meng Li:
HD-MoE: Hybrid and Dynamic Parallelism for Mixture-of-Expert LLMs with 3D Near-Memory Processing. 1-9 - Chunyuan Zhao, Jiarui Wang, Xun Jiang, Jincheng Lou, Yibo Lin:
GTA: GPU-Accelerated Track Assignment with Lightweight Lookup Table for Conflict Detection. 1-9 - Seunggeun Kim, Ziyi Wang, Sungyoung Lee, Youngmin Oh, Hanqing Zhu, Doyun Kim, David Z. Pan:
PPAAS: PVT and Pareto Aware Analog Sizing via Goal-conditioned Reinforcement Learning. 1-9 - Yi-Chen Lu, Rongjian Liang, Wen-Hao Liu, Haoxing Ren:
Invited Paper: 2025 ICCAD CAD Contest Problem C: Incremental Placement Optimization Beyond Detailed Placement: Simultaneous Gate Sizing, Buffering, and Cell Relocation. 1-3 - Zhen Wang, Hongquan He, Tao Wu, Xuming He, Qi Sun, Cheng Zhuo, Bei Yu, Jingyi Yu, Hao Geng:
LMLitho: A Large Vision Model-Driven Lithography Simulation Framework. 1-9 - Hamidreza Alikhani, Anil Kanduri, Pasi Liljeberg, Amir M. Rahmani, Nikil D. Dutt:
Invited Paper: Mindful AI for Pervasive Health and Wellbeing (PHW). 1-8 - Yan Tan, Xiangchen Meng, Yangdi Lyu:
COTIA: Concolic Testing with Intelligent Agent. 1-9 - Jing Wang, Shang Liu, Yao Lu, Zhiyao Xie:
HLSDebugger: Identification and Correction of Logic Bugs in HLS Code with LLM Solutions. 1-9 - Yi Ren, Baokang Peng, Chenhao Xue, Kairong Guo, Yukun Wang, Guoyao Cheng, Yibo Lin, Lining Zhang, Guangyu Sun:
Orthrus: Dual-Loop Automated Framework for System-Technology Co-Optimization. 1-9 - Jörg Henkel, Mehdi B. Tahoori, Heba Khdr, Hassan Nassar, Vincent Meyers, Deming Chen, Selin Yildirim, Yingbing Huang, Nirmal R. Saxena, Saurabh Hukerikar, Srivi Dhruvanarayan:
Invited Paper: Hardware-Software Co-Design for Highly Optimized, Customized, and Reliable AI Systems. 1-9 - Seungil Lee, Juntae Park, Kwanghyun Koo, Gilha Lee, Sangbeom Jeong, Junoh Park, Hyun Kim:
TETRIS: On-Device Trainable Energy-Efficient FPGA Accelerator for Trustworthy and Real-Time Instance Segmentation. 1-9 - Lin Chen, Yuxuan Li, Hu Ding:
Achieving Simultaneous Buffering and Steiner Tree Synthesis via Harmonic Based Reinforcement Learning. 1-9 - Yunkun Liao, Jingya Wu, Wenyan Lu, Hang Lu, Xiaowei Li, Guihai Yan:
SNO: Securing Network Function Offloading on FPGA-based SmartNICs in Untrusted Clouds. 1-9 - Qiang Zheng, Yongzhen Xu, Jiaxi Zhang, Zhaofeng Su, Shenggen Zheng:
CNOT Oriented Synthesis for Small-Scale Boolean Functions Using Spatial Structures of Parallelotopes. 1-9 - Kejia Shi, Yue Cao, Yuhang Du, Jianli Chen, Jun Yu, Kun Wang:
ToMamba: Towards Token-Efficient Mamba Architecture on FPGA. 1-9 - Shouzhe Zhang, Zhuren Liu, Ruixiao Huang, Hui Zhao:
GenomeDPU: A Cost-Effective In-Memory Data Processing Unit for GPU-based Genome Analysis. 1-9 - Matthew Hofmann, Berk Gokmen, Zhiru Zhang:
EqMap: FPGA LUT Remapping using E-Graphs. 1-9 - Zhenjie Lu, Hang Zhou, Quan Chen:
MF-MOR: Multi-Fidelity Model Order Reduction for Many-Port Linear Systems in Chip Power Modeling. 1-9 - Bo Mai, Jin Wang, Zhen Zhai, Liang Zhang, Yufu Zhang, Longyang Lin:
CIMWise: An IREE-based End-To-End AI Compiler with Auto-Tuning for CIM Processors. 1-8 - Wei W. Xing, Baowen Ou, Yuxuan Zhang, Zhuohua Liu, Yuanqi Hu:
ASTRA: Automatic Sizing of Transistors with Reasoning Agents. 1-9 - Liaoyuan Cheng, Mengchu Li, Zhidan Zheng, Tsun-Ming Tseng, Ulf Schlichtmann:
FAB: Fast and Demand-Aware Bandwidth Allocation Method for Wavelength-Routed Optical Networks-on-Chip. 1-9 - Haoxiong Ren, Yangu He, Kwunhang Wong, Rui Bao, Ning Lin, Zhongrui Wang, Dashan Shang:
When Pipelined In-Memory Accelerators Meet Spiking Direct Feedback Alignment: A Co-Design for Neuromorphic Edge Computing. 1-9 - Yue Zhang, Yunqi Li, Shichang Ye, Bojun Zhang, Jinkai Wang, Zhizhong Zhang, Peng Wang:
CorDBA: Corners Decoupled Bayesian Approach for yield optimization. 1-8 - Kiran Thorat, Hongwu Peng, Yuebo Luo, Xi Xie, Shaoyi Huang, Amit Hasan, Jiahui Zhao, Yingjie Li, Zhijie Shi, Cunxi Yu, Caiwen Ding:
GROOT: Graph Edge Re-growth and Partitioning for the Verification of Large Designs in Logic Synthesis. 1-9 - Philipp Ebner, Maria Emmerich, Eric Safai, Aniruddha Paul, Mathieu Odijk, Joshua Loessberg-Zahl, Robert Wille:
Automatic Design for Modular Microfluidic Routing Blocks. 1-7 - Shanyi Li, Zhen Zhuang, Siyuan Liang, Bei Yu, Tsung-Yi Ho:
MMPack: Multi-Mask Co-Design for Ultra-Large Wafer-Scale Package Integration. 1-9 - Siyuan He, Peiran Yan, Yandong He, Youwei Zhuo, Tianyu Jia:
Tasa: Thermal-aware 3D-Stacked Architecture Design with Bandwidth Sharing for LLM Inference. 1-9 - Yupeng Su, Ziyi Guan, Xiaoqun Liu, Tianlai Jin, Dongkuan Wu, Zhengfei Chen, Graziano Chesi, Ngai Wong, Hao Yu:
LLM-Barber: Block-Aware Rebuilder for Sparsity Mask in One-Shot for Large Language Models. 1-9 - Yu-En Lin, Shao-Yun Fang, Yi-Yu Liu:
Refinement Strategies for Any-Angle Package Routing with I/O Alignment Consideration. 1-8 - Yuqi Jiang, Qian Jin, Xudong Lu, Jinyuan Deng, Hao Geng, Hanming Wu, Qi Sun, Cheng Zhuo:
FabThink: A Wafer Analysis Multimodal LLM via Chain-of-Thought-Driven Retrieval Augmentation. 1-9 - Zong-Ying Cai, Wei-Han Mao, Yao-Wen Chang, Yang Lu, Jerry Bai, Bin-Chyi Tseng:
Semidefinite Programming-Based Decoupling Capacitor Placement for Power Distribution Network Optimization. 1-9 - Xingyue Qian, Chen Nie, Zhezhi He, Weikang Qian:
MASIM: An Energy-Efficient Multi-Array Scheduler for SIMD Logic-in-Memory Architectures. 1-9 - Qiang Xu, Leon Stok, Rolf Drechsler, Xi Wang, Grace Li Zhang, Igor L. Markov:
Revolution or Hype? Seeking the Limits of Large Models in Hardware Design. 1-9 - Hyunsu Chae, Seunggeun Kim, Souradip Poddar, Xiaohan Gao, Sensen Li, David Z. Pan:
Invited Paper: Towards Generative AI for Analog and RF IC Design: From Spec to Layout. 1-9 - Dongho Yoon, Gungyu Lee, Jaewon Chang, Yunjae Lee, Dongjae Lee, Minsoo Rhu:
Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices. 1-9 - Yuhao Ji, Yuntao Lu, Zuodong Zhang, Zizheng Guo, Yibo Lin, Bei Yu:
DiffCCD: Differentiable Concurrent Clock and Data Optimization. 1-9 - Zong-Han Wu, Bo-Ying Huang, Yu-Chen Chen, Yao-Wen Chang:
Parallel Non-Integer Multiple-Cell-Height Node Remapping. 1-9 - Hyoju Seo, Seokhyeon Lee, Yongtae Kim:
QQ: Is 2-bit Enough? Exploiting Quantization to Enhance Computation and Memory Efficiency in Quantum Simulation. 1-9 - Quan Cheng, Huizi Zhang, Chien-Hsing Liang, Mingtao Zhang, Jing-Jia Liou, Jinjun Xiong, Longyang Lin, Masanori Hashimoto:
Tenpura: A General Transient Fault Evaluation and Scope Narrowing Platform for Ultra-fast Reliability Analysis. 1-9 - Sumukh Pinge, Ashkan Moradifirouzabadi, Keming Fan, Prasanna Venkatesan Ravindran, Tanvir H. Pantha, Po-Kai Hsu, Zheyu Li, Weihong Xu, Zihan Xia, Flavio Ponzina, Winston Chern, Taeyoung Song, Priyankka Gundlapudi Ravikumar, Mengkun Tian, Lance Fernandes, Huy Tran, Hari Jayasankar, Hang Chen, Chinsung Park, Amrit Garlapati, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Duygu Kuzum, Shimeng Yu, Sourav Dutta, Asif Khan, Tajana Rosing, Mingu Kang:
FeNOMS: Enhancing Open Modification Spectral Library Search with In-Storage Processing on Ferroelectric NAND (FeNAND) Flash. 1-9 - Zhibai Huang, Kailiang Xu, Zhixiang Wei, Yinghao Deng, Chen Chen, Yun Wang, Fangxin Liu, Mingyuan Xia, Zhengwei Qi:
DevTrace: Lightweight Plug-In Design for PCIe Transaction Tracing in Edge Intelligence Workloads. 1-9 - Md Mizanur Rahaman Nayan, Che-Kai Liu, Zishen Wan, Arijit Raychowdhury, Azad J. Naeemi:
HyDra: SOT-CAM Based Vector Symbolic Macro for Hyperdimensional Computing. 1-9 - Yufan Du, Zizheng Guo, Runsheng Wang, Yibo Lin:
Differentiable Physical Optimization. 1-9 - Ziyao Yang, Jingbo Sun, Vidya A. Chhabria, Yu Cao:
Adaptive Graph Learning for Efficient Thermal Analysis of Multi-Stacking Chiplet Systems under Interface Variations. 1-9 - Zhaoyuan Liu, Haodong Lu, Jianli Chen, Jun Yu, Kun Wang:
A Precision-Steerable Electromigration Solver with Physics-Informed Adaptive Graph Partitioning. 1-9 - Yunxiang Zhang, Sabbir Ahmed, Abeer Matar A. Almalky, Adnan Siraj Rakin, Wenfeng Zhao:
Non-Negative AdderNet: Algorithm-Hardware Co-design for Lightweight Defense of Adversarial Bit-Flip Attacks. 1-8 - Yifan Zhang, Hongji Wang, Genhao Zhang, Jianli Chen, Jun Yu, Kun Wang:
SiST: Token Similarity and Sparsity Aware Optimization for Transformers on FPGA. 1-9 - Seohye Ha, Yunki Han, Taehwan Kim, Jiwan Kim, Junyoung Park, Gunhee Park, Lee-Sup Kim:
SAFF: Scalable Acceleration of GNN-based Machine Learning Force Fields using Tensor-Aware Hardware for Molecular Simulation. 1-9 - Qidie Wu, Jiangyuan Gu, Xuguang Yuan, Shaojun Wei, Shouyi Yin:
P2P-Chiplet: Partition and Placement Co-Optimization for Multi-Chiplet Architecture. 1-9 - Chengpeng Xia, Haibo Zhang, Hao Zhang, Yawen Chen, Amanda Susan Barnard:
BITLUME: Precision-Flexible Photonic Computing for Ultra-Fast and Energy-Efficient DNN Acceleration. 1-9 - Yuan Pu, Zhuolun He, Shutong Lin, Jiajun Qin, Xinyun Zhang, Hairuo Han, Haisheng Zheng, Yuqi Jiang, Cheng Zhuo, Qi Sun, David Z. Pan, Bei Yu:
MM-GRADE: A Multi-Modal EDA Tool Documentation QA Framework Leveraging Retrieval Augmented Generation. 1-9 - Yi-Chen Lu, Hao-Hsiang Hsiao, Haoxing Ren:
Invited Paper: LLM-Enhanced GPU-Optimized Physical Design at Scale. 1-7 - Raghul Saravanan, Sudipta Paria, Aritra Dasgupta, Swarup Bhunia, Sai Manoj P. D.:
PROFUZZ: Directed Graybox Fuzzing via Module Selection and ATPG-Guided Seed Generation. 1-9 - Tengyu Zhang, Chenqi Lin, Jiangrui Yu, Yi Chen, Shuwen Deng, Meng Li:
(Invited) FENIX: Flexible and Efficient Hybrid HE/MPC Acceleration with Near-Memory Processing. 1-9 - Abhairaj Singh, Konstantinos Stavrakakis, Rajendra Bishnoi, Rajiv V. Joshi, Said Hamdioui:
Energy-Efficient Multi-Operand XOR Logic-Based CIM Accelerator using RRAM technology. 1-7 - Jindong Li, Tenglong Li, Ruiqi Chen, Guobin Shen, Dongcheng Zhao, Qian Zhang, Yi Zeng:
Hummingbird: A Smaller and Faster Large Language Model Accelerator on Embedded FPGA. 1-9 - Chenchen Zhao, Zhengyuan Shi, Xiangyu Wen, Chengjie Liu, Yi Liu, Yunhao Zhou, Yuxiang Zhao, Hefei Feng, Yinan Zhu, Gwok-Waa Wan, Xin Cheng, Weiyu Chen, Yongqi Fu, Chujie Chen, Chenhao Xue, Ying Wang, Yibo Lin, Jun Yang, Ning Xu, Xi Wang, Qiang Xu:
MMCircuitEval: A Comprehensive Multimodal Circuit-Focused Benchmark for Evaluating LLMs. 1-9 - Karthik Garimella, Negar Neda, Austin Ebel, Nandan Kumar Jha, Brandon Reagen:
Network and Compiler Optimizations for Efficient Linear Algebra Kernels in Private Transformer Inference (Invited Paper). 1-10 - Yaman Jandali, Ruisi Zhang, Nojan Sheybani, Farinaz Koushanfar:
Invited Paper: Optimizing Privacy-Preserving Primitives to Support LLM-Scale Applications. 1-9 - Linfeng Du, Jiawei Liang, Jason Lau, Yuze Chi, Yutong Xie, Chunyou Su, Afzal Ahmad, Zifan He, Jake Ke, Jinming Ge, Jason Cong, Wei Zhang, Licheng Guo:
Automated Design Space Exploration in High-Level Physical Synthesis. 1-9 - Yue Tao, Shaowei Cai:
VeriSAT: the Hardware Design of Modern SAT Solver. 1-9 - Ziang Zhou, Qi Zhu, Hao Lan, Huifeng Zhu, Wei Yan, Chenglu Jin, Xuejun An, Xiaochun Ye:
CacheGuardian: A Timing Side-Channel Resilient LLC Design. 1-9 - Mashrafi Alam Kajol, Wei Lu, Qiaoyan Yu:
Invited Paper: Security Under the Lens: Vulnerabilities in In-Sensor Computing Systems. 1-7 - Xinyi Guo, Geguang Miao, Shinichi Nishizawa, Hiromitsu Awano, Shinji Kimura, Takashi Sato:
SOME: Symmetric One-Hot Matching Elector - A Lightweight Microsecond Decoder for Quantum Error Correction. 1-9 - Haichuan Liu, Zizheng Guo, Runsheng Wang, Yibo Lin:
IncreGPUSTA: GPU-Accelerated Incremental Static Timing Analysis for Iterative Design Flows. 1-9 - Wenjie Ren, Meng Wu, Mingxuan Li, Peiyu Chen, Tianyu Jia, Le Ye:
CIMTester: An Agile Golden-Result-Free BIST Compiler for Robust Compute-In-Memory. 1-9 - Qimin Yuan, Kai Huang, Xiaowen Jiang, Dongliang Xiong:
Quantitative Cost Model and Cost Optimization Methods for Multi-Technology-Node Architecture. 1-9 - Ye Qiao, Zhiheng Chen, Yian Wang, Yifan Zhang, Yunzhe Deng, Sitao Huang:
COBRA: Algorithm-Architecture Co-optimized Binary Transformer Accelerator for Edge Inference. 1-8 - Tingrui Ren, Bi Wang, Liang Wang, Yuanfu Zhao:
BARQ: Boundary-Aware Regularized Training for Accurate Inference on Computing-in-Memory Accelerators with Low-Precision A/D Conversion. 1-9 - Louis Coulon, Adham Ragab, Jason Anderson, Mirjana Stojilovic, Paolo Ienne:
FRESCO: Efficient Subgraph Enumeration for Scalable Clustering in Heterogeneous CGRAs. 1-9 - Chung-Han Chou, Chih-Jen (Jacky) Hsu, Hung-Chun Chiu, Kai-Chiang Wu, Yu-Guang Chen, Zhuo Li:
Invited Paper: 2025 ICCAD CAD Contest Problem A: Hardware Trojan Detection on Gate-Level Netlist. 1-5 - Yu Chen, Yilun Zhao, Bing Li, He Li, Mengdi Wang, Yinhe Han, Ying Wang:
CLASS: A Controller-Centric Layout Synthesizer for Dynamic Quantum Circuits. 1-9 - Jai-Ming Lin, Hung-Wei Hsu, Tan Huang, Chen-Fa Tsai, De-Shiun Fu, Shih-Cheng Huang:
Efficient Analytical Placement Algorithm with Hybrid Fence Region Constraints Using Non-Newtonian Fluid Model. 1-9 - Brojogopal Sapui, Mehdi B. Tahoori:
Leaks beyond Bits: Deep Learning-Assisted Side-Channel Attacks on Hyperdimensional Computing Accelerators. 1-9 - Junhao Ye, Yuchen Hu, Ke Xu, Dingrong Pan, Qichun Chen, Jie Zhou, Shuai Zhao, Xinwei Fang, Xi Wang, Nan Guan, Zhe Jiang:
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification. 1-9 - Hui Kou, Chenjie Xia, Jialin Yang, Liyi Li, Hao Cai, Xin Si, Bo Liu:
H3D-LLM: Heterogeneous 3D Chiplet Design for LLM Inference with Dynamic Task Scheduling and Memory-Aware Orchestration. 1-9 - Zihan Zhang, Marco Donato:
PIGen: Accelerating ReRAM Co-Design via Generative Physics-Informed Modeling. 1-9 - Georgios Kyriazidis, Aristotelis Tsekouras, John Davis, Vasilis F. Pavlidis, Gage Hills:
VLSI Design and Experimental Demonstration of Photonic Interposers in Thin-Film Lithium Niobate. 1-9 - Xiaomeng Yang, Jian Gao, Yanzhi Wang, Xuan Zhang:
ZeroSim: Zero-Shot Analog Circuit Evaluation with Unified Transformer Embeddings. 1-9 - Junzhuo Zhou, Ziwen Wang, Haoxuan Xia, Yuxin Yan, Chengyu Zhu, Ting-Jung Lin, Wei W. Xing, Lei He:
SetupKit: Efficient Multi-Corner Setup/Hold Time Characterization Using Bias-Enhanced Interpolation and Active Learning. 1-8 - Jiangnan Li, Xianfeng Cao, Kaixiang Zhu, Wenbo Yin, Lingli Wang:
DynVec: An End-to-End Framework for Efficient Vector-Dataflow Execution. 1-9 - Peiyu Liao, Yuxuan Zhao, Siting Liu, Bei Yu:
Ultrafast Density Gradient Accumulation in 3D Analytical Placement with Divergence Theorem. 1-9 - Rohan Juneja, Pranav Dangi, Thilini Kaushalya Bandara, Zhaoying Li, Dhananjaya Wijerathne, Li-Shiuan Peh, Tulika Mitra:
Building an Open CGRA Ecosystem for Agile Innovation. 1-9 - Xuan Wang, Minxuan Zhou, Gabrielle De Micheli, Yujin Nam, Sumukh Pinge, Augusto Vega, Tajana Rosing:
PATHE: A Privacy-Preserving Database Pattern Search Platform with Homomorphic Encryption. 1-9 - Youwei Xiao, Yuyang Zou, Yansong Xu, Yuhao Luo, Yitian Sun, Chenyun Yin, Ruifan Xu, Renze Chen, Yun Liang:
Invited Paper: APS: Open-Source Hardware-Software Co-Design Framework for Agile Processor Specialization. 1-9 - Hyunjin Kim, Sanghyeok Han, Jae-Joon Kim:
LLM-on-the-Palm: Mobile LLM Inference with PIM-Enhanced NAND Flash Memory. 1-9 - Soumi Chatterjee, Debadrita Talapatra, Nimish Mishra, Aritra Hazra, Debdeep Mukhopadhyay:
MIRAGE: Microarchitectural Footprints for Detecting Adversarial Attacks in One-Shot Inference. 1-9 - Shunjie Chang, Youran Wu, Jianli Chen, Jun Yu, Kun Wang:
3D DRC: Design Rule Checking for 3D IC with U-Net-based Non-Manhattan Optimization. 1-9 - Gyumin Kim, Heechun Park:
A Unified Design Flow for Homogeneous and Heterogeneous 3D Integration with Fine-Pitch Hybrid Bonding. 1-9 - Youngbin Kim, Yoojin Lim:
Scalable and Asynchronous Differential Checkpointing for Intermittently Powered Devices. 1-9 - Caio Vieira, Antonio Carlos Schneider Beck:
Hyle: An HLS Framework for Hyperdimensional Computing Accelerators on FPGAs. 1-9 - Xiao Dong, Songyu Sun, Xunzhao Yin, Zhou Jin, Zhiguo Shi, Cheng Zhuo:
Accelerating Electro-Thermal Co-Analysis via Coarse-to-Fine Physics-Informed Neural Networks. 1-9 - Mingfei Yu, Gabrielle De Micheli, Giovanni De Micheli:
Making the Best Switch: Encoding Strategy Management for Efficient TFHE Circuit Evaluation. 1-9 - Mehrdad Morsali, Chengwei Zhou, Deniz Najafi, Sreetama Sarkar, Pietro Mercati, Navid Khoshavi, Peter A. Beerel, Mahdi Nikdast, Gourav Datta, Shaahin Angizi:
Opto-ViT: Architecting a Near-Sensor Region of Interest-Aware Vision Transformer Accelerator with Silicon Photonics. 1-9 - Leilei Jin, Rongliang Fu, Zhen Zhuang, Liang Xiao, Fangzhou Liu, Bei Yu, Tsung-Yi Ho:
ChronoTE: Crosstalk-Aware Timing Estimation for Routing Optimization via Edge-Enhanced GNNs. 1-9 - Wenji Fang, Wang Jing, Yao Lu, Shang Liu, Zhiyao Xie:
GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment. 1-9 - Zefan Lin, Zedong Peng, Mingzhe Gao, Jieru Zhao, Zhe Lin:
HIPPO: A Hierarchy-Preserving and Noise-Tolerant Pre-HLS Power Modeling Framework for FPGA. 1-9 - Weimin Fu, Shijie Li, Kaichen Yang, Xuan Silvia Zhang, Yier Jin, Xiaolong Guo:
Building Reasoning LLMs for Hardware Design Generation via Function-Aligned Differentiated Revision. 1-8 - Yueran Zhao, Kaiqi Li, Ziying Guo, Jialin Zhang:
A Graph-Based Deep Reinforcement Learning Framework for Quantum Circuit Mapping with Look-Ahead Rewards and Biased Exploration. 1-9 - Fang Jiang, Fei Tong, Xiaoyu Cheng, Zhe Zhou, Hongyu Wang, Yuxing Mao:
SpectrePrefetch: Undermining Cache-Centric Secure Speculation with Modern Hardware Prefetchers. 1-9 - Mohsen Ahmadzadeh, Kaichang Chen, Georges G. E. Gielen:
(Invited Paper) AnaFlow: Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing. 1-7 - Shuwen Kan, Yanni Li, Hao Wang, Sara Mouradian, Ying Mao:
Circuit Folding: Scalable and Graph-Based Circuit Cutting via Modular Structure Exploitation. 1-9 - Mark Horton, Haoxuan Shan, James Kiessling, Huanrui Yang, Yiran Chen, Hai Helen Li:
Designing and Training Neural Networks for Analog In-Sensor Deployment: A Hardware-Aware Analysis. 1-7 - Xianglu Wang, Hu Ding:
Towards Multi-Objective Routing: A Novel Coreset-based Transfer Learning Framework. 1-9 - Sheng-Wei Yang, Jhih-Wei Hsu, Yu-Hsuan Cheng, Cindy Chin-Fang Shen:
Invited Paper: 2025 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop. 1-6 - Hengyi Zhu, Wenjie Zhu, Tianshu Hou, Zhigang Ji, Runsheng Wang, Min Tang, Hai-Bao Chen:
Equivalent Lumped Element Model for Electromigration Considering Thermal Effects. 1-9 - Hasan Umut Suluhan, Jiahao Lin, Serhan Gener, Chaitali Chakrabarti, Ümit Y. Ogras, Ali Akoglu:
K-PACT: Kernel Planning for Adaptive Context Switching - A Framework for Clustering, Placement, and Prefetching in Spectrum Sensing. 1-9 - Yinhui Ma, Tomomasa Yamasaki, Zhehui Wang, Tao Luo, Bo Wang:
Coflex: Enhancing HW-NAS with Sparse Gaussian Processes for Efficient and Scalable DNN Accelerator Design. 1-9 - Jingyu Pan, Isaac Jacobson, Zheng Zhao, Tung-Chieh Chen, Guanglei Zhou, Chen-Chia Chang, Vineet Rashingkar, Yiran Chen:
CROP: Circuit Retrieval and Optimization with Parameter Guidance using LLMs. 1-9 - Chung-Kuan Cheng, Andrew B. Kahng, Byeonggon Kang, Seokhyeong Kang, Jakang Lee, Bill Lin:
SO3-Cell: Standard Cell Layout Automation Framework for Simultaneous Optimization of Topology, Placement, and Routing. 1-9 - Jennifer Hasler, Afolabi Ige, Linhao Yang, Pranav O. Mathews:
Invited Paper: Synthesizing Analog & Mixed-Signal Floating-Gate enabled Reconfigurable Fabrics using Analog Standard Cells. 1-7 - Da-Wei Huang, Shao-Yun Fang, Wen-Hao Liu:
(Invited) Generalized GPU-Accelerated Dynamic Programming with Application to Mixed-Cell-Height Detailed Placement. 1-9 - Michal Andrzej Gorywoda, Wanyeong Jung:
TickTockStack: In-Datapath Current Imbalance Elimination Using Clocked Differential Logic in a Voltage Stacked Vector Processor. 1-9 - Jiun-Cheng Tsai, Wei-Min Hsu, Kuei-Lin Wu, Hsuan-Ming Huang, Jen-Hang Yang, Heng-Liang Huang, Yen-Ju Su, Charles H.-P. Wen:
MuSTNet: SAT-based Exact Multi-Stage Transistor Network Synthesis with Placement Awareness. 1-8 - Zhengyuan Shi, Chengyu Ma, Ziyang Zheng, Lingfeng Zhou, Hongyang Pan, Wentao Jiang, Fan Yang, Xiaoyan Yang, Zhufei Chu, Qiang Xu:
DeepCell: Self-Supervised Multiview Fusion for Circuit Representation Learning. 1-9 - Siyuan He, Zhantong Zhu, Yandong He, Tianyu Jia:
LP-Spec: Leveraging LPDDR PIM for Efficient LLM Mobile Speculative Inference with Architecture-Dataflow Co-Optimization. 1-9 - Yannick Stade, Wan-Hsuan Lin, Jason Cong, Robert Wille:
Routing-Aware Placement for Zoned Neutral Atom-based Quantum Computing. 1-9 - Ondrej Vlcek, Vojtech Mrazek:
ApproxGNN: A Pretrained GNN for Parameter Prediction in Design Space Exploration for Approximate Computing. 1-8 - Luca Pezzarossa, Joel August Vest Madsen, Alexander Marc Collignon, Jan Madsen:
Invited Paper: Liquid Computing: Towards Programmable Microfluidics. 1-7 - Yiwei Hu, Fangxin Liu, Zongwu Wang, Yilong Zhao, Tao Yang, Li Jiang, Haibing Guan:
PLAIN: Leveraging High Internal Bandwidth in PIM for Accelerating Large Language Model Inference via Mixed-Precision Quantization. 1-9 - M. Lakshmi Varshika, Jonathan Hollenbach, Nicolas Bohm Agostini, Ankur Limaye, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Anup Das, Mitra Taheri, Antonino Tumeo:
Neuromorphic Architectures for Scientific Computing: a Structural Characterization Case Study. 1-9 - Kangwei Xu, Bing Li, Grace Li Zhang, Ulf Schlichtmann:
HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis. 1-9 - Ke Xia, Sheng Wei:
FPGA-CC: Confidential Containers for Virtualized FPGAs. 1-9 - Jun Li, Yangyijian Liu, Chang-Wei Shi, Mingyang Li, Wu-Jun Li:
Discriminate Weight Approximation for Efficient DSP Packing in LLM Accelerators. 1-9 - Katharina Ceesay-Seitz, Flavien Solt, Alexander Klukas, Kaveh Razavi:
Pathfinder: Constructing Cycle-accurate Taint Graphs for Analyzing Information Flow Traces. 1-9 - Chengjie Liu, Jiajia Li, Yabing Feng, Wenhao Huang, Weiyu Chen, Yuan Du, Jun Yang, Li Du:
DiffCkt: A Diffusion Model-Based Hybrid Neural Network Framework for Automatic Transistor-Level Generation of Analog Circuits. 1-9 - Halil Kükner, Ji-Yung Lin, Sheng Yang, Lynn Verschueren, Jürgen Bömmels, Anita Farokhnejad, Maarten Van De Put, Odysseas Zografos, Naoto Horiguchi, Geert Hellings, Marie Garcia Bardon, Julien Ryckaert:
Half-Height Double-Row CFET Standard Cells for Area Optimized Placement in A7 CMOS Node. 1-8 - Archisman Ghosh, Swaroop Ghosh:
Invited Paper: Toward Secure In-Sensor Intelligence: Threats and Defenses in SNNs. 1-7 - Youngmin Oh, Jinje Park, Taejin Paik, Seunggeun Kim, Suwan Kim, Yoon Hyeok Lee, David Z. Pan:
M3: Mamba-assisted Multi-Circuit Optimization via Model-based RL with Effective Scheduling. 1-8 - Robert S. Aviles, Rassul Bairamkulov, Ziyu Liu, Peter A. Beerel:
Optimizing SFQ Circuit Design: A Timing-Driven Framework for Performance-Constrained Area Minimization. 1-9 - Gaurav Kothari, Kanad Ghose:
Addressing Thermal Throttling in HBM. 1-9 - Jeng-De Chang, Zhidan Zheng, Liaoyuan Cheng, Liu-Xuan-Wei Zhang, Tsun-Ming Tseng, Ing-Chao Lin, Ulf Schlichtmann:
WROXIM: A Network-Level Simulation Platform for Wavelength-Routed Optical Networks-on-Chip. 1-9 - Anubha Sehgal, Sandeep Soni, Sumit Diware, Alok Kumar Shukla, Sourajeet Roy, Rajendra Bishnoi:
Continuous On-Chip Learning in Neural Networks using SOT-MRAM based CIM Architectures. 1-8 - Priyanjana Pal, Brojogopal Sapui, Mehdi B. Tahoori:
Invited Paper: Side Channel Vulnerability Analysis of Flexible Neuromorphic Circuits. 1-7 - Tairali Assylbekov, Minsang Yu, Jaewoo Park, Mingon Kim, Seungsu Kim, Jongeun Lee:
SPIMA: Scalable and Cost-Efficient Sparse Matrix Multiplication via Processing in DRAM Array. 1-8 - Jiawen Cheng, Yibin Zhang, Wenjian Yu:
SubtreeLU: High-Performance Parallel Sparse LU Factorization for Circuit Simulation. 1-8 - Zain Taufique, Aman Vyas, Antonio Miele, Pasi Liljeberg, Anil Kanduri:
Twill: Scheduling Compound AI Systems on Heterogeneous Mobile Edge Platforms. 1-9 - Xuan Shen, Peiyan Dong, Zhenglun Kong, Yifan Gong, Changdi Yang, Zhaoyang Han, Yanyue Xie, Lei Lu, Cheng Lyu, Chao Wu, Yanzhi Wang, Pu Zhao:
Squat: Quant Small Language Models on the Edge. 1-9 - Linye Wei, Jiajun Tang, Fan Fei, Boxin Shi, Runsheng Wang, Meng Li:
No Redundancy, No Stall: Lightweight Streaming 3D Gaussian Splatting for Real-time Rendering. 1-9 - Hyunjun Lee, Joon-Sung Yang:
Self-Error Detection and Correction Techniques for Reliable and Efficient Selector-Only Memory. 1-9 - Arunava Chaudhuri, Shubhi Shukla, Sarani Bhattacharya, Debdeep Mukhopadhyay:
"Energon": Unveiling Transformers from GPU Power and Thermal Side-Channels. 1-9 - Michele Fiorito, Serena Curzel, Fabrizio Ferrandi:
Augmented Co-Simulation for Fast Functional and System-Level Verification of HLS Accelerators. 1-9 - Simone Machetti, Deniz Kasap, Juan Sapriza, Rubén Rodríguez Álvarez, Hossein Taji, José Miranda, Miguel Peón-Quirós, David Atienza:
Invited Paper: FEMU: An Open-Source and Configurable Emulation Framework for Prototyping TinyAI Heterogeneous Systems. 1-8 - Jaeheon Kwak, Sangeun Oh, Jinkyu Lee, Insik Shin:
EarDVFS: Environment-Adaptable RL-based DVFS for Mobile Devices. 1-9 - Ziyi Wang, Fangzhou Liu, Tsung-Yi Ho, David Z. Pan, Bei Yu:
NUA-Timer: Pre-Synthesis Timing Prediction Under Non-Uniform Input Arrival Times. 1-9 - Ran Ran, Zhaoting Gong, Zhaowei Li, Wujie Wen:
Invited Paper: Pushing SIMD Efficiency in Homomorphic Encryption for Machine Learning via Pattern-Aware Ciphertext Encoding. 1-9 - Vishesh Mishra, Marcello Traiola, Angeliki Kritikakou, Olivier Sentieys, Urbi Chatterjee:
SERA-Float: A Soft Error Resilient Approximate Floating-Point Computing Format. 1-9 - Boxun Xu, Junyoung Hwang, Pruek Vanna-Iampikul, Yuxuan Yin, Sung Kyu Lim, Peng Li:
3D Acceleration for Mixture-of-Experts and Multi-Head Attention Spiking Transformers with Dynamic Head Pruning. 1-9 - Rongliang Fu, Minglei Zhou, Huilong Jiang, Junying Huang, Xiaochun Ye, Tsung-Yi Ho:
J2Place: A Multiphase Clocking-Oriented Length-Matching Placement for Rapid Single-Flux-Quantum Circuits. 1-8 - Yimin Wang, Yue Jiet Chong, Xuanyao Fong:
LEAP: LLM Inference on Scalable PIM-NoC Architecture with Balanced Dataflow and Fine-Grained Parallelism. 1-9 - Ismael Youssef, Hang Yang, Cong Hao:
LaZagna: An Open-Source Framework for Flexible 3D FPGA Architectural Exploration. 1-9 - Taejin Paik, Jaemin Park, Taehee Kim, Daniel Hyunsuk Jung, Doyun Kim:
PCBFormer: Understanding 3D Structure of RealWorld PCB Traces for S-Parameter Prediction. 1-8 - Zhongzhi Yu, Chaojian Li, Yongan Zhang, Mingjie Liu, Nathaniel Ross Pinckney, Wenfei Zhou, Rongjian Liang, Haoyu Yang, Haoxing Ren, Yingyan Celine Lin:
LLM4Verilog: Building Large-Scale, High-Quality Data Infrastructure for Verilog Code Generation via Community Efforts. 1-9 - Yuchao Wu, Xiaofei Yu, Xianyi Feng, Yeyu Tong, Yuzhe Ma:
Constraints-aware Adaptive Routing with Hybrid Waveguides for Photonic Integrated Circuits. 1-8 - Evgenii Rezunov, Niko Zurstraßen, Lennart M. Reimann, Rainer Leupers:
Automatic Microarchitecture-Aware Custom Instruction Design for RISC-V Processors. 1-9 - Liangchen Li, Jianxin Wu, Changyu Li, Liang Zhang, Anyang Yu, Junda Zhao, Zhaohao Wang, Chengyuan Sun, Kaihua Cao, Hongxi Liu, Wang Kang, He Zhang, Weisheng Zhao:
An Adaptive Sparse Matrix Compression CIM Accelerator based on 256Kb SOT-MRAM for Downlink Massive MIMO Communications. 1-9 - Moritz Brunion, Navaneeth Kunhi Purayil, Francesco Dell'Atti, Sebastian Lam, Refik Bilgic, Mehdi B. Tahoori, Luca Benini, Julien Ryckaert:
Invited Paper: CMOS 2.0 - Redefining the Future of Scaling. 1-8 - Yuan Meng, Yuyan Wang, Zhixuan Dong, Yonghan Luo, Changhao Yan, Keren Zhu, Zhaori Bi, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
NSTherm: An Error-Bounded Network-Stochastic Fusion Thermal Simulator for Geometry-Adaptable Chiplets via Diffeomorphic Mapping and Neural-Guided Variance Reduction. 1-9 - Shidong Shen, Jinyu Liu, Weizhi Feng, Fu Song, Zhilin Wu:
BMCFuzz: Hybrid Verification of Processors by Synergistic Integration of Bound Model Checking and Fuzzing. 1-9 - Vidya A. Chhabria, Amur Ghose, Vikram Gopalakrishnan, Andrew B. Kahng, Sayak Kundu, Yiting Liu, Zhiang Wang, Bing-Yue Wu:
Invited: IEEE DATC RDF-2025: Enabling an EDA Research Ecosystem. 1-9 - Pinfeng Jiang, Letian Wang, Yilong Fang, Yi Wang, Mingde Zhu, Xiangshui Miao, Xingsheng Wang:
SPARTA: Spike-Aware Token Skipping Co-Optimization with Heterogeneous ReRAM-CIM Architecture for Spiking Transformer Acceleration. 1-9 - Nojan Sheybani, Tengkai Gong, Anees Ahmed, Nges Brian Njungle, Michel A. Kinsy, Farinaz Koushanfar:
Gotta Hash 'Em All! Accelerating Hash Functions for Zero-Knowledge Proof Applications. 1-9 - Zeyu Li, Shangkun Li, Chuyi Dai, Chaofang Ma, Jiawei Liang, Xin Li, Wei Zhanh:
Robin: RWKV Accelerator using Block Circulant Matrices based on FPGA. 1-9 - Chung-Kuan Cheng, Shao-Yun Fang, Yi-Yu Liu, Tsun-Ming Tseng:
(Invited Paper) Overview of 2025 CAD Contest at ICCAD. 1-4 - Hao-Hsiang Hsiao, Yi-Chen Lu, Sung Kyu Lim, Haoxing Ren:
BUFFALO: PPA-Configurable, LLM-based Buffer Tree Generation via Group Relative Policy Optimization. 1-9 - Ming-Hsiang Tsai, Ming-Liang Wei, Chia-Chun Chien, Po-Hao Tseng, Yung-Chun Lee, Hsiang-Pang Li, Chia-Lin Yang:
Accelerating Genome Alignment Pipeline with In-NAND Search Technology and Group Testing Techniques. 1-10 - Weilong Guan, Li Huang, Yuxuan Lin, Yuchao Wu, Yeyu Tong, Yuzhe Ma:
ThermoPhoton: Fast 3D Thermal Simulation of Photonic Integrated Circuits via Operator Learning. 1-8 - Darshana Jayasinghe, Yuanhua Zhong, Sri Parameswaran:
JitFilt: Mitigate Jitter-based Side Channel Analysis Attacks. 1-9 - Fu Teng, Miao Pan, Xuhong Zhang, Zhezhi He, Yiyao Yang, Xinyi Chai, Mengnan Qi, Liqiang Lu, Jianwei Yin:
VeriRL: Boosting the LLM-based Verilog Code Generation via Reinforcement Learning. 1-9 - Tishya Sarma Sarkar, Shuvodip Maitra, Abhishek Chakraborty, Sarani Bhattacharya, Debdeep Mukhopadhyay:
TREX-F: TRustability of Electronics using X-ray based Fingerprinting. 1-9 - S. G. Shoaib Ahamed, Mrityunjay Shukla, Khushang Singla, Sayandeep Saha:
Everything Depends on Your Hammer: A Systematic Rowhammer Attack Exploration on SPHINCS+. 1-9 - Jinwei Tang, Jiayin Qin, Nuo Xu, Pragnya Sudershan Nalla, Yu Cao, Yang Katie Zhao, Caiwen Ding:
MAHL: Multi-Agent LLM-Guided Hierarchical Chiplet Design with Adaptive Debugging. 1-9 - Yuan Pu, Yuhao Ji, Siying Yu, Zuodong Zhang, Zizheng Guo, Zhuolun He, Yibo Lin, David Z. Pan, Bei Yu:
GPU Acceleration for Versatile Buffer Insertion. 1-9 - Zhixuan Dong, Yonghan Luo, Yuan Meng, Changhao Yan, Zhaori Bi, Keren Zhu, Sheng-Guo Wang, Dian Zhou, Xuan Zeng:
LCTMwalk: GPU-Accelerated Transient Thermal Simulation for Liquid-Cooled 2.5D/3D ICs via Random Walks on Circuit Networks of Modified Compact Thermal Models. 1-9 - Zhixiong Zhao, Haomin Li, Fangxin Liu, Yuncheng Lu, Zongwu Wang, Tao Yang, Li Jiang, Haibing Guan:
QUARK: Quantization-Enabled Circuit Sharing for Transformer Acceleration by Exploiting Common Patterns in Nonlinear Operations. 1-9 - Omar Al Kailani, Yunxiang Zhang, Wenfeng Zhao:
JSA-CIM: A Joint-Sparse AdderNet Compute-In-Memory Accelerator for Energy-Efficient Edge AI Applications. 1-8 - Laurens Spoelstra, Marlize Kramer, Jasper Rietveld, Josh T. Loessberg-Zahl, Loes Segerink:
Invited paper - Connecting the D.O.T.S.: Design of fluidic circuit boards for multi-OoC platforms using CAD Tools for Standardization. 1-7 - Suraag Sunil Tellakula, Ching-Yi Chang, Matthew Nigh, Christos Vasileiou, John M. Carulli, Yiorgos Makris:
Unveiling the Mask: Trusted Semiconductor Manufacturing through Wafer-Level Mask-Set Attestation. 1-9 - Jing Kou, Guangyao Wang, Saiya Wang, Yuexi Lv, Liang Zhang, Chenglin Yu, Xinghao Cui, Yulong Liu, Wei. W. Xing, Wang Kang:
Towards Accurate Characterization of In-Memory Computing Non-Idealities: A Physics & Data Co-Driven Generative Framework. 1-9 - Jiaqi Yin, Zhan Song, Chen Chen, Yaohui Cai, Zhiru Zhang, Cunxi Yu:
e-boost: Boosted E-Graph Extraction with Adaptive Heuristics and Exact Solving. 1-9 - Yihang Yuan, Ali Aghdaei, Zhuo Feng:
dyGRASS: Dynamic Spectral Graph Sparsification via Localized Random Walks on GPUs. 1-9 - Guanglei Zhou, Chen-Chia Chang, Junyao Zhang, Jingyu Pan, Yiran Chen:
Diffusion-Model-Enhanced Layout Pattern Generation for Sub-3nm DFM. 1-7 - Haikang Diao, Chuyue Tang, Bocheng Xu, Haoyang Luo, Meng Li, Yuan Wang, Xiyuan Tang:
Adder-DCIM: A Parallel Bit-Flexible Digital CIM Accelerator Joint Model Compression Framework for AdderNet Inference. 1-9 - Georgios Mentzos, Valentin Alexander Frey, Konstantinos Balaskas, Georgios Zervakis, Jörg Henkel:
R2T-Tiny: Runtime-Reconfigurable Throughput-Optimized TinyML for Hybrid Inference Acceleration on FPGA SoCs. 1-9 - Yutao Sun, Jiehua Huang, Xiangping Liao, Zhijun Wang, Liping Liang:
ISO 26262-Aligned Functional Safety Verification Framework with Explainable Graph Neural Network. 1-9 - Shao-Yu Lo, Che-Ming Chang, Yao-Wen Chang:
Advanced Packaging Warpage Modeling with DeepONet-Based Operator Learning. 1-9 - Xingyu Xu, Yuan Song, Bo Hu, Peng Zheng, Zihan Zou, Xin Si, Bo Liu:
SparCIM: A Heterogeneous CIM-Based Accelerator for Large Language Models with Contextual and Unstructured Bit Sparsity. 1-9 - Robert Bao, Zongrui Cai, Shuangliang Chen, Ajay Joshi, Darius Bunandar, Rakesh Kumar:
Waferscale Silicon Photonics Systems: A Cost-Benefit Analysis and Optimization. 1-9 - Tim Kogel, Holger Keding:
AI-Driven Multi-Die Architecture Exploration. 1-4 - Minsung Kim, Jihoon Lee, Seongjin Chou, Whisoo Chung, Inwoo Kim, Woosung Kang, Hyosu Kim, Sangeun Oh, Hoon Sung Chwa, Kilho Lee:
Mitigating Resource Contention for Responsive On-device Machine Learning Inferences. 1-9 - Zhenxuan Xie, Lixin Liu, Tianji Liu, Evangeline F. Y. Young:
ExactMap: Enhancing Delay Optimization in Parallel ASIC Technology Mapping. 1-9 - Mikolaj Walczak, Uttej Kallakuri, Edward Humes, Xiaomin Lin, Tinoosh Mohsenin:
Invited Paper: BitMedViT: Ternary-Quantized Vision Transformer for Medical AI Assistants on the Edge. 1-7 - Yen-Ju Su, Jiun-Cheng Tsai, Hsuan-Ming Huang, Aaron C.-W. Liang, Han-Ya Tsai, Wei-Min Hsu, Jen-Hang Yang, Charles H.-P. Wen:
CoP&R: Co-Optimizing Place-and-Route for Standard Cell Layout via MCTS and AllSAT. 1-9 - Zhuohua Liu, Weilun Xie, Yuxuan Zhang, Chen Wang, Yuanqi Hu, Wei W. Xing:
DIVE: Dynamic Information-Guided Variable Expansion for Deeper Analog Circuit Optimization. 1-9 - Liuke Wang, Shenshuo Yao, Shihan Wang, Zhen Wang, Zicheng Huang, Jingyi Yu, Hao Geng:
When Semi-Supervised LVM Meets Frequency-Based Critical Layout Pattern Selection. 1-9 - Shangshang Yao, Kunlong Li, Li Shen:
ILP-Driven FPGA Multiplier Synthesis: A Scalable Framework for Area-Latency Co-Optimization. 1-9 - Andreia Podasca, Anup Das:
Invited Paper: Analyzing the Robustness of Neuromorphic Computing in the Presence of Variability in Non-Volatile Memory. 1-8 - Yipei Xu, Zhisheng Zeng, Qing He:
A Complete Modeling Methodology for Full-chip Parasitic Extraction. 1-9 - Bolun Li, Chen Dong, Decheng Qiu, Mingzhi Chen, Yang Yang:
Defense in the Reverse Fragment: RL-Based Partial Netlist Hardware Trojan Detection. 1-7 - Haodong Lu, Da Tang, Xiqiong Bai, Zexu Zhang, Tianyi Zhou, Xinran Li, Kun Wang:
LUT-HD: Accelerating Hyperdimensional Computing Inference via Efficient Table Lookup. 1-9 - Chen-Han Lu, Wen-Hao Liu, Haoxing Ren, Ting-Chi Wang:
Leveraging GPU for Better Detailed Placement Quality. 1-9 - Donger Luo, Tianyi Li, Xinheng Li, Qi Sun, Cheng Zhuo, Bei Yu, Jingyi Yu, Hao Geng:
LLM-Augmented Multi-Modal Fusion for SoC Design Space Exploration. 1-8 - Batuhan Sesli, Muhammad Sabih, Frank Hannig, Jürgen Teich:
Design of Machine Learning Accelerators as RISC-V Extensions using an Open Source Tool Flow. 1-9 - Seung-Eon Hwang, Hyeon Gwon Kim, Dongwoo Lew, Jongsun Park:
SiGNoR: Similarity-based Graph Partitioning and Node Reuse for Memory Efficient GNN Acceleration. 1-9 - Mengyuan Yin, Benjamin Chen Ming Choong, Chuping Qu, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo:
Optimizing Neural Networks with Learnable Non-Linear Activation Functions via Lookup-Based FPGA Acceleration. 1-9 - Shikai Wang, Qiufeng Li, Houbo He, Jian Gao, Zining Wang, Yu Sun, Xuan Zhang, Taiyun Chi, Weidong Cao:
Invited Paper: Multi-Agent Generative Synthesis for Analog/RF Circuit: from Scalable Topology Generation to Efficient Inverse Design. 1-9 - Linfeng Zhong, Songqiang Xu, Huifeng Wen, Tong Xie, Qingyu Guo, Yuan Wang, Meng Li:
SpecMamba: Accelerating Mamba Inference on FPGA with Speculative Decoding. 1-9 - Siqing Fu, Lizhou Wu, Tiejun Li, Chunyuan Zhang, Sheng Ma, Jianmin Zhang, Yuhan Tang, Jixuan Tang:
NeuroPDE: A Neuromorphic PDE Solver Based on Spintronic and Ferroelectric Devices. 1-9 - Chen Bai, Xin Fan, Zhenhua Zhu, Wei Zhang, Yuan Xie:
AccelStack: A Cost-Driven Analysis of 3D-Stacked LLM Accelerators. 1-9 - Zizhuo Fu, Xiaotian Guo, Wenxuan Zeng, Shuzhang Zhong, Yadong Zhang, Peiyu Chen, Runsheng Wang, Le Ye, Meng Li:
H2EAL: Hybrid-Bonding Architecture with Hybrid Sparse Attention for Efficient Long-Context LLM Inference. 1-9 - Kimia Tasnia, Alexander Garcia, Tasnuva Farheen, Sazadur Rahman:
VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi-Role LLMs. 1-9 - Shao-Hsiang Chen, Zeng-Wei Chen, Po-Jen Lin, Hung-Jen Hsu, Hsin-Ying Lin, Yung-Hsiang Chuang, Huang-Yu Chen, Jim Chang, Yao-Wen Chang:
Performance-Driven Pre-Assignment Routing for High-Speed Package Designs. 1-9 - Shidi Tang, Pengwei Zheng, Ruiqi Chen, Yuxuan Lv, Bruno da Silva, Ming Ling:
Diff-DiT: Temporal Differential Accelerator for Low-bit Diffusion Transformers on FPGA. 1-9 - Hung-Yuna Chen, Chun-Feng Wu, Yuna-Hao Chang, David Hung-Chang Du:
GAIA: Glass-Aware I/O Middleware. 1-9 - Jiahao Cai, Ann Franchesca Laguna, Zeyu Yang, Yuxiao Yang, Thomas Kämpfe, Zheyu Yan, Cheng Zhuo, Xunzhao Yin:
FACAM: Design and Optimization of A Compact Energy Efficient FeFET-Based Analog Content Addressable Memory. 1-9 - Gauthaman Murali, Mudit Bhargava, Shairfe Salahuddin, Zhichao Chen, Archana Pandey, Srivatsa Rangachar Srinivasa, Prerna Budhkar, Ragh Kuttappa, Vinayak Honkote, Prashanth Sakthi, Myung-Hee Na, Tanay Karnik:
Invited Paper: System and Technology Co-Optimization Framework for a Disaggregated System with Passive Die 2.5D Integration. 1-7 - Ruiyang Qin, Dancheng Liu, Gelei Xu, Amir Nassereldine, Zheyu Yan, Chenhui Xu, Yuting Hu, X. Sharon Hu, Jinjun Xiong, Yiyu Shi:
Tiny-Align: Bridging Automatic Speech Recognition and Large Language Model on Edge. 1-9 - Yayue Hou, Zhenyu Liu, Garrett Gagnon, Hsinyu Tsai, Kaoutar El Maghraoui, Geoffrey W. Burr, Liu Liu:
SAGE: Saliency-Aware Grouping for Efficient Mapping of LLMs on Analog Compute-in-Memory. 1-9 - Haiyang Liu, Xueyan Wang, Jianlei Yang, Xiaotao Jia, Gang Qu, Weisheng Zhao:
Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-Optimization. 1-9 - Martin Schmid, Giuseppe Manzoni, Aydin Aysu, Elif Bilge Kavun:
The Fellowship of the Leak: Power Analysis of a Masked FrodoKEM Hardware Accelerator. 1-8 - Shu-Yi Tsai, Yu-Guang Chen, Kun-Min Chen, Sheng-Bing Ke, Chung-Hui Hsieh, Chih-Wei Lin, Mango Chia-Tso Chao:
COPA: A Congestion-Oriented Pin Assignment Framework for Intra-Block Physical Design Optimization. 1-9 - Shuo Yin, Jiahao Xu, Jiaxi Jiang, Mingjun Li, Yuzhe Ma, Tsung-Yi Ho, Bei Yu:
G-Contour: GPU Accelerated Contour Tracing For Large-Scale Layouts. 1-9
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