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ORCIDFPT 2019: Tianjin, China
- International Conference on Field-Programmable Technology, FPT 2019, Tianjin, China, December 9-13, 2019. IEEE 2019, ISBN 978-1-7281-2943-3
- Sean Fox, Julian Faraone, David Boland, Kees A. Vissers, Philip H. W. Leong
:
Training Deep Neural Networks in Low-Precision with High Accuracy Using FPGAs. 1-9 - Zeinab Seifoori, Hossein Asadi, Mirjana Stojilovic:
A Machine Learning Approach for Power Gating the FPGA Routing Network. 10-18 - Xinkai Di, Haigang Yang, Zhihong Huang, Ning Mao, Yiping Jia, Yong Zheng:
Exploring Resource-Efficient Acceleration Algorithm for Transposed Convolution of GANs on FPGA. 19-27 - Hongxiang Fan, Gang Wang, Martin Ferianc, Xinyu Niu, Wayne Luk:
Static Block Floating-Point Quantization for Convolutional Neural Networks on FPGA. 28-35 - Julian Oppermann, Lukas Sommer, Lukas Weber, Melanie Reuter-Oppermann, Andreas Koch, Oliver Sinnen:
SkyCastle: A Resource-Aware Multi-Loop Scheduler for High-Level Synthesis. 36-44 - Yiren Zhao, Xitong Gao, Xuan Guo, Junyi Liu, Erwei Wang, Robert D. Mullins, Peter Y. K. Cheung, George A. Constantinides, Cheng-Zhong Xu:
Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs. 45-53 - Matthew B. Ashcraft, Jeffrey Goeders:
Synchronizing On-Chip Software and Hardware Traces for HLS-Accelerated Programs. 54-62 - Susumu Mashimo, Koji Inoue, Ryota Shioya, Akifumi Fujita, Reoma Matsuo, Seiya Akaki, Akifumi Fukuda, Toru Koizumi, Junichiro Kadomoto, Hidetsugu Irie, Masahiro Goshima:
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor. 63-71 - Prajith Ramakrishnan Geethakumari, Vincenzo Gulisano, Pedro Trancoso, Ioannis Sourdis:
Time-SWAD: A Dataflow Engine for Time-Based Single Window Stream Aggregation. 72-80 - Takeharu Ikezoe, Takuya Kojima, Hideharu Amano:
A Coarse-Grained Reconfigurable Architecture with a Fault Tolerant Non-Volatile Configurable Memory. 81-89 - Ameer M. S. Abdelhadi, Christos-Savvas Bouganis, George A. Constantinides:
Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization. 90-98 - Paolo Gorlani, Tobias Kenter, Christian Plessl:
OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs. 99-107 - Vipula Sateesh, Connor Mckeon, Jared Winograd, André DeHon:
Pipelined Parallel Finite Automata Evaluation. 108-116 - Gongjin Sun, Sang-Woo Jun:
ZFP-V: Hardware-Optimized Lossy Floating Point Compression. 117-125 - Shanquan Tian, Wen Wang, Jakub Szefer:
Merge-Exchange Sort Based Discrete Gaussian Sampler with Fixed Memory Access Pattern. 126-134 - Daniel Holanda Noronha, Ruizhe Zhao, Zhiqiang Que, Jeffrey Goeders, Wayne Luk, Steven J. E. Wilton:
An Overlay for Rapid FPGA Debug of Machine Learning Applications. 135-143 - Long Chung Chan, Gurshaant Malik, Nachiket Kapre:
Partitioning FPGA-Optimized Systolic Arrays for Fun and Profit. 144-152 - Yuanlong Xiao, Dongjoon Park, Andrew Butt, Hans Giesen, Zhaoyang Han, Rui Ding, Nevo Magnezi, Raphael Rubin, André DeHon:
Reducing FPGA Compile Time with Separate Compilation for FPGA Building Blocks. 153-161 - Jessica Vandebon, José Gabriel F. Coutinho, Wayne Luk, Eriko Nurvitadhi, Mishali Naik:
Enhanced Heterogeneous Cloud: Transparent Acceleration and Elasticity. 162-170 - Pongstorn Maidee, Chris Neely, Alireza Kaviani, Chris Lavin:
An Open-Source Lightweight Timing Model for RapidWright. 171-178 - Kristiyan Manev, Anuj Vaishnav, Dirk Koch:
Unexpected Diversity: Quantitative Memory Analysis for Zynq UltraScale+ Systems. 179-187 - Gabor Csordas, Mikhail Asiatici, Paolo Ienne:
In Search of Lost Bandwidth: Extensive Reordering of DRAM Accesses on FPGA. 188-196 - Lana Josipovic, Atri Bhattacharyya, Andrea Guerrieri, Paolo Ienne:
Shrink It or Shed It! Minimize the Use of LSQs in Dataflow Designs. 197-205 - Viet Ba Dang, Farnoud Farahmand, Michal Andrzejczak, Kris Gaj:
Implementing and Benchmarking Three Lattice-Based Post-Quantum Cryptography Algorithms Using Software/Hardware Codesign. 206-214 - Mingjun Jiao, Yue Li, Pengbo Dang, Wei Cao, Lingli Wang:
A High Performance FPGA-Based Accelerator Design for End-to-End Speaker Recognition System. 215-223 - Jinyu Xie, Yunhui Qiu, Wenbo Yin, Lingli Wang:
High-Throughput and Low-Latency Distributed Management Proxy for Key-Value Store Over 100Gbps Ethernet on FPGA. 224-230 - Jingwei Hu, Wen Wang, Ray C. C. Cheung, Huaxiong Wang:
Optimized Polynomial Multiplier Over Commutative Rings on FPGAs: A Case Study on BIKE. 231-234 - Anrong Yang, Yuanhui Li, Hongqiao Shu, Jianlin Deng, Chuanzhao Ma, Zheng Li, Qigang Wang:
An OpenCL-Based FPGA Accelerator for Compressed YOLOv2. 235-238 - El Mehdi Benhani, Cuauhtemoc Mancillas López, Lilian Bossuet:
Secure Internal Communication of a Trustzone-Enabled Heterogeneous Soc Lightweight Encryption. 239-242 - Anh Hoang Ngoc Nguyen, Masashi Aono, Yuko Hara-Azumi:
Amoeba-Inspired Hardware SAT Solver with Effective Feedback Control. 243-246 - Xifan Tang, Edouard Giacomin, Aurélien Alacchi, Pierre-Emmanuel Gaillardon:
A Study on Switch Block Patterns for Tileable FPGA Routing Architectures. 247-250 - Lukas Weber, Lukas Sommer, Julian Oppermann, Alejandro Molina, Kristian Kersting, Andreas Koch:
Resource-Efficient Logarithmic Number Scale Arithmetic for SPN Inference on FPGAs. 251-254 - Di Wu, Wei Cao, Lingli Wang:
SpWMM: A High-Performance Sparse-Winograd Matrix-Matrix Multiplication Accelerator for CNNs. 255-258 - Alex R. Bucknall, Shanker Shreejith, Suhaib A. Fahmy:
Network Enabled Partial Reconfiguration for Distributed FPGA Edge Acceleration. 259-262 - Shirui Zhao, Fengwei An, Hao Yu:
A 307-fps 351.7-GOPs/W Deep Learning FPGA Accelerator for Real-Time Scene Text Recognition. 263-266 - Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara:
A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA. 267-270 - Yong Zheng, Haigang Yang, Zhihong Huang, Tianli Li, Yiping Jia:
A High Energy-Efficiency FPGA-Based LSTM Accelerator Architecture Design by Structured Pruning and Normalized Linear Quantization. 271-274 - Nicholas V. Giamblanco, Jason Helge Anderson:
ASAP: Automatic Sizing and Partitioning for Dynamic Memory Heaps in High-Level Synthesis. 275-278 - Daniele Passaretti, Jan Moritz Joseph, Thilo Pionteck:
Survey on FPGAs in Medical Radiology Applications: Challenges, Architectures and Programming Models. 279-282 - Yunfei Sun, Brian Liu, Xianchao Xu:
An OpenCL-Based Hybrid CNN-RNN Inference Accelerator On FPGA. 283-286 - Linhuai Tang, Gang Cai, Tao Yin, Yong Zheng, Jiamin Chen:
A Resource Consumption and Performance Overhead Optimized Reduction Circuit on FPGAs. 287-290 - Bo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen:
Extending the Lifetime of Coarse-Grained Runtime Reconfigurable FPGAs by Balancing Processing Element Usage. 291-294 - Moucheng Yang, Tao Chen, Xuegong Zhou, Liang Zhao, Yunping Zhu, Lingli Wang:
A Complete CPU-FPGA Architecture for Protein Identification with Tandem Mass Spectrometry. 295-298 - Stephen Tridgell, David Boland, Philip H. W. Leong, Siddhartha:
Real-Time Automatic Modulation Classification. 299-302 - Joel Mandebi Mbongue, Danielle Tchuinkou Kwadjo, Christophe Bobda:
Automatic Generation of Application-Specific FPGA Overlays with RapidWright. 303-306 - Eriko Nurvitadhi, Mishali Naik, Andrew Boutros, Prerna Budhkar, Ali Jafari, Dongup Kwon, David Sheffield, Abirami Prabhakaran, Karthik Gururaj, Pranavi Appana:
Scalable Low-Latency Persistent Neural Machine Translation on CPU Server with Multiple FPGAs. 307-310 - Yu Gong, Bo Liu, Wei Ge, Longxing Shi:
RNA: Reconfigurable LSTM Accelerator with Near Data Approximate Processing. 311-314 - Cheng Liu, Xinyu Chen, Bingsheng He, Xiaofei Liao, Ying Wang, Lei Zhang:
OBFS: OpenCL Based BFS Optimizations on Software Programmable FPGAs. 315-318 - Johanna Rohde, Christian Hochberger:
AutoBoxing: Improving GCC Passes to Optimize HW/SW Multi-Versioning of Kernels for HLS. 319-322 - Kizheppatt Vipin:
ZyNet: Automating Deep Neural Network Implementation on Low-Cost Reconfigurable Edge Computing Platforms. 323-326 - Alexander Montgomerie-Corcoran, Stylianos I. Venieris, Christos-Savvas Bouganis:
Power-Aware FPGA Mapping of Convolutional Neural Networks. 327-330 - Yukui Luo, Xiaolin Xu:
HILL: A Hardware Isolation Framework Against Information Leakage on Multi-Tenant FPGA Long-Wires. 331-334 - Dan Cristian Turicu, Octavian Cret, Lucia Vacariu:
Storage Mirroring for Bare-Metal Malware Analysis on FPGA Devices. 335-338 - Seyedramin Rasoulinezhad, Sean Fox, Hao Zhou, Lingli Wang, David Boland, Philip H. W. Leong:
MajorityNets: BNNs Utilising Approximate Popcount for Improved Efficiency. 339-342 - André Bannwart Perina, Jürgen Becker, Vanderlei Bonato:
Lina: Timing-Constrained High-Level Synthesis Performance Estimator for Fast DSE. 343-346 - Stefan Brennsteiner, Tughrul Arslan, John S. Thompson:
Evaluation of Partially Constant, Fine-Grained, Dynamic Partial Reconfigurable Functions in FPGAs. 347-350 - Ali Asghar, Rick van Loo, Timon Kruiper, Daniel Ziener:
Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining. 351-354 - Lenos Ioannou, Suhaib A. Fahmy:
Lightweight Programmable DSP Block Overlay for Streaming Neural Network Acceleration. 355-358 - Umar Ibrahim Minhas, Roger F. Woods, Georgios Karakonstantis:
Optimisation of System Throughput Exploiting Tasks Heterogeneity on Space Shared FPGAs. 359-362 - Tomohiro Ueno, Takaaki Miyajima, Antoniette Mondigo, Kentaro Sano:
Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster. 363-366 - Ye Tian, Jean-Christophe Prévotet, Fabienne Nouvel:
Efficient OS Hardware Accelerators Preemption Management in FPGA. 367-370 - Duc Tri Nguyen, Viet Ba Dang, Kris Gaj:
A High-Level Synthesis Approach to the Software/Hardware Codesign of NTT-Based Post-Quantum Cryptography Algorithms. 371-374 - Yu Ting Chen, Jin Hee Kim, Kexin Li, Graham Hoyes, Jason Helge Anderson:
High-Level Synthesis Techniques to Generate Deeply Pipelined Circuits for FPGAs with Registered Routing. 375-378 - Zhiqiang Que, Yanyang Liu, Ce Guo, Xinyu Niu, Yongxin Zhu, Wayne Luk:
Real-Time Anomaly Detection for Flight Testing Using AutoEncoder and LSTM. 379-382 - Ameer M. S. Abdelhadi, Lesley Shannon:
Revisiting Deep Learning Parallelism: Fine-Grained Inference Engine Utilizing Online Arithmetic. 383-386 - Keisuke Takano, Tetsuya Oda, Ryo Ozaki, Akira Uejima, Masaki Kohata:
Implementation of Distributed Processing Using a PC-FPGA Hybrid System. 387-390 - Longyu Ma, Chiu-Wing Sham:
SoC-FPGA-Based Implementation of Iris Recognition Enhanced by QC-LDPC Codes. 391-394 - Raúl Valencia, Chiu-Wing Sham, Oliver Sinnen:
Evolved Binary Neural Networks Through Harnessing FPGA Capabilities. 395-398 - Yang Yang, Chao Wang, Lei Gong, Xuehai Zhou:
FPNet: Customized Convolutional Neural Network for FPGA Platforms. 399-402 - Deshya Wijesundera, Kisaru Liyanage, Alok Prakash, Thambipillai Srikanthan, Thilina Perera:
An Iterative Technique for Runtime Efficient Hardware-Software Partitioning. 403-406 - Ryota Yamashita, Daichi Teruya, Hironori Nakajo:
Parallelization of Recursive Function in Ruby-Based High-Level Synthesis. 407-410 - Deshya Wijesundera, Nadeeshan Dissanayake, Alok Prakash, Thambipillai Srikanthan, Damith Anhettigama:
Dependency-Aware Clustering for Variable-Grained Hardware-Software Partitioning. 411-414 - Lahiru Rasnayake, Magnus Själander:
Improving Memory Access Locality for Vectorized Bit-Serial Matrix Multiplication in Reconfigurable Computing. 415-418 - Hyeong-Ju Kang:
Real-Time Object Detection on 640x480 Image With VGG16+SSD. 419-422 - Bizhao Shi, Zhucheng Tang, Guojie Luo, Ming Jiang:
Winograd-Based Real-Time Super-Resolution System on FPGA. 423-426 - Tianze Wu, Weiyi Liu, Yongwei Jin:
An End-to-End Solution to Autonomous Driving Based on Xilinx FPGA. 427-430 - Euan Jones, Keegan Pepper, Aimei Li, Shiyue Li, Yuteng Zhang, Donald Bailey:
Autonomous Driving Developed with an FPGA Design. 431-434 - Shimon Kudaka, Ai Suzuki, Natsumi Yamada, Noriki Oshiro, Taichi Miyagi, Yasunori Osana:
Self-Driving Car Application of a Stream-Oriented Accelerator Framework. 435-436 - Musashi Aoto, Moe Mitsugi, Takumi Momose, Yasutaka Wada:
Towards the Improvement of Training Efficiency and Image Recognition Accuracy for an FPGA Controlled Mini-Car by Offloading Neural Network Training. 437-440 - Akira Kojima, Yuya Osawa:
Design and Implementation of Autonomous Driving Robot Car Using SoC FPGA. 441-444 - Yasuhiro Nitta, Sou Tamura, Hidetoshi Yugen, Hideki Takase:
ZytleBot: FPGA Integrated Development Platform for ROS Based Autonomous Mobile Robot. 445-448 - Hamish Simmonds, Nicholas Carlisle, Xue Li, Fanglin Mu, Donald Bailey:
Autonomous Vehicle Development Using FPGA for Image Processing. 449-452 - Tomonari Tanaka, Itsuki Ikeno, Riku Tsuruoka, Takumi Kuchiba, Wang Liao, Yukio Mitsuyama:
Development of Autonomous Driving System Using Programmable SoCs. 453-456 - Kento Hasegawa, Kazunari Takasaki, Makoto Nishizawa, Ryota Ishikawa, Kazushi Kawamura, Nozomu Togawa:
Implementation of a ROS-Based Autonomous Vehicle on an FPGA Board. 457-460 - Taito Manabe, Naofumi Yoshinaga, Yuta Imamura, Taichi Saikai, Koki Fujita, Masatomo Matsuda, Kotoko Miyata, Tatsuma Mori, Yuichiro Shibata, Hiroki Egawa, Yuichi Kawamata, Tomohiro Kida, Ryouhei Tsugami, Ryohei Kakizaki, Taichi Katayama, Koki Tomonaga, Shota Fukui:
Autonomous Vehicle Driving Using the Stream-Based Real-Time Hardware Line Detector. 461-464 - Kenichi Harada, Kenji Kanazawa, Moritoshi Yasunaga:
FPGA-Based Object Detection for Autonomous Driving System. 465-468 - Yuya Kudo, Atsushi Takada, Yuta Ishida, Tomonori Izumi:
An SoC-FPGA-Based Micro UGV with Localization and Motion Planning. 469-472 - Takeshi Ohkawa, Shotaro Tayama, Hayato Mori, Dohyung Lee, Hayato Amano, Itsuki Hirakawa, Mikiko Sato, Harumi Watanabe:
Design and Development of Networked Multiple FPGA Components for Autonomous Tiny Robot Car. 473-475 - Andrew Yeo, Damon Hill, Anzhen Huang, Xueao Liu, Guanchen Dong, Donald Bailey:
Image Processing and Vehicles - Using FPGA to Reduce Latency of Time Critical Tasks. 476-479
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