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ORCIDIMW 2024: Seoul, Republic of Korea
- IEEE International Memory Workshop, IMW 2024, Seoul, Republic of Korea, May 12-15, 2024. IEEE 2024, ISBN 979-8-3503-0652-1
- Daniel Schön
, Stephan Menzel:
Understanding the Thermal Aspects in Dense RRAM Memory Arrays. 1-4 - Boncheol Ku, Jae-Min Sim, Jae Seok Hur, Jae Kyeong Jeong, Yun-Heub Song, Changhwan Choi:
A Novel 3D Gate-All-Around Vertical FeFET with Back-Gate Structure for Disturbance-Less Program Operation. 1-4 - Po-Hao Tseng, Shao-Yu Fang, Yu-Hsuan Lin, Feng-Ming Lee, Jhe-Yi Liao, Yu-Yu Lin, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
3D-NAND based Filtering Cube with High Resolution 2D Query and Tunable Feature Length for Computational SSD. 1-4 - Jihun Kim, Sangsu Park, Hongju Suh, Youngjae Kwon, Seonghun Lee, Yubin Lee, Kayoung Kim, Eungu Han, Jongil Kim, Kyu Sung Kim, Hyejung Choi, Seungwook Ryu, Su Jin Chae, Seho Lee, Soo Gil Kim, Jaeyun Yi, Seonyong Cha:
Realistic Noise-aware Training as a Component of the Holistic ACiM Development Platform. 1-4 - Hao-Ling Tang, Insoo Jung, Frank CC Chin, Luc Thomas, Xin Meng, Arvind Kumar, Jaesoo Ahn, Zuoming Zhu, Abhishek Dube, Mahendra Pakala:
Demonstration of High-Growth-Rate Epitaxially Grown Si Channel on 3D NAND Test Vehicle with Memory Functionality. 1-4 - Naoko Misawa, Tao Wang, Chihiro Matsui, Ken Takeuchi:
Embedded Transformer Hetero-CiM: SRAM CiM for 4b Read/Write-MAC Self-attention and MLC ReRAM CiM for 6b Read-MAC Linear&FC Layers. 1-4 - Dipjyoti Das, Lance Fernandes, Prasanna Venkatesan Ravindran, Taeyoung Song, Chinsung Park, Nashrah Afroze, Mengkun Tian, Hang Chen, Winston Chem, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Shimeng Yu, Suman Datta, Asif Islam Khan:
Design Framework for Ferroelectric Gate Stack Engineering of Vertical NAND Structures for Efficient TLC and QLC Operation. 1-4 - Olivier Billoint, Simon Martin, J. Laguerre, L. Hosier, Jean Coignus, Catherine Carabasse, François Andrieu, Laurent Grenouillet:
Charge-based Sense Demonstration in 1T-1C HZO FeRAM Arrays to Overcome CBL-induced Bank Size Limitations. 1-4 - Hitomi Tanaka, Hajime Sano, Reika Ichihara, Yuta Aiba, Kazuma Hasegawa, Kana Kudo, Chieko Tokunaga, Yasuhito Yoshimizu, Fumie Kikushima, Tomoya Sanuki:
Overcome the End of Life of 3D Flash Memory by Recovery Annealing, Aiming for Carbon Neutrality in Semiconductor Manufacturing. 1-4 - Alexander Grun, Z. L. Lui, C. W. Cheng, D. Piatek, E. K. Lai, Y. T. Kuo, Wei-Chih Chien, S. Cheng, M. J. BrightSky, H. L. Lung, Huai-Yu Cheng:
AsSeGeS and GeN Heterostructures for Superior OTS Performance. 1-4 - Taras Ravsher, Andrea Fantini, Kruti Trivedi, Nouredine Rassoul, Harold Dekkers, Attilio Belmonte, Jan Van Houdt, Valeri Afanas'ev, Kurt Wostyn, Sebastien Couet, Gouri Sankar Kar:
Novel Cross-Point Architecture utilizing Distributed Diode Selector for Read Margin Amplification. 1-4 - Ryota Katsumata:
Flash memory revolution: journey from 2D to 3D, migrating to modular memory fabrication. 1-4 - Jun Yu, Jiawei Fu, Candong Zhao, Fuwei Zhuge, Qi Chen, Yuhui He, Xiangshui Miao:
High Operation Speed(10ns/100ns) and Low Read Current (sub-1μA) 2D Floating Gate Transistor. 1-4 - Yu Li, Hao Jiang, Jie Yu, Xuanyu Zhao, Xiaodong Wang, Qihan Liu, Yingfen Wei, Qi Liu, Ming Liu:
High-efficient and Comprehensive Modeling of MFIM Ferroelectric Tunnel Junctions for Non-volatile/Volatile Applications. 1-4 - Wei-Chih Chien, C. L. Sung, Robert L. Bruce, C. W. Yeh, Huai-Yu Cheng, Z. L. Liu, E. K. Lai, C. W. Cheng, J. X. Zheng, Alexander Grun, A. Ray, D. Daudelin, H. Y. Ho, Matthew BrightSky, H. L. Lung:
A Novel Program-verify Free and Low Drift Multilevel Operation on Cross-point OTS-PCM for In-Memory Computing Application. 1-4 - Thomas Bauvent, Gaël Pillonnet, Gabriel Molas:
Optimizing RRAM Performance: A Comparative Analysis of Forming Strategies. 1-4 - Yuan He, Chengxiang Ma, Xiangchao Ma, Yilong Huang, Qianze Zheng, Yue Xi, Qiumeng Wei, Jianing Li, Xiaodong He, Yongqin Wu, Weihai Bu, Kai Zheng, Jin Kang, Jianshi Tang, Bin Gao, Dong Wu, He Qian, Huaqiang Wu:
A 3.75Mb Embedded RRAM IP on 40nm High-Voltage CMOS Technology. 1-4 - Bastien Beltrando, Marco A. Villena, Mondol Anik Kumar, Shruba Gangopadhyay, Deepak Kamalanathan, E. Smith, Nasrin Kazem, Ghazal Saheli, Stephen Weeks, Michael Haverty, Muthukumar Kaliappan, Andrea Padovani, S. Krishnan, Jeffrey W. Anthis, Luca Larcher, Milan Pesic:
Self-rectifying non-volatile tunneling synapse: multiscale modeling augmented development. 1-4 - Won-Tae Koo, Jae-Gil Lee, Gunhee Lee, Woocheol Lee, Jungwook Woo, Dong Ik Suh, Joongsik Kim, Hyung Dong Lee, Seho Lee, Jaeyun Yi, Seonyong Cha:
Modeling and Demonstration for Multi-level Weight Conductance in Computational FeFET Memory Cell. 1-4 - Hang-Ting Lue, Wei-Chen Chen, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F2 DRAM Below Equivalent 10nm Node. 1-4 - Youngjae Kwon, Won-Tae Koo, Sangsu Park, Dong Ik Suh, Gunhee Lee, Hyung Dong Lee, Youngbae Ahn, Dohee Kim, Seungwook Ryu, Hoseok Em, Seokjoon Kang, Chang Won Jeong, Junho Cheon, Hyejung Choi, Soo Gil Kim, Seho Lee, Jaeyun Yi, Seonyong Cha:
Improvement of MAC Accuracy using Oxygen Diffusion Barriers in Resistive Synaptic Cell Arrays. 1-4 - Ralf Richter, Stefan Dünkel, Bert Müller, Frank Mauersberger, Sven Wittek, Sven Beyer, Jana Böhme, Uwe Ritter, Violetta Sessi, Zhen Xu, Maximilian Drescher, Jinho Kim, Parviz Ghazavi, Yuri Tkachev, Latt Tee, Zonglin Li, Mandana Tadayoni, Fan Luo, Nhan Do, Serguei Jourba, Catherine Decobert, Gilles Festes, Bruno Villard, Thibaut Pate-Cazal:
Performance and Reliability of Technology Qualified 34 Mb Split-Gate eFLASH Macro in 28 nm HKMG. 1-4 - Fu-Chang Hsu, Richard J. Huang, Re-Peng Tsay, Jui-Hsin Chang, Chia-Haur Chang, I-Wei Huang, Kevin Hsu:
3D X-DRAM: A Novel 3D NAND-like DRAM Cell and TCAD Simulations. 1-4 - Dasom Lee, Tsu-Jae King Liu:
SiGe/Si Heterojunction Drain Transistor for Faster 3D NAND Flash Memory Erase. 1-4 - Yuanbiao Li, Xinyi Tang, Guangwei Xu, Songming Miao, Xiao Chen, Jiachen Li, Di Lu, Shibing Long:
CMOS-Compatible Low-T Processing Methods for HZO-based DRAM capacitors by E-field Cycling. 1-4 - Zhongkui Zhang, Xiaofei Fan, Danrong Xiong, Huiyan Sun, Xiantao Shang, Bowen Man, Cong Zhang, Shuhui Li, Renjie Su, Chengyuan Sun, Jennifer Zhou, Hongxi Liu, Gefei Wang:
Process optimization and cryogenic evaluation of spin-orbit torque magnetic random access memory. 1-4 - Daewon Ha, Y. Lee, S. Yoo, W. Lee, M. H. Cho, K. Yoo, S. M. Lee, S. Lee, M. Terai, T. H. Lee, J. H. Bae, K. J. Moon, C. Sung, M. Hong, D. G. Cho, Kyunghwan Lee, S. W. Park, K. Park, Bong Jin Kuh, S. Hyun, Sujin Ahn, J. H. Song:
Exploring Innovative IGZO-channel based DRAM Cell Architectures and Key Technologies for Sub-10nm Node. 1-4 - Pratik B. Vyas, Ashish Pal, Gregory Costrini, Benjamin Colombeau, Bala Haran, Subi Kengeri, El Mehdi Bazizi:
Gate-All-Around SRAM: Performance Investigation and Optimization Towards Vccmin Scaling. 1-4 - Hiraki Inoue, Takeya Hirose, Toshiki Mizuguchi, Yusuke Komura, Toshihiko Saito, Minato Ito, Kiyotaka Kimura, Tatsuya Onuki, Yoshinori Ando, Hiromi Sawai, Tsutomu Murakawa, Hitoshi Kunitake, Takanori Matsuzaki, Hajime Kimura, Makoto Ikeda, Shunpei Yamazaki:
Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM. 1-4 - Laurent Breuil, R. Izmailov, Mihaela Ioana Popovici, J. Stiers, Antonio Arreghini, S. Ramesh, Geert Van den Bosch, Jan Van Houdt, Maarten Rosmeulen:
Gate Side Injection Operating Mode for 3D NAND Flash Memories. 1-4 - Kwiwook Kim, Myeong-Jae Park:
Present and Future, Challenges of High Bandwith Memory (HBM). 1-4 - Ashonita Chavan, Adharsh Rajagopal, Yixin Yan, Isamu Asano, Devanarayanan Ettisserry, Vassil Antonov, Giorgio Servalli, Alessandro Calderoni, Nirmal Ramaswamy:
Materials Engineering for High Performance Ferroelectric Memory. 1-4 - Gaurav Mehta, Jonathan Abdilla, Raymond Hung, El Mehdi Bazizi, Yong Chang Bum, Djuro Bikajlevic, Liu Jiang, Gregory Costrini:
D2W Hybrid Bonding Challenges for HBM. 1-4 - Tae-Hyeon Kim, Yuan-Chun Luo, Omkar Phadke, James Read, Shimeng Yu:
Engineering nvCap From FEOL to BEOL with Ferroelectric Small-signal Non-destructive Read. 1-4 - W. Kim, Valerio Pica, N. Jossart, Farrukh Yasin, Kurt Wostyn, S. Couet, Sidharth Rao:
A novel test and analysis scheme to elucidate tail bit characteristics in STT-MRAM arrays. 1-4 - Saifei Dai, Songwei Li, Shuangshuang Xu, Fengbin Tian, Junshuai Chai, Jiahui Duan, Wenjuan Xiong, Jinjuan Xiang, Yanrong Wang, Hao Xu, Jing Zhang, Xiaolei Wang, Wenwu Wang:
Role of Nitrogen in Suppressing Interfacial States Generation and Improving Endurance in Ferroelectric Field Effect Transistors. 1-4 - Noboru Shibata, Hironori Uchikawa, Taira Shibuya, Hirofumi Inoue:
Novel Multi-Level Coding and Architecture Enabling Fast Random Access for Flash Memory. 1-4 - Sven Beyer, Dominik Kleimaier, Stefan Dünkel, Halid Mulaosmanovic, Steven Soss, Johannes Müller, Zhouhang Jiang, Kai Ni, Thomas Mikolajick, Haidi Zhou:
Charge trapping challenges of CMOS embedded complementary FeFETs. 1-4 - Wei-Chen Chen, Hang-Ting Lue, Ming-Hung Wu, Yu-Tang Lin, Keh-Chung Wang, Chih-Yuan Lu:
Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. 1-4 - Xi-Wei Lin, Salvatore M. Amoroso, Ko-Hsin Lee, Meng Hsuan Ke, Tue Gunst, Pavel Tikhomirov, Plamen Asenov:
Modeling and Simulation for DRAM and Flash Memory Technology Exploration and Development. 1-4 - Maximilian Lederer, Franz Müller, Raik Hoffmann, Ricardo Olivo, Yannick Raffel, Shouzhuo Yang, Sourav De, Roman Potjan, Oliver Ostien, Abdelrahman Altawil, Ayse Sünbül, David Lehninger, Thomas Kämpfe, Konrad Seidel:
Enhanced reliability and trapping behavior in ferroelectric FETs under cryogenic conditions. 1-4 - S. Rachidi, S. Ramesh, Davide Tierno, G. L. Donadio, A. Pacco, J. W. Maes, Y. Jeong, Antonio Arreghini, Geert Van den Bosch, Maarten Rosmeulen:
Pure-Metal Replacement Gate for Reliable 30 nm Pitch Scaled 3D NAND Flash. 1-4 - Karansingh Thakor, Nikhil Rangarajan, Himanshu Diwakar, Rashmi Saikia, Tarun Samadder, Souvik Mahapatra, Shyam Raghunathan, Yingda Dong:
Comprehensive physics-based modeling of post-cycling long-term data retention in 176L 3-D NAND Flash Memories. 1-4
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