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ORCID30th ISCA 2003: San Diego, California, USA
- Allan Gottlieb, Kai Li:
30th International Symposium on Computer Architecture (ISCA 2003), 9-11 June 2003, San Diego, California, USA. IEEE Computer Society 2003, ISBN 0-7695-1945-8
Thermal and Energy-Aware Microarchitectures
- Kevin Skadron, Mircea R. Stan
, Wei Huang, Sivakumar Velusamy, Karthik Sankaranarayanan, David Tarjan:
Temperature-Aware Microarchitecture. 2-13 - Grigorios Magklis, Michael L. Scott, Greg Semeraro, David H. Albonesi, Steve Dropsho:
Profile-Based Dynamic Voltage and Frequency Scaling for a Multiple Clock Domain Microprocessor. 14-25
Processor Architecture
- Ilhyun Kim, Mikko H. Lipasti:
Half-Price Architecture. 28-38 - Il Park, Babak Falsafi, T. N. Vijaykumar:
Iimplicitly-Multithreaded Processors. 39-50
Subsetting SPEC When Measuring Results: Valid or Manipulative?
- Daniel Citron:
MisSPECulation: Partial and Misleading Use of SPEC CPU2000 in Computer Architecture Conferences. 52-59
Microarchitecture Techniques
- Jessica H. Tseng, Krste Asanovic:
Banked Multiported Register Files for High-Frequency Superscalar Microprocessors. 62-71 - Michael D. Powell, T. N. Vijaykumar:
Pipeline Damping: A Microarchitectural Technique to Reduce Inductive Noise in Supply Voltage. 72-83 - Roland E. Wunderlich, Thomas F. Wenisch, Babak Falsafi, James C. Hoe:
SMARTS: Accelerating Microarchitecture Simulation via Rigorous Statistical Sampling. 84-95
Recovery and Replay
- Mohamed A. Gomaa, Chad Scarbrough, Irith Pomeranz, T. N. Vijaykumar:
Transient-Fault Recovery for Chip Multiprocessors. 98-109 - Milos Prvulovic, Josep Torrellas:
ReEnact: Using Thread-Level Speculation Mechanisms to Debug Data Races in Multithreaded Codes. 110-121 - Min Xu, Rastislav Bodík, Mark D. Hill:
A "Flight Data Recorder" for Enabling Full-System Multiprocessor Deterministic Replay. 122-133
Energy-Saving Designs
- Chuanjun Zhang, Frank Vahid, Walid A. Najjar:
A Highly-Configurable Cache Architecture for Embedded Systems. 136-146 - Alper Buyuktosunoglu, Tejas Karkhanis, David H. Albonesi, Pradip Bose:
Energy Efficient Co-Adaptive Instruction Fetch and Issue. 147-156 - Michael C. Huang, Jose Renau, Josep Torrellas:
Positional Adaptation of Processors: Application to Energy Reduction. 157-168 - Sudhanva Gurumurthi, Anand Sivasubramaniam, Mahmut T. Kandemir, Hubertus Franke:
DRPM: Dynamic Speed Control for Power Mangagement in Server Class Disks. 169-179
Interconnects and Multiprocessors
- Milo M. K. Martin, Mark D. Hill, David A. Wood:
Token Coherence: Decoupling Performance and Correctness. 182-193 - Arjun Singh, William J. Dally, Amit K. Gupta, Brian Towles:
GOAL: A Load-Balanced Adaptive Routing Algorithm for Torus Networks. 194-205 - Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, David A. Wood:
Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared-Memory Multiprocessors. 206-217 - Zarka Cvetanovic:
Performance Analysis of the Alpha 21364-BAsed HP GS1280 Multiprocessor. 218-228
Front-End Scheduling
- Paramjit S. Oberoi, Gurindar S. Sohi:
Parallelism in the Front-End. 230-240 - André Seznec, Antony Fraboulet:
Effective ahead Pipelining of Instruction Block Address Generation. 241-252 - Dan Ernst, Andrew Hamel, Todd M. Austin:
Cyclone: A Broadcast-Free Dynamic Instruction Scheduler with Selective Replay. 253-262
Clustered Processors
- Ravi Bhargava, Lizy Kurian John:
Improving Dynamic Cluster Assignment for Clustered Trace Cache Processors. 264-274 - Rajeev Balasubramonian, Sandhya Dwarkadas, David H. Albonesi:
Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors. 275-286
Network Processors
- Timothy Sherwood, George Varghese, Brad Calder:
A Pipelined Memory Architecture for High Throughput Network Processors. 288-299 - Jahangir Hasan, Satish Chandra, T. N. Vijaykumar:
Efficient Use of Memory Bandwidth to Improve Network Processor Throughput. 300-311
Prediction
- Renju Thomas, Manoj Franklin, Chris Wilkerson, Jared Stark:
Improving Branch Prediction by Dynamic Dataflow-Based Identification of Correlated Branches from a Large Global History. 314-323 - Huiyang Zhou, Jill Flanagan, Thomas M. Conte:
Detecting Global Stride Locality in Value Streams. 324-335 - Timothy Sherwood, Suleyman Sair, Brad Calder:
Phase Tracking and Prediction. 336-347
Mechanisms and Support
- Aravindh Anantaraman, Kiran Seth, Kaustubh Patil, Eric Rotenberg, Frank Mueller:
Virtual Simple Architecture (VISA): Exceeding the Complexity Limit in Safe Real-Time Systems. 350-361 - Marc L. Corliss, E. Christopher Lewis, Amir Roth:
DISE: A Programmable Macro Engine for Customizing Applications. 362-373 - Mark Oskin, Frederic T. Chong, Isaac L. Chuang, John Kubiatowicz:
Building Quantum Wires: The Long and the Short of It. 374-385
Memory Issues
- Zhenlin Wang, Doug Burger, Steven K. Reinhardt, Kathryn S. McKinley, Charles C. Weems:
Guided Region Prefetching: A Cooperative Hardware/Software Approach. 388-398 - Christoforos E. Kozyrakis, David A. Patterson:
Overcoming the Limitations of Conventional Vector Processors. 399-409 - Jinwoo Suh, Eun-Gyu Kim, Stephen P. Crago, Lakshmi Srinivasan, Matthew C. French:
A Performance Analysis of PIM, Stream Processing, and Tiled Processing on Memory-Intensive Signal Processing Kernels. 410-419
Exploiting Parallelisms
- Karthikeyan Sankaralingam, Ramadass Nagarajan, Haiming Liu, Changkyu Kim, Jaehyuk Huh, Doug Burger, Stephen W. Keckler, Charles R. Moore:
Exploiting ILP, TLP and DLP with the Polymorphous TRIPS Architecture. 422-433 - Michael K. Chen, Kunle Olukotun:
The Jrpm System for Dynamically Parallelizing Java Programs. 434-445
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