![](https://dblp.dagstuhl.de/img/logo.ua.320x120.png)
![](https://dblp.dagstuhl.de/img/dropdown.dark.16x16.png)
![](https://dblp.dagstuhl.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp.dagstuhl.de/img/search.dark.16x16.png)
![search dblp](https://dblp.dagstuhl.de/img/search.dark.16x16.png)
default search action
40th ISCA 2013: Tel-Aviv, Israel
- Avi Mendelson:
The 40th Annual International Symposium on Computer Architecture, ISCA'13, Tel-Aviv, Israel, June 23-27, 2013. ACM 2013, ISBN 978-1-4503-2079-5
Accelerators and emerging architectures
- Bilel Belhadj, Antoine Joubert, Zheng Li, Rodolphe Héliot, Olivier Temam:
Continuous real-world inputs can open up alternative accelerator designs. 1-12 - Paula Petrica, Adam M. Izraelevitz, David H. Albonesi, Christine A. Shoemaker
:
Flicker: a dynamically adaptive architecture for power limited multicore systems. 13-23 - Wajahat Qadeer, Rehan Hameed, Ofer Shacham, Preethi Venkatesan, Christos Kozyrakis, Mark A. Horowitz:
Convolution engine: balancing efficiency & flexibility in specialized computing. 24-35 - Kevin T. Lim, David Meisner, Ali G. Saidi, Parthasarathy Ranganathan, Thomas F. Wenisch:
Thin servers with smart pipes: designing SoC accelerators for memcached. 36-47
DRAM and memory controller issues
- Janani Mukundan, Hillery C. Hunter, Kyu-Hyoun Kim
, Jeffrey Stuecheli, José F. Martínez
:
Understanding and mitigating refresh overheads in high-density DDR4 DRAM systems. 48-59 - Jamie Liu, Ben Jaiyen, Yoongu Kim, Chris Wilkerson, Onur Mutlu:
An experimental study of data retention behavior in modern DRAM devices: implications for retention time profiling mechanisms. 60-71 - Prashant J. Nair, Dae-Hyun Kim, Moinuddin K. Qureshi:
ArchShield: architectural framework for assisting DRAM scaling by tolerating high error rates. 72-83 - Saugata Ghose, Hyodong Lee, José F. Martínez
:
Improving memory scheduling via processor-side load criticality information. 84-95
Virtualization
- Canturk Isci, Suzanne McIntosh
, Jeffrey O. Kephart, Rajarshi Das, James E. Hanson, Scott Piper, Robert R. Wolford, Thomas Brey, Robert Kantner, Allen Ng, James Norris, Abdoulaye Traore, Michael Frissora:
Agile, efficient virtualization power management with low-latency server power states. 96-107 - Cheng-Chun Tu, Chao-Tang Lee, Tzi-cker Chiueh:
Secure I/O device sharing among virtual machines on multiple hosts. 108-119 - Xiaotao Chang, Hubertus Franke, Yi Ge, Tao Liu, Kun Wang, Jimi Xenidis, Fei Chen, Yu Zhang:
Improving virtualization in the presence of software managed translation lookaside buffers. 120-129
Heterogeneous and fine-grained architectures
- Ji Kim, Christopher Torng, Shreesha Srinath, Derek Lockhart, Christopher Batten:
Microarchitectural mechanisms to exploit value structure in SIMT architectures. 130-141 - Angshuman Parashar, Michael Pellauer, Michael Adler, Bushra Ahsan, Neal Clayton Crago, Daniel Lustig, Vladimir Pavlov, Antonia Zhai, Mohit Gambhir, Aamer Jaleel, Randy L. Allmon, Rachid Rayess, Stephen Maresh, Joel S. Emer:
Triggered instructions: a control paradigm for spatially-programmed architectures. 142-153 - José A. Joao, M. Aater Suleman, Onur Mutlu, Yale N. Patt:
Utility-based acceleration of multithreaded applications on asymmetric CMPs. 154-165
Emerging technologies
- Daniel Kudrow, Kenneth Bier, Zhaoxia Deng, Diana Franklin, Yu Tomita, Kenneth R. Brown, Frederic T. Chong:
Quantum rotations: a case study in static and dynamic machine-code generation for quantum computers. 166-176 - Richard A. Muscat, Karin Strauss, Luis Ceze, Georg Seelig:
DNA-based molecular architecture with spatially localized components. 177-188 - Qing Guo, Xiaochen Guo, Ravi Patel, Engin Ipek, Eby G. Friedman:
AC-DIMM: associative computing with STT-MRAM. 189-200
Memory consistency and transactions
- Blake A. Hechtman, Daniel J. Sorin:
Exploring memory consistency for massively-threaded throughput-oriented processors. 201-212 - Yuelu Duan, Abdullah Muzahid, Josep Torrellas:
WeeFence: toward making fences free in TSO. 213-224 - Harold W. Cain, Maged M. Michael, Brad Frey, Cathy May, Derek Williams, Hung Q. Le:
Robust architectural support for transactional memory in the power architecture. 225-236
Big data
- Arkaprava Basu, Jayneel Gandhi
, Jichuan Chang, Mark D. Hill, Michael M. Swift:
Efficient virtual memory for big memory servers. 237-248 - Lisa Wu
, Raymond J. Barker, Martha A. Kim
, Kenneth A. Ross:
Navigating big data with high-throughput, energy-efficient data partitioning. 249-260 - Eric S. Chung, John D. Davis, Jaewon Lee:
LINQits: big data on little clients. 261-272 - Islam Atta, Pinar Tözün
, Xin Tong, Anastasia Ailamaki, Andreas Moshovos:
STREX: boosting instruction cache reuse in OLTP workloads through stratified transaction execution. 273-284
Power and energy
- Indrani Paul, Srilatha Manne, Manish Arora, William Lloyd Bircher, Sudhakar Yalamanchili:
Cooperative boosting: needy versus greedy power management. 285-296 - Anys Bacha, Radu Teodorescu:
Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors. 297-307 - Henry Cook, Miquel Moretó
, Sarah Bird, Khanh Dao, David A. Patterson, Krste Asanovic:
A hardware evaluation of cache partitioning to improve utilization and energy-efficiency while preserving responsiveness. 308-319 - Reetuparna Das
, Satish Narayanasamy
, Sudhir Satpathy, Ronald G. Dreslinski:
Catnap: energy proportional multiple network-on-chip. 320-331
GPUs
- Adwait Jog, Onur Kayiran, Asit K. Mishra, Mahmut T. Kandemir, Onur Mutlu, Ravishankar R. Iyer, Chita R. Das:
Orchestrated scheduling and prefetching for GPGPUs. 332-343 - Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang:
An energy-efficient and scalable eDRAM-based register file architecture for GPGPU. 344-355 - Minsoo Rhu, Mattan Erez
:
Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation. 356-367 - Aniruddha S. Vaidya, Anahita Shayesteh, Dong Hyuk Woo, Roy Saharoy, Mani Azimi:
SIMD divergence optimization through intra-warp compaction. 368-379
Memory
- Young Hoon Son, Seongil O, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn
:
Reducing memory access latency with asymmetric DRAM bank organizations. 380-391 - Ziyi Liu, Jong-Hyuk Lee, Junyuan Zeng, Yuanfeng Wen, Zhiqiang Lin, Weidong Shi:
CPU transparent protection of OS kernel and hypervisor integrity with programmable DRAM. 392-403 - Djordje Jevdjic, Stavros Volos, Babak Falsafi:
Die-stacked DRAM caches for servers: hit ratio, latency, or bandwidth? have it all with footprint cache. 404-415 - Jaewoong Sim, Gabriel H. Loh, Vilas Sridharan, Mike O'Connor
:
Resilient die-stacked DRAM caches. 416-427
Non-volatile storage
- Yu Du, Miao Zhou, Bruce R. Childers, Daniel Mossé, Rami G. Melhem:
Bit mapping for balanced PCM cell programming. 428-439 - Nak Hee Seong, Sungkap Yeo, Hsien-Hsin S. Lee:
Tri-level-cell phase change memory: toward an efficient and reliable memory system. 440-451 - Rodolfo Azevedo
, John D. Davis, Karin Strauss, Parikshit Gopalan, Mark S. Manasse, Sergey Yekhanin:
Zombie memory: extending memory lifetime by reviving dead blocks. 452-463 - Adrian M. Caulfield, Steven Swanson
:
QuickSAN: a storage area network for fast, distributed, solid state disks. 464-474
Simulation and analysis techniques
- Daniel Sánchez, Christos Kozyrakis:
ZSim: fast and accurate microarchitectural simulation of thousand-core systems. 475-486 - Jingwen Leng, Tayler H. Hetherington, Ahmed ElTantawy, Syed Zohaib Gilani, Nam Sung Kim, Tor M. Aamodt, Vijay Janapa Reddi:
GPUWattch: enabling energy optimizations in GPGPUs. 487-498 - Meng-Ju Wu, Minshu Zhao, Donald Yeung:
Studying multicore processor scaling via reuse distance analysis. 499-510 - Kristof Du Bois, Stijn Eyerman, Jennifer B. Sartor, Lieven Eeckhout:
Criticality stacks: identifying critical threads in parallel programs using synchronization behavior. 511-522
Cache coherence
- George Kurian, Omer Khan, Srinivas Devadas:
The locality-aware adaptive cache coherence protocol. 523-534 - Stefanos Kaxiras, Alberto Ros
:
A new perspective for efficient virtual-cache coherence. 535-546 - Hongzhou Zhao, Arrvindh Shriraman, Snehasish Kumar, Sandhya Dwarkadas:
Protozoa: adaptive granularity cache coherence. 547-558
Security
- John Demme, Matthew Maycock, Jared Schmitz, Adrian Tang, Adam Waksman, Simha Sethumadhavan, Salvatore J. Stolfo:
On the feasibility of online malware detection with performance counters. 559-570 - Ling Ren, Xiangyao Yu, Christopher W. Fletcher, Marten van Dijk
, Srinivas Devadas:
Design space exploration and optimization of path oblivious RAM in secure processors. 571-582 - Hassan M. G. Wassel, Ying Gao, Jason Oberg, Ted Huffmire, Ryan Kastner
, Frederic T. Chong
, Timothy Sherwood
:
SurfNoC: a low latency and provably non-interfering approach to secure networks-on-chip. 583-594
Data centers
- Di Wang, Chuangang Ren, Anand Sivasubramaniam:
Virtualizing power distribution in datacenters. 595-606 - Hailong Yang, Alex D. Breslow, Jason Mars, Lingjia Tang:
Bubble-flux: precise online QoS management for increased utilization in warehouse scale computers. 607-618 - Jason Mars, Lingjia Tang:
Whare-map: heterogeneity in "homogeneous" warehouse-scale computers. 619-630
Reliability and debugging
- Nikos Foutris, Dimitris Gizopoulos, Xavier Vera, Antonio González
:
Deconfigurable microprocessor architectures for silicon debug acceleration. 631-642 - Gilles Pokam, Klaus Danne, Cristiano Pereira, Rolf Kassa, Tim Kranich, Shiliang Hu, Justin Emile Gottschlich, Nima Honarmand, Nathan Dautenhahn, Samuel T. King, Josep Torrellas:
QuickRec: prototyping an intel architecture extension for record and replay of multithreaded programs. 643-654 - Ruirui C. Huang, Erik Halberg, G. Edward Suh
:
Non-race concurrency bug detection through order-sensitive critical sections. 655-666
![](https://dblp.dagstuhl.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.