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ORCIDISCAS 2002: Scottsdale, Arizona, USA - Volume 3
- Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002. IEEE 2002, ISBN 0-7803-7448-7
- Hoi-Kok Cheung, Wan-Chi Siu:
Fast global motion estimation for sprite generation. 1-4 - Wing Cheong Chan, Oscar C. Au, Ming Fai Fu:
A novel predictive global motion estimation for video coding. 5-8 - Zhibo Chen, Cheng Du, Jinghua Wang, Yun He:
PPFPS - a paraboloid prediction based fractional pixel search strategy for H.26L. 9-12 - Ming Fai Fu, Oscar C. Au, Wing Cheong Chan:
Low-band-shift (LBS) motion estimation with symmetric padding in wavelet domain. 13-16 - Qilian Liang:
Link adaptation and receiver design for enhanced General Packet Radio Services wireless networks. 17-20 - Qilian Liang:
Bandwidth utilization and signal strength-based handover initiation in mobile multimedia cellular networks. 21-24 - J. Zhang, Kamal Premaratne, Peter H. Bauer:
Local resource management of distributed sensor networks via static output feedback control. 25-28 - Panu Hämäläinen, Marko Hännikäinen, Markku Niemi, Timo Hämäläinen:
Performance evaluation of Secure Remote Password protocol. 29-32 - Toshio Koide, Takeshi Ishibashi, Hitoshi Watanabe:
Network optimization problem in tie-set flow vector space and information network resource management. 33-36 - Shannon D. Blunt
, Dominic K. C. Ho:
A novel sparse adaptive algorithm using wavelets. 37-40 - K. Konishi, K. Okuyama, A. Kato, T. Furukawa:
Design method for optimal step size matrix of the affine projection algorithm using semidefinite programming. 41-44 - Dominic K. C. Ho, Shannon D. Blunt:
Enhanced adaptive sparse algorithms using the Haar wavelet. 45-48 - Ken Okuyama, Sadanobu Yoshimoto, Toshihiro Furukawa:
New adaptive Kalman filters using filter bank. 49-52 - Eftychios V. Papoulis, Tania Stathaki:
A transmultiplexer-based adaptive filtering structure using a new adaptation scheme. 53-56 - M. Miyamura, Yoshifumi Nishio, Akio Ushida:
Clustering in globally coupled system of chaotic circuits. 57-60 - Silvano Cincotti, Andrea Teglio:
Generalized synchronization on linear manifold in coupled nonlinear systems. 61-64 - Vinay Varadan, Henry Leung:
Chaotic system reconstruction from noisy time series measurements using improved least squares genetic programming. 65-68 - Roberto Tonelli, Leon O. Chua, Franco Meloni:
Mapping atoms to nonlinear Chua's circuits. 69-72 - Han Jung Song, Kae-Dal Kwack:
CMOS circuit design and implementation of the discrete time chaotic chip. 73-76 - Chih-Chun Tang, Chia-Hsin Wu, Kun-Hsien Li, Tai-Cheng Lee, Shen-Iuan Liu:
CMOS 2.4-GHz receiver front end with area-efficient inductors and digitally calibrated 90° delay network. 77-80 - Luis Hernández, Susana Patón:
A superregenerative receiver for phase and frequency modulated carriers. 81-84 - Keliu Shu, Edgar Sánchez-Sinencio:
A 5-GHz prescaler using improved phase switching. 85-88 - Kwang-Jin Koh, Yong-Sik Youn, Hyun-Kyu Yu:
A gain boosting method at RF frequency using active feedback and its application to RF variable gain amplifier (VGA). 89-92 - Sabri Arik, Vedat Tavsanoglu:
On the global robust stability of delayed neural networks. 93-96 - K. Jin'no:
Oscillatory hysteresis associative memory. 97-100 - Víctor M. Brea, David López Vilariño, Ari Paasio, Diego Cabello:
Implementation oriented theory design issues on the DTCNN template generation. 101-104 - William Soares-Filho, José Manoel de Seixas, Luiz Pereira Calôba:
Enlarging neural class detection capacity in passive sonar systems. 105-108 - Simone G. O. Fiori, Pietro Burrascano:
Nonsymmetric PDF approximation by artificial neurons: application to statistical characterization of reinforced composites. 109-112 - Qun Gao, P. Messmer, George S. Moschytz:
Binary image rotation using cellular neural networks. 113-116 - Yu-Yee Liow, Chung-Yu Wu:
The design of high-speed pipelined analog-to-digital converters using voltage-mode sampling and current mode processing techniques. 117-120 - Z. Tao, M. Keramat:
A 10-bit 100-MS/s 50 mW CMOS A/D converter. 121-124 - V. Srinivasan, S. K. Islam, G. T. Hendrickson:
A method for the estimation of aperture uncertainty in A-D converters. 125-128 - Jonas Elbornsson, Kalle Folkesson, Jan-Erik Eklund:
Measurement verification of estimation method for time errors in a time-interleaved A/D converter system. 129-132 - Jafar Talebzadeh, Mohammad Reza Hassanzadeh, Mohammad Yavari, Omid Shoaei:
A 10-bit 150-MS/s, parallel pipeline A/D converter in 0.6-µm CMOS. 133-136 - Hongwei Wang, Cheong-Fat Chan, Chiu-sing Choy:
A 12-bit 80 Ms/s 110 mW floating analog-to-digital converter. 137-140 - Weidong Guo, Robert J. Huber, Kent F. Smith:
A current steering CMOS folding amplifier. 141-144 - Charles T. Peach, Waisiu Law, D. R. Beck, Ward J. Helms, David J. Allstot:
Matching considerations in I/Q A/D converter pairs. 145-148 - Yonghua Cong, Randall L. Geiger:
Formulation of INL and DNL yield estimation in current-steering D/A converters. 149-152 - Janusz A. Starzyk, Dong Liu:
Locating stuck faults in analog circuits. 153-156 - Janusz A. Starzyk, Dong Liu:
A decomposition method for analog fault location. 157-160 - S. Cailotto, Alessandro Fin, Franco Fummi:
A fault tolerant incremental design methodology. 161-164 - Stefan R. Meier, Mario Steinert, Steffen Buch:
Testability of path history memories with register-exchange architecture used in Viterbi-decoders. 165-168 - Maurizio Martignano, Nicola Drago, Franco Fummi, Stefano Martini:
A combined approach to validate the design of embedded network devices. 169-172 - Ye-Ming Li, J. Alvin Connelly:
Modeling a resonant LC tank circuit embedded in a VCO. 173-176 - Youcef Fouzar, Yvon Savaria, Mohamad Sawan:
A CMOS phase-locked loop with an auto-calibrated VCO. 177-180 - H. Parthasarathy, Ghanshyam Nayak, Ponnathpur R. Mukund:
Analysis of VCO jitter in chip-package co-design. 181-184 - Yonghui Tang, Randall L. Geiger:
Transient bit error rate analysis of data recovery systems using jitter models. 185-188 - Mieczyslaw Jessa, Marcin Walentynowicz:
Discrete-time phase-locked loop as a source of random sequences with different distributions. 189-192 - Julius Georgiou, Christofer Toumazou:
A resistorless low current reference circuit for implantable devices. 193-196 - Dean A. Badillo:
1.5V CMOS current reference with extended temperature operating range. 197-200 - A. Bendali, Yvon Savaria:
Low-voltage bandgap reference with temperature compensation based on a threshold voltage technique. 201-204 - A. Azarkan, Arie van Staveren, Fabiano Fruett:
A low-noise bandgap reference voltage source with curvature correction. 205-208 - Han-Seung Jung, Nam Ik Cho, Sang Uk Lee:
Image-adaptive watermarking based on warped discrete cosine transform. 209-212 - Akio Miyazaki, Akihiro Okamoto:
Analysis and improvement of correlation-based watermarking methods for digital images. 213-216 - Shiwei Zhang, P. K. Rajan:
Independent component analysis of digital image watermarking. 217-220 - Ya Jun Yu, Yong Ching Lim:
FRM based FIR filter design - the WLS approach. 221-224 - Tapio Saramäki, Juha Yli-Kaakinen:
Optimization of frequency-response-masking based FIR filters with reduced complexity. 225-228 - Sergio L. Netto, Paulo S. R. Diniz, Luiz C. R. de Barcellos:
Efficient implementation for cosine-modulated filter banks using the frequency response masking approach. 229-232 - Linnéa Svensson, Håkan Johansson:
Frequency response masking FIR filters with short delay. 233-236 - Chun Zhu Yang, Yong Lian:
A modified structure for the design of sharp FIR filters using frequency response masking technique. 237-240 - Say Wei Foo, Edwin Wei Thai Lee:
Transcription of polyphonic signals using fast filter bank. 241-244 - G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith:
Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family. 245-248 - Massimo Alioto, Gaetano Palumbo:
Power-delay trade-offs in SCL gates. 249-252 - Hong-Yi Huang, Jing-Fu Lin:
CMOS bulk input technique. 253-256 - Ramin Rafati, A. Z. Charaki, G. R. Chaji, Seid Mehdi Fakhraie, Kenneth Carless Smith:
Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D3L (D4L) logic styles. 257-260 - Rouwaida Kanj, Elyse Rosenbaum:
A critical look at design guidelines for SOI logic gates. 261-264 - Frank Livingston, Vikram Chandrasekhar, Mani Vaya, Joseph R. Cavallaro:
Handset detector architectures for DS-CDMA wireless systems. 265-268 - Yoshihiro Uchida, Masanao Ise, Takao Onoye, Isao Shirakawa, Itthichai Arungsrisangchai:
VLSI architecture of digital matched filter and prime interleaver for W-CDMA. 269-272 - Kwan-wai Wong, Chi-Ying Tsui, Roger S.-K. Cheng, Wai Ho Mow:
A VLSI architecture of a K-best lattice decoding algorithm for MIMO channels. 273-276 - A. Perez-Pascual, T. Sansaloni, Javier Valls:
FPGA-based radix-4 butterflies for HIPERLAN/2. 277-280 - Byung S. Son, Byung G. Jo, Myung Hoon Sunwoo, Yong Serk Kim:
A high-speed FFT processor for OFDM systems. 281-284 - Anas A. Hamoui, Kenneth W. Martin:
Linearity enhancement of multibit Delta-Sigma modulators using pseudo data-weighted averaging. 285-288 - Neil A. Fraser, Behrouz Nowrouzian:
A novel technique to estimate the statistical properties of Sigma-Delta A/D converters for the investigation of DC stability. 289-292 - Lourans Samid, Maurits Ortmanns, Yiannos Manoli, Friedel Gerfers:
A new kind of low-power multibit third order continuous-time lowpass Sigma-Delta modulator. 293-296 - Fausto Borghetti, Antonio Esposito, Umberto Gatti, Piero Malcovati, Franco Maloberti:
BiCMOS switched buffers resonator for a 320 MHz 2-path sigma-delta modulator. 297-300 - Rocío del Río, Fernando Medeiro, José M. de la Rosa, Maria Belen Pérez-Verdú, Ángel Rodríguez-Vázquez:
A 2.5-V Sigma-Delta modulator in 0.25-µm CMOS for ADSL. 301-304 - George Palaskas, Yannis P. Tsividis:
Design considerations and experimental evaluation of a syllabic companding audio frequency filter. 305-308 - Andrew E. J. Ng, John I. Sewell:
Direct noise analysis of log-domain filters. 309-312 - Sandro A. P. Haddad, Wouter A. Serdijn:
High-frequency dynamic translinear and log-domain circuits in CMOS technology. 313-316 - Esther Rodríguez-Villegas, Adoración Rueda, Alberto Yufera:
A micropower log domain FGMOS filter. 317-320 - Eric J. McDonald, Bradley A. Minch:
Synthesis of a translinear analog adaptive filter. 321-324 - Qiang Luo, John G. Harris:
A novel integration of on-sensor wavelet compression for a CMOS imager. 325-328 - Richard A. Blum, Charles S. Wilson, Paul E. Hasler, Stephen P. DeWeerth:
A CMOS imager with real-time frame differencing and centroid computation. 329-332 - Hiroe Kimura, Tadashi Shibata:
A motion-based analog VLSI saliency detector using quasi-two-dimensional hardware algorithm. 333-336 - Paul E. Hasler, Abhishek Bandyopadhyay, Paul D. Smith:
A matrix transform imager allowing high-fill factor. 337-340 - Gustavo Liñán Cembrano, Servando Espejo-Meana, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez:
A processing element architecture for high-density focal plane analog programmable array processors. 341-344 - Alfred Fettweis, Nirmal K. Bose:
A property of Jacobian matrices and some of its consequences. 345-348 - Sankar Basu:
On spectral factorization in two-dimensions. 349-352 - Wu-Sheng Lu, Andreas Antoniou:
Minimax design of 2-D IIR digital filters using sequential semidefinite programming. 353-356 - Anastasios N. Venetsanopoulos, Konstantinos N. Plataniotis, Marek Szczepanski, Bogdan Smolka:
On the geodesic paths approach to multichannel signal processing. 357-360 - Alfred Fettweis:
Improved wave-digital approach to numerically integrating the PDES of fluid dynamics. 361-364 - Terry Tao Ye, Samit Chaudhuri, Fei Huang, Hamid Savoj, Giovanni De Micheli:
Physical synthesis for ASIC datapath circuits. 365-368 - Delong Shang, Fei Xia, Alexandre Yakovlev:
Asynchronous circuit synthesis via direct translation. 369-372 - Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Kunihiro Asada:
Logic synthesis for PLA with 2-input logic elements. 373-376 - Susanto Rahardja, Bogdan J. Falkowski:
Polynomial expansions over GF(2) based on fastest transformation. 377-380 - Bogdan J. Falkowski, Radomir S. Stankovic, Dragan Jankovic:
Circuit design from minimized Haar wavelet series. 381-384 - Xiaoyan Sun, Feng Wu, Shipeng Li, Wen Gao, Ya-Qin Zhang:
Seamless switching of scalable video bitstreams for efficient streaming. 385-388 - Kai-Tat Fung, Wan-Chi Siu, Yui-Lam Chan:
A dynamic frame-skipping video combiner for multipoint video conferencing. 389-392 - Hao Wang, Guobin Shen, Shipeng Li, Yuzhuo Zhong:
Efficient error recovery techniques in a novel multimedia streaming framework with peer-paired collaboration. 393-396 - Zhi-Wei Gao, Wen-Nung Lie:
MPEG-4 video error detection by using data hiding techniques. 397-400 - Hsiang-Chun Huang, Chung-Neng Wang, Tihao Chiang:
A robust fine granularity scalability using trellis based predictive leak. 401-404 - Toshimichi Saito, M. Yoshizawa, Hiroyuki Torikai, Shintaro Tazaki:
Analysis of interleaved converters with WTA-based switching. 405-408 - Yefim Berkovich, Adrian Ioinovici:
Analysis and design of PWM regulators for large-signal stability. 409-412 - Tadashi Suetsugu, Marian K. Kazimierczuk:
A method for predicting the ZVS condition for the class E amplifier. 413-416 - Masaru Ogawa:
Magnetizing inrush current of a transformer and a new technique of its computation. 417-420 - Somchart Chokchaitam, Masahiro Iwahashi:
Lossless/lossy image compression based on non-separable two-dimensional L-SSKF. 421-424 - Wei Dai, Trac D. Tran, Soontorn Oraintara, Truong Q. Nguyen:
Integer- and rational-coefficient M-band wavelet. 425-428 - Cheong Yiu Fung, S. C. Chan:
A multistage filterbank-based channelizer and its multiplier-less realization. 429-432 - Soontorn Oraintara:
The unified discrete Fourier-Hartley transforms: theory and structure. 433-436 - Min Li, Chi-Wah Kok:
Linear phase IIR filter bank design by LMI based Hinfinity optimization. 437-440 - J. Bhattacharjee, D. Mukherjee, Joy Laskar:
A monolithic CMOS VCO for wireless LAN applications. 441-444 - Yan Wang, Hing Mo Lam, Chi-Ying Tsui, Roger S. Cheng, Wai Ho Mow:
Low complexity OFDM receiver using Log-FFT for coded OFDM system. 445-448 - Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner:
Design of an efficient OFDM burst synchronization scheme. 449-452 - Yuanbin Guo, Joseph R. Cavallaro:
A novel adaptive pre-distorter using LS estimation of SSPA non-linearity in mobile OFDM systems. 453-456 - Chunyu Xin, Bo Xia, Wenjun Sheng, Ari Yakov Valero-López, Edgar Sánchez-Sinencio:
A mixed-mode IF GFSK demodulator for Bluetooth. 457-460 - Tomoya Hayashi, Yoshifumi Nishio, Martin Hasler, Akio Ushida:
Response of coupled chaotic circuits to sinusoidal input signal. 461-464 - Yoko Uwate, Yoshifumi Nishio, Tetsushi Ueta, Tohru Kawabe, Tohru Ikeguchi:
Solving ability of Hopfield neural network with chaotic noise and burst noise for quadratic assignment problem. 465-468 - Tohru Ikeguchi, Koya Sato, Mikio Hasegawa, Kazuyuki Aihara:
Chaotic optimization for quadratic assignment problems. 469-472 - GuoJie Hu, ZhengJin Feng, Lin Wang:
Analysis of a type of digital chaotic cryptosystem. 473-475 - Mieczyslaw Jessa:
Data transmission with adjustable security exploiting chaos-based pseudorandom number generators. 476-479 - Mohamed Rezki, Lesley P. Sabel, Izzet Kale:
A prefiltering approach to frequency offset estimation in AWGN. 480-483 - A. W. Gunst, G. W. Kant:
Application of digital wide band mismatch calibration to an I/Q receiver. 484-487 - Arata Kawamura, Kensaku Fujii, Yoshio Itoh, Yutaka Fukui:
A new noise reduction method using linear prediction error filter and adaptive digital filter. 488-491 - Qiyue Zou, Zhiping Lin:
Measurement time requirement for generalized cross-correlation based time-delay estimation. 492-495 - Wei Xing Zheng:
A modified identification algorithm for linear systems with noisy input-output data. 496-499 - Khier Benmahammed, Abdelaziz Hamzaoui:
Application of the SD to LCTI systems 1. 500-502 - Khier Benmahammed, Abdelaziz Hamzaoui:
Application of the SD to LCTI systems 2. 503-506 - Gunther Reißig, Holger Boche, Paul I. Barton:
On inconsistent initial conditions for linear time-invariant differential-algebraic equations. 507-510 - Yang Xiao:
Derivation algorithm of transfer functions of 2-D continuous-discrete systems. 511-514 - Sidnei Noceti Filho, Rui Seara:
Cut-off frequencies in wide-band systems. 515-518 - Antônio Carlos M. de Queiroz:
Generalized LC multiple resonance networks. 519-522 - Karel Hajek, Z. Sedlacek, B. Sviezeny:
New circuits for realization of the 1st and 2nd order all-pass LC filters with a better technological feasibility. 523-526 - B. Siddik Yarman, Ahmet Aksen, Ali Kilinc:
Immitance data modelling via linear interpolation techniques. 527-530 - Esteban Tlelo-Cuautle:
Computing the elements embedded into a positive feedback loop. 531-534 - Esteban Tlelo-Cuautle:
An efficient biasing technique suitable for any kind of the four basic amplifiers designed at or level. 535-538 - Mladen Vucic, Hrvoje Babic:
A robust method for equalizer design based on the impulse response symmetry. 539-542 - Jiwei Chen, Bingxue Shi:
Analysis and optimization of CMOS LNA noise performance with channel resistance. 543-546 - Aziz S. Inan, Peter M. Osterberg:
Revisiting the sifting integral: an interesting special case. 547-550 - Hengsheng Liu, Aydin I. Karsilayan:
An automatic tuning scheme for high frequency bandpass filters. 551-554 - Aleksandar Tasic, Wouter A. Serdijn:
Concept of frequency-transconductance tuning of bipolar voltage-controlled oscillators. 555-558 - Mohammed Sayed, Wael M. Badawy:
Performance analysis of single-bit full adder cells using 0.18, 0.25, and 0.35 µm CMOS technologies. 559-562 - Amar Aggoun, A. Farwan, M. K. Ibrahim:
A radix-2n vector inner product. 563-566 - Johann Großschädl:
A unified radix-4 partial product generator for integers and binary polynomials. 567-570 - Robert Hägglund, Per Löwenborg, Mark Vesterbacka:
A polynomial-based division algorithm. 571-574 - Meng-Hung Tsai, Yi-Ting Chen, Wen-Sheng Cheng, Jun-Xian Teng, Shyh-Jye Jou:
Sub-word and reduced-width Booth multipliers for DSP applications. 575-578 - Ayman A. Fayed, Magdy A. Bayoumi:
Noise-tolerant design and analysis for a low-voltage dynamic full adder cell. 579-582 - Lorenzo Repetto, Marco Storace, Mauro Parodi:
A procedure for the piecewise-linear approximation of the resistive part of a cellular nonlinear network. 583-586 - Simone Orcioni, Massimiliano Pirani, Claudio Turchetti, Massimo Conti:
Practical notes on two Volterra filter identification direct methods. 587-590 - Antti Heiskanen, Timo Rahkonen:
5th order multi-tone Volterra simulator with component-level output. 591-594 - Christian Niederhöfer, S. Suna, Ronald Tetzlaff:
Nonlinear prediction of brain electrical activity in epilepsy with a Volterra RLS algorithm. 595-598 - Mikio Hasegawa, Tohru Ikeguchi:
An analysis of the Internet traffic by the method of surrogate data. 599-602 - Volney C. Vincence, Carlos Galup-Montoro, Márcio C. Schneider:
A low-voltage CMOS class-AB operational amplifier. 603-606 - Godi Fischer, Deokhwan Hyun:
Delta-sigma modulator topologies with high immunity to pattern noise. 703-706 - Pieter Rombouts, Johan Raman, Ludo Weyten:
An efficient technique to eliminate quantisation noise folding in double-sampling Sigma-Delta modulators. 707-710 - Bingxin Li, Hannu Tenhunen:
A structure of cascading multi-bit modulators without dynamic element matching or digital correction. 711-714 - R. Batten, Terri S. Fiez:
An efficient parallel delta-sigma ADC utilizing a shared multi-bit quantizer. 715-718 - Dan P. Scholnik, Jeffrey O. Coleman:
Space-time vector delta-sigma modulation. 719-722 - Kazuyuki Wada, Yoshiaki Tadokoro:
Design of a body-effect reduced-source follower and its application to linearization technique. 723-726 - Reid R. Harrison:
A wide-linear-range subthreshold CMOS transconductor employing the back-gate effect. 727-730 - Slawomir Koziel, Stanislaw Szczepanski, Rolf Schaumann:
Design of highly linear tunable CMOS OTA. 731-734 - Adrian Leuciuc, Yi Zhang:
A highly linear low-voltage MOS transconductor. 735-738 - Takao Oura, Teru Yoneyama, Shashidhar Tantry, Hideki Asai:
A threshold voltage independent floating resistor circuit exhibiting both positive and negative resistance values. 739-742 - Yuichi Tanji, Akio Ushida, Michel S. Nakhla:
Passive closed-form expression of RLCG transmission lines. 795-798 - Jean-Michel Portal, L. Forli, Didier Née:
Floating-gate EEPROM cell model based on MOS model 9. 799-802 - Zbigniew Galias, Gian Mario Maggio:
On the optimal labeling for pseudo-chaotic phase hopping. 883-886 - Sergio Callegari, Riccardo Rovatti, Gianluca Setti:
Folded sums of chaotic trajectories distribute uniformly. 891-894 - Riccardo Rovatti, Sergio Callegari, Gianluca Setti:
On the correlation of non-jittered and chaotically-jittered PWM signals carrying maximum information. 895-898
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