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ORCID55th ISMVL 2025: Montreal, QC, Canada
- 55th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2025, Montreal, QC, Canada, June 5-6, 2025. IEEE 2025, ISBN 979-8-3315-0744-2
- Shunsuke Fukami:
Probabilistic computing utilizing stochastic spintronic devices. 1-3 - Tomohiro Yoneda, Yasuhiro Takako, Akira Tamakoshi, Masanori Natsui, Daisuke Suzuki, Takahiro Hanyu:
Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique. 4-9 - Fangcen Zhong, Masanori Natsui, Takahiro Hanyu:
Intelligent Power-Gating Technique with Quick Wake-Up/Sleep Functionality for Spintronics-Based Edge Computing Hardware. 10-14 - Ryan Seah, Tingting Zhang, Warren J. Gross:
Enhanced Simulated Bifurcation for MIMO Detection. 15-20 - Alexander Sakharov:
Multi-Valued Models for Intuitionistic Logic. 21-25 - Ondrej Majer, Igor Sedlár:
On Many-Valued Modal Probabilistic Logics. 26-31 - Libor Behounek:
A Predicate Variant of Two-Layered Many-Valued Probability Logic. 32-37 - Jordi Coll, Chu Min Li, Felip Manyà, Elifnaz Yangin:
A Complete Tableau Calculus for Signed MaxSAT. 38-43 - Zeljko Zilic:
Contributions of K. C. Smith in Applications of Multiple-Valued Logic. 44-49 - Vincent Gaudet:
Memories of K. C. Smith: Analog Computing, Multiple-Valued Logic and Machine Learning. 50 - Eric-Khang Dao, Katherine Zukotynski, Sandra E. Black, Vincent Gaudet:
Hardware-Compatible U-Net for Low-Dose PET Reconstruction. 51-56 - Alireza Dabbaghian, Hossein Kassiri:
Energy-Efficient Automated Seizure Detection in Wearable/Implantable BCIs: Motivations, Methods, and Example Implementation. 57-62 - Takao Waho, Akihisa Koyama, Hitoshi Hayashi:
Delta-sigma modulated noise-shaping bitstreams for multilayer perceptron. 63-68 - Shigeo Sato, Satoshi Moriya, Masaya Ishikawa, Hideaki Yamamoto:
Analog CMOS Spiking Neural Network for Time-Series Signal Recognition. 69 - Daisuke Suzuki, Akira Tamakoshi, Tomohiro Yoneda, Masanori Natsui, Yasuhiro Takako, Takahiro Hanyu:
An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware. 70-73 - Masashi Imai:
Simulation and Evaluation of Asynchronous Circuits in Extreme Edge Environments. 74-79 - Naoya Onizawa, Takahiro Hanyu:
Generating Hamiltonians with Known Minimum Energy Based on Ground-State Spin Logic for Probabilistic-Bit-Based Simulated Annealing. 80-85 - Tagir Nukenov, Kamila Abdiyeva, Oliver Keszöcze
, Shinobu Nagayama, Martin Lukac:
Binarization and Classification of RGB Images. 86-91 - Aviraj Sinha, Darrell L. Young, Eric C. Larson, Mitchell A. Thornton:
MUSIC Spectra Using Cayley Graphs of Multiple-Valued Signals. 92-97 - Steven Bos, Vetle Bodahl, Ole Christian Moholth, Henning Gundersen:
REBEL-6: A 32-trit balanced ternary instruction set architecture with R2R compiler pipeline for C. 98-103 - Takehiro Ishioka, Martin Lukac, Shinobu Nagayama:
Reducing the Cost of Clifford+T Quantum Gates. 104-109 - Shigeru Yamashita, Takashi Horiyama, Norihito Yasuda, Tatsuya Nakao:
Realizing 4-input Functions with the Minimum Toffoli Gate Count. 110-116 - Haruhiko Hasegawa, Masayuki Shimoda, Hiroki Nakahara, Takefumi Miyoshi:
A Novel Data Representation Towards Efficient FPGA-based Quantum Computer Simulation. 117-122 - Joshua Ange, Mason Tuller, Jessie M. Henderson, Elena R. Henderson, Bradley A. Moores, Duncan L. MacFarlane, Mitchell A. Thornton:
Modeling and Simulation of Multiple-Valued and Nonlinear Quantum Photonic Components. 123-128 - Can Aknesil, Elena Dubrova, Niklas Lindskog, Jakob Sternby, Håkan Englund:
Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks. 129-134 - Ruize Wang, Joel Gärtner, Elena Dubrova:
Decompressing Dilithium's Public Key with Fewer Signatures Using Side Channel Analysis. 135-140 - Yanning Ji, Elena Dubrova, Ruize Wang:
Is Your Chip Leaking Secrets via RF Signals? 141-146 - Elena Dubrova:
Solving AES-SAT Using Side-Channel Hints: A Practical Assessment. 147-152 - Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler, Martin Lukac:
Representation of Rotation Symmetric Multiple-Valued Functions Using Decision Diagrams. 153-159 - Tsutomu Sasao:
Linear Transformations for Iterative Reduction of Variables. 160-165 - Klaus Schneider, Nadine Kercher:
Normal Forms and Decompositions of Monotone Ternary Functions. 166-171 - Claudio Moraga, Radomir S. Stankovic, Milena Stankovic:
Additive Decomposition of Bent Functions. 172-177 - Saeideh Nabipour, Kamalika Datta, Lennart Weingarten, Abhoy Kole, Rolf Drechsler:
Multi-Input MAGIC Synthesis and Verification for In-Memory Computing Design. 178-183 - Mike Behrisch, Edith Vargas-García, Andreas Wachtel:
All minimal clones generated by {0, 1}-valued majority operations on a five-element set. 184-189 - Hajime Machida:
On 2-valued Majority Functions with their Relation to Minimal Clones. 190-195 - Michal Botur, Jan Paseka, Milan Lekár:
Foulis m-semilattices and their modules. 196-201 - Norihiro Kamide:
Cut Elimination and Normalization in Intermediate Connexive Logics. 202-207 - Norihiro Kamide:
Normalization Theorem for Extended Intuitionistic Belnap-Dunn Logic. 208-213 - D. Michael Miller:
On the Contributions to Multiple-Valued Logic by Prof. Kenneth C. Smith. 214-216 - Yosuke Iijima, Atsunori Okada, Yasushi Yuminaka:
Multi-Valued Data Transmission System Using Mild Waveform Shaping Based on Multi-Dimensional Symbol Mapping. 217-222 - Yasushi Yuminaka, Ryou Andachi, Haohao Zhang, Yosuke Iijima:
Visualization of the Waveform Shaping Effect of Higher-order FFEs Using Multi-Valued Symbol Mapping. 223-227
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