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ORCIDISOCC 2024: Sapporo, Japan
- 21st International SoC Design Conference, ISOCC 2024, Sapporo, Japan, August 19-22, 2024. IEEE 2024, ISBN 979-8-3503-7708-8
- Chan Park, Sohmyung Ha, Minkyu Je:
A High-Efficiency High-Data-Rate Wireless Power and Data Transfer IC Using Orthogonal Codes for Miniatureized Multi-Channel Neural Interface Systems. 1-3 - Ngoc Hung Nguyen, Duc Hong An Le, Vu Trung Duong Le, Van Tinh Nguyen, Tuan Hai Vu, Hoai Luan Pham, Yasuhiko Nakashima:
LI-RV: A Fast and Efficient RISC-V based Coprocessor for Lightweight Cryptography. 1-2 - Chen-Hua Chen, Guan-Yu Lai, Chuan Lee, Chang-Yu Wu, Kuan-Lin Liu, Shin-Chi Lai:
Design of a Multilingual Translation System with Personalized Voice Characteristics. 1-2 - Jae-Hyoun Park:
High Voltage Driver with Multiple Outputs Capable of Independent PWM Control. 1-2 - Kensuke Fukui, Shigeru Yamashita:
An Efficient Cost Reduction Method By Reusing Intermediate Droplets in MEDA Biochips. 1-2 - Kunpeng Li, Jong-Chul Lee:
Self-Supervised Contrastive Representation Learning for Time-Series Classification. 1-2 - Yen-Yun Huang, Po-Hung Chen:
Self-sustainable Triple-input Triple-output Power Management Unit for Battery-less IoT Application with Low-power Time-monitoring MPPT. 3-4 - Sungyoun Hwang, Hyoju Seo, Yongtae Kim:
Comparative Analysis of Quantum Adder Circuits in Computation Accuracy on Noisy Quantum Computers. 5-6 - Carl Lester Fabian, Marc D. Rosales, John Richard E. Hizon:
Interface Circuits for Piezoelectric Polyvinylidene Fluoride (PVDF) Films. 5-6 - Tzung-Je Lee, Han Yi Chiu:
A Cap-less LDO Regulator with Improved Load Regulation using Adaptive Feedback Control and Modified Voltage Damper. 9-10 - Pradyumna Vellanki, Hung-Che Tseng, Ying-Xuan Chen, L. S. S. Pavan Kumar Chodisetti
, Chua-Chin Wang:
An On-chip Temperature Sensor with 1°C Resolution And Wide Detection Range Using 180-nm CMOS Process. 11-12 - Tzung-Je Lee, Cheng-Han Wu:
Optimal Efficiency True Random Number Generator with Discrete-time Chaos for Low-Cost Applications. 15-16 - Soheila Khakneshin, Mehdi Saberi, Alexandre Schmid:
A High-Gain Transimpedance Amplifier Using Highly-Linear and Symmetric Multi-Stage Pseudo-Resistors. 19-20 - Junsei Oshika, Shogo Ishida, Daisuke Ito, Makoto Nakamura:
Compact Inductor-less CMOS PAM4 VCSEL Driver for High-speed Optical Communications. 21-22 - Yu-Chun Hsiao, Rui-Cheng Ai, Zhen-Jie Hong, Yu-Lung Lo, Jen-Chieh Liu:
A Low-power PLL with a Standby Mode. 23-24 - Changhoon Chae, Jongsun Kim:
A Fast-Lock All-Digital PLL with a TDC-based FLL. 25-26 - Shuan Yang, Tai-Hong Chen, Yu-Chi Wang, Chia-Hsi Fang, Chun-Yu Lin, Shan-Chih Tsou, Shon-Hang Wen, Kuan-Dar Chen, Tsung-Hsien Lin:
A 339-nW 32.768-kHz DFLL-Based Reference Clock Generator with an Embedded Temperature Sensor. 27-28 - Yu-Wei Huang, Cheng-En Wu, Wei-Bin Yang, Jen-Chieh Liu:
A Programmable DLL-based Delay Chain. 29-30 - Yoochang Kim, Seunghoon Yi, Seung Chae Jung, Hee-Cheol Joo, Sung-Chul Lee, Young-Ha Hwang:
A 12.8-Gb/s/lane, 1.03-pJ/b Transmitter With Reconfigurable Charge-Injecting Crosstalk Cancellation For Capacitively Coupled High-Density Interconnects. 31-32 - Yufeng Ge, Zheng Jiang, Yibin Fu, Yaolong Zhang, Jingbo Wang, Hong Zhang:
A 1.08pJ/bit DisplayPort RX with Combined AFE Offset Cancellation and Training-Less Link Setup. 33-34 - Jaewon Lee, Seoyoung Jang, Donggeon Kim, Yujin Choi, Sungyu Song, Gain Kim:
A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links. 35-36 - Seul-Ki Han, Won-Young Lee:
A Reference Voltage Generator Using Level Tracking Scheme for Low-Swing PAM-3 Signaling. 37-38 - Yujin Na, Jin-Ku Kang:
A 2.5-12.3 Gb/s continuous-rate referenceless CDR with counter-based unlimited frequency detection. 39-40 - Dong-Seob Shin, Jong-Ho Park, Changmin Song, Seong-Yun Kim, Hyeonseok Lee, Jinyeong Lee, Young-Chan Jang:
Clock Recovery Circuit for 3-Gsymbol/s/lane MIPI C-PHY Receiver. 45-46 - Thinh Nguyen-Viet, Gyung-Su Byun:
A High-Speed HBM Receiver Design for High-Performance Computing Systems. 47-48 - Jong-Ho Park, Minjun Cho, Juncheol Kim, Haewoon Son, Hyeon-Ho Kim, Young-Chan Jang:
3-Gsymbol/s/lane MIPI C-PHY Receiver with Feed-forward Level-dependent Equalization. 49-50 - Soumika Majumder, Lean Karlo Santos Tolentino, Oliver Lexter July Alvarez Jose, Venkata Naveen Kolakaluri, Mitch Ming-Chi Chou, Chua-Chin Wang:
A Multi-Level Power Gating Logic Controlled Driver for A 10-V Power Transistor Using 180-nm High Voltage BCD Process. 51-52 - Szu-Ting Wang, Shang-Sian Wu, Kuo-Cheng Tseng, Li-Chuan Hsu, Song-Min Ke, Shin-Chi Lai:
A LoRaWAN Enabled Sensor-Based System for Detecting Rodent Activity. 53-54 - Y. S. Chong, V. P. Nambiar, A. Mani, V. Leong, C. P. Y. Wong, A. T. Do:
Performance Evaluation of a RISC-V CPU at Cryogenic Temperature for Future Quantum Control. 67-68 - Chao-Yen Hsu, Mu-Heng Pi, Tai-Cheng Lee:
An 800-MS/s 10b Pipelined ADC with Floating Ring Amplifiers. 69-70 - Wonseon Lee, Youngcheol Chae:
Power Reduction Techniques for Energy-Efficient Audio Continuous-Time Delta-Sigma Modulator. 71-72 - Ting-Yu Syu, Yin-Qin Ye, Hsin-Liang Chen, Hsiao-Hsing Chou, Jen-Shiun Chiang:
An Integrator Time-Constant Calibration Scheme with Modified Voltage to Digital Converter. 73-74 - Jihun Choi, Sangwook Na, Taehun Kim, Jeongjin Roh:
A Robust DT ∆Σ Modulator for High-Resolution Sensor Against Temperature Variations. 75-76 - Wonseok Heo, Hoyong Seong, Donghyun Youn, Minkyu Je, Sohmyung Ha:
An Energy Efficient Period-modulation-based Current-to-digital Converter for FET-type Sensors. 77-78 - Chenxu Zhao, Mengchu Fang, Toshihiko Yoshimasu:
A 14-GHz-Band Low-Supply-Voltage Low-Phase-Noise LC-VCO IC with Harmonic Tuned LC Tank in 45-nm CMOS SOI. 79-80 - Chia-Chia Wang, Yue-Fang Kuo:
5GHz Automatic Amplitude Calibration VCO Using Synchronous Clock Temperature Compensation. 81-82 - Zhewen Wei, Toshihiko Yoshimasu:
A 38-GHz Stacked-FET Linear Power Amplifier with Novel Phase Linearizer Circuit in 45-nm CMOS SOI. 85-86 - Donald Y. C. Lie, Liang-Wei Ouyang, Clint Sweeney, Jill C. Mayeda, Jerry Lopez:
5G Millimeter-Wave RF Front-End Module ICs Design in Silicon CMOS SOI vs. GaN. 87-88 - Vishnu P. Nambiar, Y. S. Chong, Thilini Kaushalya Bandara, Dhananjaya Wijerathne, Z. Li, Rohan Juneja, Li-Shiuan Peh, Tulika Mitra, A. T. Do:
A 360 GOPS/W CGRA in a RISC-V SoC with Multi-Hop Routers and Idle-State Instructions for Edge Computing Applications. 89-90 - Y. S. Chong, U. Jana, S. Y. Soh, V. P. Nambiar, W. L. Goh, B. Wang, A. T. Do:
Lookup Table and Neural Network Based Decoders for Real Time Quantum Error Correction. 91-92 - Pham Hoai Luan, Vu Trung Duong Le, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima:
CGLA: Coarse-Grained Linear Array for Multi-Hash Acceleration in Blockchain Mining. 93-94 - Vu Trung Duong Le, Hoai Luan Pham, Tuan Hai Vu, Van Duy Tran, Thi Diem Tran, Yasuhiko Nakashima:
UCP: A Unified Cryptographic Processor for High Performance and Low Power Security Applications. 95-96 - Hyeri Roh, Woo-Seok Choi:
Constructing Hardware Accelerators for Number-Theoretic Transform Using High-Level Synthesis. 97-98 - Jaehun Jung, Jin-Hyeong Park, Young-Gil Jeong, Jeongwoo Park:
MHC : Multi-flit HBM Crossbar with Enhancing Performance and Resource Utilization. 99-100 - Yoojin Kim, Yesin Ryu, Jungrae Kim:
LEAP: LLW RowHammer Mitigation System. 101-102 - Duc Hong An Le, Vu Trung Duong Le, Viet Anh Ho, Van Tinh Nguyen, Hoai Luan Pham, Van Duy Tran, Tuan Hai Vu, Yasuhiko Nakashima:
High-Efficiency RISC-V-Based Cryptographic Coprocessor for Security Applications. 103-104 - Chanyung Kim, Eunchong Lee, Kyungho Kim, Sung-Joon Jang, Sang-Seol Lee:
A Simple Up-and-Down Weight Update Method for Tiny 8-bit Quantized CNN Training. 109-110 - Yiwen Peng, Gexuan Wu, Lei Huang, Bing Li:
Hybrid CC-LSTM Algorithm for SOC Estimation and Its Dual-Mode Hardware Design. 113-114 - Mahendra Kumar Gurve, Gaurav Kumar, Sankar Behera, Yamuna Prasad, Satyadev Ahlawat:
On Exploring Non-negative Matrix Factorization for Deep Neural Network Compression. 115-116 - Sunjoo Whang, Soyeon Um, Sangwoo Ha, Hoi-Jun Yoo:
A Software-Hardware Co-Optimized Sense Amplifier for 2T1C Cell-based DRAM In-Memory-Computing. 117-118 - Edward Jongyoon Choi, Jiho Chun, Byeongseon Choi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je:
An SRAM-based Error-Free Time Domain Pulse Train Computing-In-Memory Macro achieving 226.14 TOPS/W and 5.782 TOPS/mm2. 119-120 - Vu Tuan Hai, Vo Minh Kiet, Vu Trung Duong Le, Pham Hoai Luan, Le Bin Ho, Yasuhiko Nakashima:
Quantum Battery Optimization through Quantum Machine Learning Techniques. 121-122 - Jungbeom Ko, JaeYun Park, Minjeong Kim, Soomi Jeong, Hyunchul Kim, Jungsuk Kim:
Efficient Cardiovascular Disease Diagnosis System for an Wearable Device based on Multi Stage BCResNet. 123-124 - Lih-Yih Chiou, Yu-Hung Lee, Chung-Chieh Chiu, Shun-Hsiu Hsu:
An Effective Neural Network Model Protection Method Against Model Stealing Attacks for Image Classification Applications. 125-126 - Seohyun Kim, Gangmin Cho, Shilong Zhang, Youngsoo Shin:
Fast and Accurate Curvilinear OPC with ML-Guided Curve Correction. 127-128 - Yen-Lin Chua, Meng-Shan Wu, Yu-Guang Chen:
CARDS: A Novel Detailed Macro Placement Framework for Minimizing Wirelength. 131-132 - Yu-Guang Chen, Hung-Han Chang, Yu-Chuan Liang, Wen-Hsiang Chang, I-Ching Tsai, Chih-Wei Lin, Yun-Chih Chang, Mango Chia-Tso Chao:
IR-drop and Routing Congestion Aware PDN Refinement Framework for Timing Optimization. 133-134 - Yongchan James Ban, Gangsic Kim, Hosoon Shin:
Optimizing and Addressing Stitch Challenges in High-NA EUV Lithography for Large Die Designs. 135-136 - Seung-Mo Noh, Kee-Won Kwon:
An Invariant Interconnect Delay Monitoring Circuit for 3D System Scaling. 137-138 - André Lucas Chinazzo, Norbert Wehn, Sani R. Nassif:
Enabling cell selection optimization for non-traditional CMOS topologies. 139-140 - Jiho Lee, Jieui Kang, Eunjin Lee, Yejin Lee, Jaehyeong Sim:
AlphaAccelerator: An Automatic Neural FPGA Accelerator Design Framework Based on GNNs. 143-144 - Atsushi Ooka, Kazunari Inoue, Takaya Miyazawa:
An Embedded core of Content-based maskable CAM exploring Longest Prefix Match fashion. 145-146 - Seunjae Shin, Yeong Min Jang, Jinho Jeong:
D-band Low Noise Amplifier with Improved Linearity in 90-nm BiCMOS9HP Process. 149-150 - Seungmin Kang, Sangwan Kim, Sihyun Kim:
Write Bias Scheme Optimization of Ferroelectric Field-Effect-Transistor (FeFET) Synapse for Accurate On-chip Training. 153-154 - Sihyung Kim, Seokin Hong:
Leveraging Algorithm-based Fault Tolerance for Propagation Error Detection in NPUs. 157-158 - Hanyoung Lee, Hanho Lee:
Automorphism Architecture for Bootstrapping Homomorphic Encryption. 159-160 - Novi Prihatiningrum, Jungu Kang, Chanyeong Choi, Yeongkyo Seo:
Design of an Area-Efficient and Error-Reduced CMOS Approximate Adder. 161-162 - Sua Kim, Jin-Ku Kang:
A 12-28 Gb/s Temperature Compensated PAM-4 Transmitter with 7B4Q Maximum Transition Avoidance and Fractional-Spaced FFE. 163-164 - Akshay Kumar Sharma, Kyung Ki Kim:
Enhanced Image Classification through Layer-Wise Feature Concatenation in Deep Neural Networks. 165-166 - Jiwon Lee, Hyeonjun Cheon, Ho-Sung Lee, Ik-Hyeon Jeon, Joo-Hyung Chae:
Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed. 167-169 - Hyeonjun Cheon, Ho-Sung Lee, Jiwon Lee, Ik-Hyeon Jeon, Joo-Hyung Chae:
A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes. 169-170 - Beom Jin Kang, Nam Joon Kim, Hyun Kim:
Hardware-aware Network Compression for Hybrid Vision Transformer via Low-Rank Approximation. 171-172 - Jungkook Jo, Jaehoon Jun:
A Low-Noise Capacitively-Coupled Chopper Instrumentation Amplifier with SAR-Assisted Low Current Ripple Reduction Technique. 173-174 - Jiho Park, Geon Shin, Hoyoung Yoo:
Implementation of Activation Functions using various approximation methods. 175-176 - Shin-Uk Kang, Seung-Mo Jin, Min-Gwon Song, Dong-Hyun Lee, Woo-Suk Jung, Min-Seong Choo:
A 2T1C eDRAM-based Compute-In-Memory Macro with 8-to-l Column Multiplexing Scheme for Highly Sparse Binarized Deep Neural Networks. 177-178 - Kyungmi Kim, Soeun Choi, Eunkyeol Hong, Yoonseo Jang, Jaehyeong Sim:
An Energy-Efficient Hardware Accelerator for On-Device Inference of YOLOX. 179-180 - Kwanghyun Koo, Hyun Kim:
FB-SKP: Front-Back Structured Kernel Pruning via Group Convolution without Increasing Memory. 181-182 - Jin-Won Hyun, Dana Kim, Kyung-Sik Choi, Jae-Won Nam:
AI-Assisted Design Automation of Circular and Asymmetric Inductor in CMOS Technology. 183-184 - Jinyeol Kim, Raehyeong Kim, Jongwon Oh, Seung Eun Lee:
Accelerating Embedded WebAssembly Based on FPGA. 187-188 - Rikuu Hasegawa, Kazuki Monta, Takuya Wadatsumi, Takuji Miki, Makoto Nagata, Lang Lin, Akhilesh Kumar, Norman Chang:
Si-Backside Side-Channel Leakage Measurement and Simulation. 189-190 - Atsushi Hasegawa, Makoto Ikeda, Ichiro Naka, Kunio Uchiyama:
SoC Platform for Heterogeneous Accelerator IPs SoC development platform for evaluation and demonstration. 191-192 - Sangjin Kim, Hoi-Jun Yoo:
Opportunities and Challenges of DRAM-based Computing-in-Memory for AI Accelerator. 193-194 - Man Ni, Gabriela Mogos:
Botnet Classification using Machine Learning. 197-198 - Tso-Bing Juang, Huang-Sen Chiu:
Design of Automatic Generators for Fibonacci Q- matrix based Encryption/Decryption Circuits. 199-200 - Ningfei Song, Nanlin Jin, Jingchen Wang, Jie Zhang, Ka Lok Man, Jeremy S. Smith, Yutao Yue:
State of Charge Estimation for Lithium-Ion Batteries Based on Informer-LSTM Hybrid Network. 201-202 - Xiaozhe Ji, Jingchen Wang, Ka Lok Man, Eng Gee Lim, Yutao Yue, Jiafeng Zhou:
Designs of Dual-band Metamaterials for Near-field Wireless Power Transmission. 203-204 - Gianfranco Avitabile, Ka Lok Man, Claudio Talarico:
DDS-PLL Architecture for Adaptive Beam Steering. 205-206 - Gianfranco Avitabile, Marco Rossano, Ka Lok Man:
Low-Cost Dual-Band Active Transponder for SAR Satellites Calibration. 207-208 - Sota Ohtaki, Hiroyuki Torikai:
A small and low power ergodic sequential logic neuron model for neural prostheses. 209-210 - Masaki Fujita, Yoko Uwate, Yoshifumi Nishio:
Effect of Mutual Information on Chaotic Attractor Classification Accuracy Using Neural Network. 209-210 - Rintaro Kaneiso, Ayano Komanaka, Yinchen Xie, Yutaro Komiyama, Akihiro Konishi, Kien Nguyen, Hiroo Sekiya:
Design of Resonant Converter with Genetic- Algorithm Optimization. 211-212 - Masayuki Shimoda, Atsushi Takahashi:
Wirelength Minimization by Gap Swap-Flip in Gridless Gap Channel Routing. 213-214 - Ihara Ayase, Yoko Uwate, Yoshifumi Nishio:
Study on Reservoir Computing Combining Chaotic Circuits and Periodic Oscillators. 215-216 - Yasufumi Kajino, Yoko Uwate, Yoshifumi Nishio:
Waveform Classification by Two-Layer Reservoir Computing with van der Pol Oscillators. 217-218 - Zhicheng Hu, Liang Chang:
Enhancing Embedded Super-Resolution Accelerators: Techniques for Hardware Performance Improvement. 222-223 - Jinhong Ahn, Silin Chen, Junwei Feng, Hyunseung Lee, Junbeom Park, Hyoungjoon Kim, Jerald Yoo:
Real-Time Ultrasound Imaging System for Drone and Robotic Applications. 224-225 - Kohei Suzue, Yoko Uwate, Yoshifumi Nishio:
Effect of Coupling Strength on Synchronization Phenomena in Chaotic Circuits with Unidirectional Coupling. 226-227 - Rikuto Nozu, Hiroyuki Torikai:
Analysis of the synchronization performance of wireless functional electronic stimulation central pattern generator. 228-229 - Haruto Ota, Jiaying Lin, Ryuji Nagazawa, Kien Nguyen, Hiroo Sekiya, Won-Joo Hwang:
Implementation of Wireless Spiking Neural Network for Classifications on MNIST Dataset. 230-231 - Taishi Segawa, Yoko Uwate, Yoshifumi Nishio:
Switching Phenomena by Adding a Memristor to a Chaos Circuit. 232-233 - Yukinojo Kotani, Yoko Uwate, Yoshifumi Nishio:
Synchronization Phenomena in Coupled van der Pol Oscillators with Memristor Couplings as Ladder Structure. 234-235 - Taehyun Kim, Junmo Yang, Chungmo Yang, Sung-Hoon Choa, Hee Yeoun Kim:
Wafer-level Packaging Platform for MEMS Sensor Applications. 238-239 - Luepol Pipanmekaporn, Suwatchai Kamonsantiroj, Ruslee Sutthaweekul, Wilaiporn Lee, Kanabadee Srisomboon:
Smartphone-based Road Condition Sensing using Machine Learning techniques. 246-247 - Wilaiporn Lee, Kanabadee Srisomboon:
Rank Reversal Avoiding Algorithm for Modern Cooperative Spectrum Sensing. 248-249 - Wilaiporn Lee, Cattareeya Suwanasri, Luepol Pipanmekaporn, Kanabadee Srisomboon:
Machine Learning for Indoor Localization using CSI Technique. 250-251 - Kallaya Songklang, Kanabadee Srisomboon, Wilaiporn Lee, Akara Prayote:
Enhancing Event Extraction and Impact Analysis with Knowledge Graph Augmented Transformer. 252-253 - Pattarapon Klaykul, Akara Prayote, Wilaiporn Lee:
A New Service Time Framework for Expressway Toll Lane Capacity Model. 254-255 - Jettasic Popun, Wilaiporn Lee, Akara Prayote:
Automatic Speech Recognition Techniques for Transcription of Thai Traditional Medicine Texts. 256-257 - Watcharet Kuntichod, Wilaiporn Lee, Akara Prayote:
Unseen Named Entity Recognition for Thai Language. 258-259 - Adisorn Kheaksong, Wilaiporn Lee, Kanabadee Srisomboon:
Enhancing Multi-parent Selection Algorithm Exploiting MPTCP Protocol. 260-261 - Jiann-Chyi Rau, Wei-Bin Yang, Yu-Lung Lo, Chin-Yuan Shih, Cheng-Kai Lin, Che-Chia Chuang:
A Hierarchical Tree-Structured Control Digital Low Drop-out Regulator with Status-Dumping Mechanism. 262-263 - Minho Seo, Hongil Yoon:
A bandgap reference with low TC of 1.363ppm/°C across wide temperature range for PMICs. 264-265 - Hyunwook Lee, Hee-Cheol Joo, Seung Chae Jung, Seunghoon Yi, Young-Ha Hwang:
An All-Digital Standard-Cell-Based Resistive-Sensing Display Panel/Chip Crack Detector. 268-269 - Daisuke Ito, Masataka Furuta, Yasuhiro Takahashi, Makoto Nakamura:
Power-efficiency estimation of exponential horn driver circuit for low-power optical link. 274-275 - Dohyun Shin, Jonghyun Kim, Jinwook Burm:
Phase Locked Loop with Ramp Generator for FMCW LiDAR TX in 28-nm CMOS. 276-277 - Xinye Gu, Mingyi Chen:
A DLL-Based Three-Step Time-to-Digital Converter for Time-of-Flight Applications. 278-277 - Hsiang-Kai Teng, Shi-Yu Huang:
A Resilient All-Digital PLL Using Ping-Pong Delay Line. 280-281 - Tzung-Je Lee, Po-Hsuan Hsiao:
Low-Power Frequency-Mode Temperature Sensing Circuit with Subthreshold Operational Amplifier. 284-285 - Juwon Ham, Wooseok Jang, Hamin Lee, Sangweun Kim, Dabin Yun, Junseong Kim, Seunghoon Ko:
Reconfigurable Gaussian filtering TSP readout circuit for Flexible AMOLED Display. 288-289 - Donghyun Han, Sunghoon Kim, Sungho Kang:
Signal Shifting-based Reusable Redundant TSV Structure for Infrastructure TSV. 290-291 - Ikkyum Kim, Heechun Park:
3T1R Memristor Crossbar Architecture for Diverse Logic Implementation. 292-293 - Suzuki Koki, Shigeru Yamashita:
An Efficient Error Correction Method for DMFBs with Node Redundancy Considering Node Levels. 294-295 - Youngmin Cho, Jinwook Burm:
Calibrating the Dark Count Rate of Single Photon Avalanche Diodes Using Linear Regression. 296-297 - Donghui Lee, Yongtae Kim:
Design of a Low-Cost Stochastic Computing-based Median Filter for Digital Image Processing. 298-299 - S. Kumar, V. Kumar, A. Antonyan, B. Prickett, U. K. Bobbili, D. Chakraborty, D. Nguyen, S. Sharma, H. Harshul, A. Dang:
22/16nm High Speed and Area Efficient Automotive Grade STT-MRAM Memory Compiler for 2~128Mb. 302-303 - Jiapei Zheng, Xinkai Nie, Zhenghang Zhi, Zhidong Tang, Qi Liu, Xufeng Kou, Chixiao Chen:
A 28-nm 10.4-fJ/b Cryogenic embedded DRAM with 3T1C Gain Cell and MBIST at 4-Kelvin. 306-307 - Nhat Nguyen Dinh, Hoai Luan Pham, Vu Trung Duong Le, Tuan Hai Vu, Van Duy Tran, Yasuhiko Nakashima:
Kyberator: A High-Efficiency FPGA-Based Multi-Mode CRYSTALS-Kyber Accelerator for Quantum-Resistant Security Applications. 308-309 - Binh Kieu-Do-Nguyen, Khai-Duy Nguyen, Nguyen The Binh, Tuan-Kiet Dang, Duc-Hung Le, Cuong Pham-Quoc, Ngoc-Thinh Tran, Cong-Kha Pham, Trong-Thuc Hoang:
A Resource-Efficient Multi-core Multi-thread RISC-V-based System-on-Chip. 310-311 - Seung Ho Shin, Youngki Moon, Byungsoo Kim, Sungho Kang:
Effective Data-Width Aware ECC Scheme for HBM. 316-317 - Jeongwon Choe, Youngjoo Lee:
Cost-Efficient Partially-Parallel LDPC Decoder Architecture for 50G-PON Standard. 318-319 - Soyoung Park, Jungrae Kim:
Evaluating the Impact of In-band ECC on GPU Performance. 320-321 - Cheol-Ho Choi, Jeongwoo Cha, Joonhwan Han, Hyunmin Choi, Jungho Shin:
Improved Contrast Enhancement Algorithm for Night Vision Systems using Thermal Camera. 322-323 - Yuhui Liu, Taosong Zhao, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
FPGA Design of a Masked AES Circuit with PPRM-based S-Box. 328-329 - Soudabeh Mousavi, Dara Rahmati, Saeid Gorgin, Jeong-A Lee:
Enhancing Efficiency in Computational Intensive Domains via Redundant Residue Number Systems. 330-331 - Sangmuk Lee, Jongseung Lee, Jeong-Ho Woo, Jinhong Park:
Design of a 3D-IC based AI-Vision SoC. 332-333 - Esha Muzammal, Saransh Rajjarwal, Min-Chae Kim, Gyung-Su Byun:
Analysis and Design of CRC-based SENT Interface for Future Automotive Applications. 334-335 - Xiangyu Li, Hiroki Nishikawa, Xiangbo Kong, Hiroyuki Tomiyama:
An Approximate Multiplier Design Based on Mitchell's Algorithm. 336-337 - Friedrich Pauls, Sebastian Haas, Yogesh Verma:
Integration of IP-Cores for the M3 Architecture with Low Area Overhead: Accelerator Support Module. 340-341 - Hojin Sung, Yeonjoo Nam, Woong Choi:
PEMAC: A Posit EM AC with LDD and Logarithm Approximation. 342-343 - Jongwon Oh, Raehyeong Kim, Jinyeol Kim, Seung Eun Lee:
On-Device Eye Tracking System with Dual Lightweight AI Processor. 344-345 - Hyunjae Park, Jin-Ku Kang, Yongwoo Kim:
The hardware implementation of QARMA-64 with RoCC on FPGA for memory encryption. 346-347 - Wai Yie Leong, Yuan Zhi Leong, Wai San Leong:
System-on-Chip iot for Smart Poultry Manufacturing. 348-349 - Snehit Chunarkar, Samba Raju Chiluveru:
Efficient Hardware Implementation of Nonlinear Activation Function For Inference Model. 350-351 - Keerthana Pamidimukkala, Kyung Ki Kim, Yong-Bin Kim, Minsu Choi:
A Novel Area Efficient Approximate Stochastic Computing Approach for Edge Devices. 352-353 - Aeri Kim, Yumi Kim, Eunchong Lee, Minkyu Lee, Sang-Seol Lee:
A Fully 4-bit Quantized MobileNet-SSD. 354-355 - Eunseo Kim, Subean Lee, Chaeyun Kim, HaYoung Lim, Jimin Nam, Jaehyeong Sim:
BS2: Bit-Serial Architecture Exploiting Weight Bit Sparsity for Efficient Deep Learning Acceleration. 356-357 - Abhishek Yadav, Masahiro Fujita, Binod Kumar:
Resource-efficient DL Model Inference with Weight Clustering and Zero-skipping. 358-359 - Lih-Yih Chiou, Hong-Ming Shih, Shun-Hsiu Hsu, Tzung-Jin Tsai:
Fast Performance and Power Profiler for SRAM Compute-in-Memory-based Accelerators. 360-361 - Ian Christian Fernandez, Percival Magpantay, Marc D. Rosales, John Richard E. Hizon:
Simplified Real-time Categorized Vehicle Counting and Speed Estimation. 362-363 - Gil-Ho Kwak, Tae-Hwan Kim:
Error-Resilient Binary Neural Network Inference with Selective Recompute-Based Error Correction. 364-365 - Ying-Hsiu Hung, Yen-Ching Chang, Shin-Chi Lai, Wen-Ho Juang, Ming-Hwa Sheu, Jeng-Dao Lee:
Integrating Noise Classification and Speech Enhancement Model for Hearing Aids. 368-369 - Kyou-Jung Son, Seokhun Jeon, Byung-Soo Kim:
Integrating CNN and RCE Networks for Efficient On-Device Image Classification. 370-371 - Jaehyeon So, Jong Hwan Ko:
A Hybrid Precision Network with Efficient Processing Elements for 3D Hand Pose Estimation. 372-373 - Eunchong Lee, Sang-Seol Lee, Minkyu Lee, Kyungho Kim, Sung-Joon Jang:
Strategic Improvements in CNN Accelerators: Optimizing PE Utilization for MobileNetV2. 374-375 - Yugwon Seo, Jin-Ku Kang, Yongwoo Kim:
Autoencoder-based Knowledge Distillation For Quantized YOLO Detector. 376-377 - Johnny Rhe, Jong Hwan Ko:
Row-Efficient Pruning for In-Memory Convolutional Weight Mapping. 378-379 - Sanghyun Kim, Kyungho Kim, Yumi Kim, Aeri Kim, Sung-Joon Jang:
An Im2col Architecture Using The Benes Network For Deep Learning Hardware Accelerators. 380-381 - Juhong Park, Jong Hwan Ko:
C-AFA: A Conditionally Approximate Full Adder for Efficient DNN Inference in CIM Arrays. 382-383 - Abhishek Yadav, Masahiro Fujita, Binod Kumar:
Lightweight DL-based Drone Image Classification for Surveillance Applications. 386-387 - Mao-Hsiu Hsu, Sheng-Lyang Jang, Meng-Ting Lin, Wen-Cheng Lai, Miin-Horng Juang:
Differential Injection-Locked Frequency Tripler with a Low-coupling 8-shaped Transformer. 388-389 - Amrita Rana, Kyung Ki Kim:
Tailoring Backbone Architectures for SSD. 388-389 - Longfan Li, Chao Wang, Wangzilu Lu, Yuhang Zhang, Leilai Shao, Yanan Sun, Jian Zhao, Yongfu Li:
LogicEdu: Enhancing Computational Logic Understanding through Web-Based Boolean Logic Simplification Tool. 390-391 - Sijin Jang, Gunwoo Jeong, Hwayoung Jeong, Hyunchol Shin:
A 60 GHz CMOS OOK Receiver with 7.7 GHz Bandwidth for Wireless Proximity Communication. 392-393 - Juyong Lee, Sooryeong Lee, Hayoung Lee, Sungho Kang:
Scan Architecture with Data Observation for Multiple Scan Cell Fault Diagnosis. 392-393 - Yoonyul Yoo, Jungrae Kim:
INC: In channel Crossing ECC for LPDDR Compression Attached Memory Module. 394-395 - Sooryeong Lee, Hayoung Lee, Juyong Lee, Sungho Kang:
APAPG: Address Pre-Processed ALPG for High-Speed Linear Test. 396-397 - T. Sukapan, P. Tambanjong, R. Sutthaweekul, Pisit Vanichchanunt, Sukritta Paripurana, W. Saelee, A. Marindra:
Low-cost SDR-based Reader for Chipless Sensor Tag. 396-397 - Adam Górski, Maciej Ogorzalek:
Detecting and assignment of unexpected tasks in SoC design process using genetic programming. 398-399 - Jan Lappas, Norbert Wehn, Sani R. Nassif:
Timing Analysis with Analytical Sensitivity. 400-401 - Yoonjae Lee, Heechun Park:
Double-Row Flip-flop Design Under Advanced Technology and Its IC-Level Effects. 402-403 - Seokmin Park, Jewoo Park, Young-Woo Lee:
Optimized Instruction Set Architecture for Programmable Memory Test Pattern Generation. 404-405 - Daseul Moon, Jisoo Lee, Woong Choi:
Optimized Multiplier Architecture: Integrating Det/Pre-Encoder and Compound Gate. 406-407 - Jaehwan Shin, Young-Woo Lee:
Production-Oriented Design for High Parallel Test Efficiency. 410-411 - Gokul T, Ajay B. S, Raveendranathreddy P:
High Quality Power-Aware Verification of Mixed Signal designs using UPF checkers. 422-423 - Minjeong Kim, Taehoon Kim, Woo-Seok Choi:
Device Parameter Extraction Method for Training Performance Predicting Models. 424-425 - Yunseong Jo, Hyuntae Kim, Jaeduk Han:
Analysis of Test Environment Configuration for High-Speed Link Chip Measurement. 430-431 - Seoyoung Jang, Jaewon Lee, Yujin Choi, Donggeon Kim, Gain Kim:
A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links. 432-433
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