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ORCIDISPD 2014: Petaluma, CA, USA
- Cliff C. N. Sze, Azadeh Davoodi:
International Symposium on Physical Design, ISPD'14, Petaluma, CA, USA, March 30 - April 02, 2014. ACM 2014, ISBN 978-1-4503-2592-9
Welcome and Monday keynote address
- Serge Leef:
Hardware cyber security. 1-2
Placement
- Wing-Kai Chow, Jian Kuang, Xu He, Wenzan Cai, Evangeline F. Y. Young:
Cell density-driven detailed placement with displacement constraint. 3-10 - Shuai Li, Cheng-Kok Koh:
MIP-based detailed placer for mixed-size circuits. 11-18 - Wen-Hao Liu, Tzu-Kai Chien, Ting-Chi Wang:
A study on unroutable placement recognition. 19-26 - Anand Arunachalam:
Integrated structured placement design methodology in place and route flow. 27-28
Routing
- Yilin Zhang, David Z. Pan:
Timing-driven, over-the-block rectilinear steiner tree construction with pre-buffering and slew constraints. 29-36 - Stephan Held, Sophie Theresa Spirkl:
A fast algorithm for rectilinear steiner trees with length restrictions on obstacles. 37-44 - Rajat Aggarwal:
FPGA place & route challenges. 45-46
3D integration
- Shreepad Panth, Kambiz Samadi, Yang Du, Sung Kyu Lim
:
Placement-driven partitioning for congestion mitigation in monolithic 3D IC designs. 47-54 - Caleb Serafy, Ankur Srivastava:
Coupling-aware force driven placement of TSVs and shields in 3D-IC layouts. 55-62 - William Wu Shen:
3DIC system design impact, challenge and solutions. 63-64
Keynote address
- Robert C. Aitken, Greg Yeric, Brian Cline, Saurabh Sinha, Lucian Shifren, Imran Iqbal, Vikas Chandra:
Physical design and FinFETs. 65-68
Clocking and power-grid planning
- Subhendu Roy, Pavlos M. Mattheakis, Laurent Masse-Navette, David Z. Pan:
Clock tree resynthesis for multi-corner multi-mode timing closure. 69-76 - Shih-Chuan Lo, Chih-Cheng Hsu, Mark Po-Hung Lin:
Power optimization for clock network with clock gate cloning and flip-flop merging. 77-84 - Jai-Ming Lin, Che-Chun Lin, Zong-Wei Syu, Chih-Chung Tsai, Kevin Huang:
Current density aware power switch placement algorithm for power gating designs. 85-92 - Chia-Tung Ho, Yu-Min Lee, Shu-Han Wei, Liang-Chia Cheng:
Incremental transient simulation of power grid. 93-100
DFM
- Xiaoqing Xu, Brian Cline, Greg Yeric, Bei Yu, David Z. Pan:
Self-aligned double patterning aware pin access and standard cell layout co-optimization. 101-108 - Jian Kuang, Evangeline F. Y. Young:
A highly-efficient row-structure stencil planning approach for e-beam lithography with overlapped characters. 109-116 - Subhasish Mitra:
Carbon nanotube computer: transforming scientific discoveries into working systems. 117-118
Commemoration for Dr. Bryan Preas
- Michael J. Lorenzetti:
Making a difference in EDA: a thank you to Bryan Preas for his contributions to the profession. 119-120 - Jason Cong:
From design to design automation. 121-126 - Massoud Pedram:
Interconnect length estimation in VLSI designs: a retrospective. 127-128 - Scott Elrod:
Bryan Preas: broad contributions to system engineering in the 2000's. 129-130 - Bryan Preas:
Smart matter systems, an introduction through examples. 131-132
CAD for cyber physical systems
- Shang-Tsung Yu, Sheng-Han Yeh, Tsung-Yi Ho:
Reliability-driven chip-level design for high-frequency digital microfluidic biochips. 133-140 - Qi Zhu, Peng Deng:
Design synthesis and optimization for automotive embedded systems. 141-148 - Gi-Joon Nam, Sani R. Nassif:
Opportunities in power distribution network system optimization: from EDA perspective. 149-150 - Fan Ye:
Indoor localization technology and algorithm issues. 151-152
Contest
- Jin Hu, Debjit Sinha, Igor Keller:
TAU 2014 contest on removing common path pessimism during timing analysis. 153-160 - Vladimir Yutsis, Ismail Bustany, David G. Chinnery, Joseph R. Shinnerl, Wen-Hao Liu:
ISPD 2014 benchmarks with sub-45nm technology rules for detailed-routing-driven placement. 161-168
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