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ORCIDISSCC 2006: San Francisco, CA, USA
- 2006 IEEE International Solid State Circuits Conference, ISSCC 2006, Digest of Technical Papers, an Francisco, CA, USA, February 6-9, 2006. IEEE 2006, ISBN 1-4244-0079-1
- Tze-Chiang Chen:
Where CMOS is going: trendy hype vs. real technology. 1-18 - Hermann Eul:
ICs for mobile multimedia communications. 21-39 - Ken Kutaragi:
Toward Future Computer Entertainment Systems. 40-56 - Marcin K. Augustyniak, Christian Paulus, Ralf Brederlow
, N. Persike, Gerhard Hartwich, Doris Schmitt-Landsiedel, Roland Thewes:
A 24x16 CMOS-Based Chronocoulometric DNA Microarray. 59-68 - Claudio Stagni, D. Esposti, Carlotta Guiducci, Christian Paulus, Meinrad Schienle, Marcin K. Augustyniak, Giampaolo Zuccheri, Bruno Samorì, Luca Benini, Bruno Riccò, Roland Thewes:
Fully Electronic CMOS DNA Detection Array Based on Capacitance Measurement with On-Chip Analog-to-Digital Conversion. 69-78 - Pamela T. Bhatti, Sangwoo Lee, Kensall D. Wise:
A 32-Site 4-Channel Cochlear Electrode Array. 79-88 - Maurits Ortmanns, N. Unger, André Rocke, Marcus Gehrke, H. J. Tietdke:
A 0.1mm2, Digitally Programmable Nerve Stimulation Pad Cell with High-Voltage Capability for a Retinal Implant. 89-98 - Luke Theogarajan, John Wyatt, Joseph Rizzo, Bill Drohan, Mariana T. Markova, Shawn K. Kelly, Greg Swider, Milan Raj, Douglas B. Shire, Marcus D. Gingerich, John Lowenstein, Barry Yomtov:
Minimally Invasive Retinal Prosthesis. 99-108 - Refet Firat Yazicioglu, Patrick Merken, Robert Puers, Chris Van Hoof:
A 60µW 60 nV/Hz Readout Front-End for Portable Biopotential Acquisition Systems. 109-118 - Honglei Wu, Yong Ping Xu:
A 1V 2.3µW Biomedical Signal Acquisition IC. 119-128 - Gerhard Mitteregger, Christian Ebner, Stephan Mechnig, Thomas Blon, Christophe Holuigue, E. Romani, Andrea Melodia, V. Melini:
A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOB. 131-140 - Richard Schreier, Nazmy Abaskharoun, Hajime Shibata, Iuri Mehr, Steve Rose, Donald Paterson:
A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHz. 141-150 - Paulo G. R. Silva, Lucien J. Breems, Kofi A. A. Makinwa, Raf Roovers, Johan H. Huijsing:
An 118dB DR CT IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio Receivers. 151-160 - Sunwoo Kwon, Franco Maloberti:
A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+. 161-170 - Kye-Shin Lee, Sunwoo Kwon, Franco Maloberti:
A 5.4mW 2-Channel Time-Interleaved Multi-bit ΔΣ Modulator with 80dB SNR and 85dB DR for ADSL. 171-180 - Kong-Pang Pun, Shouri Chatterjee, Peter R. Kinget:
A 0.5V 74dB SNDR 25kHz CT ΔΣ Modulator with Return-to-Open DAC. 181-190 - João Goes, Bruno Vaz, Rui Monteiro, Nuno Paulino:
A 0.9V ΔΣ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase Technique. 191-200 - Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo Ré, Masayuki Miyamoto:
An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV Receivers. 201-210 - Mounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, Woogeun Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, Aichin Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman:
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS. 213-222 - Koon-Lun Jackie Wong, Chih-Kong Ken Yang:
A Serial-Link Transceiver with Transition Equalization. 223-232 - Yongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim:
A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time Control. 233-242 - Mark Callicotte, James Little, Hiroshi Takatori, Ken Dyer, Chien-Hsin Lee:
A 12.5Gb/s Single-Chip Transceiver for UTP Cables in 0.13µm CMOS. 243-252 - Edoardo Prete, Dirk Scheideler, Anthony Sanders:
A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory Interfaces. 253-262 - Bryan Casper, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, K. Canagasaby, Joseph T. Kennedy, E. Yeung, Randy Mooney:
A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS B. 263-272 - Jri Lee:
A 20Gb/s Adaptive Equalizer in 0.13µm CMOS Technology. 273-282 - Jintae Kim, Hamid Hatamkhani, Chih-Kong Ken Yang:
An 8Gb/s Transformer-Boosted Transmitter with >V00 swing. 283-292 - Ana Sonia Leon, Jinuk Luke Shin, Kenway W. Tam, William Bryg, Francis Schumacher, Poonacha Kongetira, David Weisner, Allan Strong:
A Power-Efficient High-Throughput 32-Thread SPARC Processor. 295-304 - Vishnu Yalala, Derek Brasili, David Carlson, Adam Hughes, Anil Jain, Tim Kiszely, Kolar Kodandapani, Anand Varadharajan, Thucydides Xanthopoulos:
A 16-Core RISC Microprocessor with Network Extensions. 305-314 - Stefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang:
A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 Cache. 315-324 - Michael Golden, Srikanth Arekapudi, Greg Dabney, Mike Haertel, Stephen Hale, Lowell Herlinger, Yongg Kim, Kevin McGrath, Vasant Palisetti, Monica Singh:
A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory Support. 325-332 - Erwin B. Cohen, Norman J. Rohrer, Peter A. Sandon, Miles G. Canada, Cédric Lichtenau, Mathew I. Ringler, Paul Kartschoke, Robert Floyd, Jan Heaslip, M. Ross, Thomas Pflueger, Rolf B. Hilgendorf, Pete McCormick, Gerard Salem, J. Connor, Stephen F. Geissler, Dana Thygesen:
A 64B CPU Pair: Dual- and Single-Processor Chips. 333-342 - Jun Yamada, Hiroyuki Adachi, Yutaka Mori, Akihiko Harada, Seishi Okada, Hisashige Ando:
High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s Crossbar. 343-352 - Sapumal B. Wijeratne, Nanda Siddaiah, Sanu Mathew, Mark A. Anders, Ram Krishnamurthy, Jeremy Anderson, Seung Hwang, Matthew Ernest, Mark D. Nardin:
A 9GHz 65nm Intel Pentium 4 Processor Integer Execution Core. 353-365 - Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx:
A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS. 368-377 - Yuanjin Zheng, Yan Tong, Chyuen-Wei Ang, Yong Ping Xu, Wooi Gan Yeoh, Fujiang Lin, Rajinder Singh:
A CMOS Carrier-less UWB Transceiver for WPAN Applications. 378-387 - Steve Lo, Isaac Sever, Ssu-Pin Ma, Peter Jang, Albert Zou, Chris Arnott, Kalyan Ghatak, Adam Schwartz, Lam Huynh, Thai Nguyen:
Dual-antenna phased-array UWB transceiver in 0.18µm CMOS. 388-397 - Akio Tanaka, Hiroyuki Okada, Hiroshi Kodama, Hiromu Ishikawa:
A 1.1V 3.1-to-9.5GHz MB-OFDM UWB transceiver in 90nm CMOS. 398-407 - Christoph Sandner, Sven Derksen, Dieter Draxelmayr, Staffan Ek, Voicu Filimon, Graham Leach, Stefano Marsili, Denis Matveev, Koen L. R. Mertens, Florian Michl, Hermann Paule, Manfred Punzenberger, Christian Reindl, Raffaele Salerno, Marc Tiebout, Andreas Wiesbauer, Ian Winter, Zisan Zhang:
A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWB. 408-417 - Turgut Aytur, Han-Chang Kang, Ravishankar H. Mahadevappa, Mustafa Altintas, Stephan ten Brink, Thanh Diep, Cheng-Chung Hsu, Feng Shi, Fei-Ran Yang, Chao-Cheng Lee, Ran-Hong Yan, Behzad Razavi:
A Fully Integrated UWB PHY in 0.13µm CMOS. 418-427 - Che-Fu Liang, Shen-Iuan Liu, Yen-Horng Chen, Tzu-Yi Yang, Gin-Kou Ma:
A 14-band Frequency Synthesizer for MB-OFDM UWB Application. 428-437 - Mahim Ranjan, Lawrence Larson:
A Sub-1mm2 Dynamically Tuned CMOS MB-OFDM 3-to-8GHz UWB Receiver Front-End. 438-445 - Yan Polansky, Avi Lavan, Ran Sahar, Oleg Dadashev, Yoram Betser, Guy Cohen, Eduardo Maayan, Boaz Eitan, Ful-Long Ni, Yen-Hui Joseph Ku, Chih-Yuan Lu, Tim Chang-Ting Chen, Chun-Yu Liao, Chin-Hung Chang, Chung Kuang Chen, Wen-Chiao Ho, Yite Shih, Wenchi Ting, Wenpin Lu:
A 4b/cell NROM 1Gb Data-Storage Memory. 448-458 - Katsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, Sumiko M. Doumae, Sumito Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii:
A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst Mode. 459-466 - Heinz Hoenigschmid, P. Beer, Alexander Bette, R. Dittrich, R. Gardic, Dietmar Gogl, Stefan Lammers, J. Schmid, Laith Altimime, Serge Bournat, Gerhard Müller:
Signal-Margin-Screening for Multi-Mb MRAM. 467-476 - Yoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda:
A 16Mb MRAM with FORK Wiring Scheme and Burst Modes. 477-486 - Sangbeom Kang, WooYeong Cho, Beak-Hyung Cho, Kwangjin Lee, Changsoo Lee, Hyung-Rok Oh, Byung-Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Du-Eung Kim, Kang-Sik Cho, Choong-Duk Ha, Young-Ran Kim, Ki-Sung Kim, Choong-Ryeol Hwang, Choong-Keun Kwak, Hyun-Geun Byun, YunSueng Shin:
A 0.1µm 1.8V 256Mb 66MHz Synchronous Burst PRAM. 487-496 - Rino Micheloni, R. Ravasio, Alessia Marelli, E. Alice, V. Altieri, A. Bovino, Luca Crippa, E. Di Martino, L. D'Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, Ilaria Motta, A. Prisco, Giancarlo Ragone, M. Romano, Miriam Sangalli, P. Sauro, Marco Scotti, S. Won:
A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read Throughput. 497-506 - Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima:
A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput. 507-516 - Kyu-Hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jae-Kwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim:
An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection Scheme. 527-536 - Martin Brox, H. Fibranz, Maksim Kuzmenka, F. Lu, S. Mann, M. Markert, U. Möller, Manfred Plan, Kai Schiller, P. Schmölz, P. Schrögmeier, A. Täuber, Bradley Weber, Peter Mayer, Wolfgang Spirkl, Holger Steffens, Jörg Weller:
A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction Techniques. 537-546 - Dong-Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih:
A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLL. 547-556 - Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura:
An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer Scheme. 557-566 - Takeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano:
A 65nm low-power embedded DRAM with extended data-retention sleep mode. 567-576 - Jinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh:
TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search Lines. 577-586 - Young-Deok Kim, Hyun-Seok Ahn, Joon-Young Park, Suhwan Kim, Deog-Kyoon Jeong:
A Storage- and Power-Efficient Range-Matching TCAM for Packet Classification. 587-596 - Imre Knausz, Robert J. Bowman:
A 250µW 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display Drivers. 599-608 - Jong-Hak Baek, Jaehoon Lee, Han Su Pae, Chang-Ju Lee, Jongseon Kim, Myunghee Lee, JinTae Kim, ChangSik Choi, Hong Kwon Kim, Tae Jin Kim, Ho Kyoon Chung:
A Current Driver IC using a S/H for QVGA FullColor Active-Matrix Organic LED Mobile Displays. 609-618 - O. Ishibashi, M. Iriguchi, Keigo Kimura, J. Ishii, D. Sasaki, Hideyuki Imai, H. Tsuchi, Hiroshi Hayama:
Panel-Sized TFT-LCD Column Driver. 619-626 - Aydin Babakhani, Xiang Guan, Abbas Komijani, Arun Natarajan, Ali Hajimiri:
A 77GHz 4-Element Phased Array Receiver with On-Chip Dipole Antennas in Silicon. 629-638 - Arun Natarajan, Abbas Komijani, Xiang Guan, Aydin Babakhani, Y. Wang, Ali Hajimiri:
A 77GHz Phased-Array Transmitter with Local LO-Path Phase-Shifting in Silicon. 639-648 - Brian A. Floyd, Scott K. Reynolds, Ullrich R. Pfeiffer, Troy J. Beukema, Janus Grzyb, Chuck Haymes:
A silicon 60GHz receiver and transmitter chipset for broadband communications. 649-658 - Chi-Hsueh Wang, Yi-Hsien Cho, Chin-Shen Lin, Huei Wang, Chun-Hsiung Chen, Dow-Chih Niu, John Yeh, Chwan-Ying Lee, John Chern:
A 60GHz transmitter with integrated antenna in 0.18µm SiGe BiCMOS technology. 659-668 - Nicola Da Dalt, Claus Kropf, Markus Burian, Thomas Hartig, Hermann Eul:
A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOS. 669-678 - Masazumi Marutani, Hideaki Anbutsu, Masafumi Kondo, Noriaki Shirai, Hiroshi Yamazaki, Yuu Watanabe:
An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tuners. 681-690 - Pietro Andreani, Ali Fard:
A 2.3GHz LC-tank CMOS VCO with optimal phase noise performance. 691-700 - Chih-Wei Yao, Alan N. Willson Jr.:
A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversion. 701-710 - Alan W. L. Ng, Howard Cam Luong:
A 1V 17GHz 5mW Quandrature CMOS VCO based on transformer coupling. 711-720 - Jing-Hong Conan Zhan, Stewart S. Taylor:
A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applications. 721-730 - Hyung-Jin Lee, Dong S. Ha, Sang S. Choi:
A 3 to 5GHz CMOS UWB LNA with input matching using miller effect. 731-740 - Xiaofei Kuang, Nanjian Wu:
A fast-settling PLL frequency synthesizer with direct frequency presetting. 741-750 - Ehsan Afshari, Harish S. Bhat, Xiaofeng Li, Ali Hajimiri:
Electrical funnel: A broadband signal combining method. 751-760 - Jongchan Kang, Ali Hajimiri, Bumman Kim:
A single-chip linear CMOS power amplifier for 2.4 GHz WLAN. 761-769 - Tindaro Pittorino, Y. Chen, V. Neubauer, Thomas Mayer, Linus Maurer:
A UMTS-complaint fully digitally controlled oscillator with 100Mhz fine-tuning range in 0.13µm CMOS. 770-779 - Govert Geelen, Edward J. F. Paulus, Dobson Simanjuntak, Hein Pastoor, René Verlinden:
A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-step. 782-791 - Seung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania:
A 10b 50MS/s pipelined ADC with opamp current reuse. 792-801 - Yasuhide Shimizu, Shigemitsu Murayama, Kohhei Kudoh, Hiroaki Yatsuda, Akihide Ogawa:
A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOS. 802-811 - Todd Sepke, John Kenneth Fiorenza, Charles G. Sodini, Peter Holloway, Hae-Seung Lee:
Comparator-based switched-capacitor circuits for scaled CMOS technologies. 812-821 - Naveen Verma, Anantha P. Chandrakasan:
A 25µW 100kS/s 12b ADC for wireless micro-sensor applications. 822-831 - Peter Bogner, Franz Kuttner, Claus Kropf, Thomas Hartig, Markus Burian, Hermann Eul:
A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13µm CMOS. 832-841 - Hee-Cheol Choi, Ju-Wha Kim, Sang-Min Yoo, Kang-Jin Lee, Tae-Hwan Oh, Mi-Jung Seo, Jae-Whui Kim:
A 15mW 0.2mm2 50MS/s ADC with wide input range. 842-851 - Sourja Ray, Bang-Sup Song:
A 13b linear 40MS/s pipelined ADC with self-configured capacitor matching. 852-861 - Jack Kenney, Declan Dalton, Murat Hayri Eskiyerli, Eric Evans, Barry Hilton, Dave Hitchcox, Terence Kwok, Daniel Mulcahy, Chris McQuilkin, Viswabharath Reddy, Siva Selvanayagam, Paul Shepherd, Ward S. Titus, Larry DeVito:
A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOS. 864-873 - Hyeon-Min Bae, Jonathan B. Ashbrook, Jinki Park, Naresh R. Shanbhag, Andrew C. Singer, Sanjiv Chopra:
An MLSE receiver for electronic-dispersion compensation of OC-192 fiber links. 874-883 - Derrick C. Wei, Yunteng Huang, Bruno W. Garlepp, Jerrell P. Hein:
A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generation. 884-893 - Chia-Ming Tsai, Li-Ren Huang:
A 24mW 1.25Gb/s 13kΧ transimpedance amplifier using active compensation. 894-903 - Robert Swoboda, Horst Zimmermann:
11Gb/s monolithically integrated silicon optical receiver for 850nm wavelength. 904-911 - Day-Uei Li, Chia-Ming Tsai:
A 10Gb/s burst-mode/continuous-mode laser driver with current-mode extinction-ratio compensation circuit. 912-921 - Andrew Huang, Cary Gunn, Guo-Liang Li, Yi Liang, Sina Mirsaidi, Adithyaram Narasimha, Thierry Pinguet:
A 10Gb/s photonic modulator and WDM MUX/DEMUX integrated with electronics in 0.13µm SOI CMOS. 922-929 - Shahriar Rabii, Nikhil Acharya, Pak Chau, Joseph Dao, Arnold Feldman, Haw-Jyh Liaw, Dean Liu, Marc Loinaz, Manuel Luschas, Azmeer Salleh, Siddharth Sheth, Stefanos Sidiropoulos, Donald Stark, Shwetabh Verma:
An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOS. 930-939 - Masafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi:
A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOS. 940-949 - Thomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hömke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, Hamid Mabrouki, Goulhamid Juhoor, Matthias Sauer:
A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensions. 952-961 - Simon Damphousse, Khalid Ouici, Ahmed Rizki, A. Martin Mallinson:
All digital spread spectrum clock generator for EMI reduction. 962-971 - Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOS. 972-981 - Davide De Caro, Nicola Petra, Antonio G. M. Strollo:
A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOS. 982-991 - Akihiro Koyama, Hideki Iwami, Yasuhiko Mizoguchi, Shinsuke Tashiro, Fumihiro Nishiyama, Tomonari Yamagata, Yuhei Hashimoto, Masayuki Takada, Katsumi Watanabe, Jun Iwasaki, Mitsuhiro Suzuki:
A DSSS UWB digital PHY/MAC transceiver for wireless ad hoc mesh networks with distributed control. 992-1001 - Lei-Fone Chen, Yuan Chen, Lu-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee:
A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications. 1002-1011 - Mehdi Bathaee, Hamid Ghezelayagh, Wang Qin Heng, Dragos Nicolae, Octavian Fratu, Radu Pop, Gigi Dilimot, Vali Feies, Petronela Agache, Radu Ruscu, Mihu Iorgulescu, Gang Jing, Mao Lin Wei, Lei Ma, Zhaohui Dong, Tao Wang:
A 0.13µm CMOS SoC for all format blue and red laser DVD front-end digital signal processor. 1012-1021 - Jyh-Shin Pan, Tse-Hsiang Hsu, Hao-Cheng Chen, Jong-Woei Chen, Bing-Yu Hsieh, Hong-Ching Chen, Wei-Hsuan Tu, Chi-Ming Chang, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan-Cheng Hsiao, Chuan Liu, Lily Huang, Chia-Hua Chou, Chang-Long Wu, Meng-Hsueh Lin, Shang-Ping Chen, Brian Liu, Heng-Shou Hsu, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, Sean Chien, Kuan-Hua Chao, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Yih-Shin Weng, Ming-Shiam Tsai, Kun-Hung Hsieh, Kuang-Jung Chang, Jin-Chuan Hsu, Hsiu-Chen Peng, Alex Ho:
Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHY. 1022-1031 - Markus Böhm, Andreas Ullmann, Dietmar Zipperer, Alexander Knobloch, Wolfram H. Glauert, Walter Fix:
Printable electronics for polymer RFID applications. 1034-1041 - Eugenio Cantatore, Thomas C. T. Geuns, Arnold F. A. Gruijthuijsen, Gerwin H. Gelinck, Steffen Drews, Dago M. De Leeuw:
A 13.56MHz RFID System based on Organic Transponders. 1042-1051 - Vivek Subramanian, Josephine B. Lee, Vincent H. Liu, Steven E. Molesa:
Printed Electronic Nose Vapor Sensors for Consumer Product Monitoring. 1052-1059 - Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Teruki Someya, Takayasu Sakurai:
An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin. 1060-1069 - Nicolas Gay, Wolf-Joachim Fischer, Marcus Halik, Hagen Klauk, Ute Zschieschang, Günter Schmid:
Analog Signal Processing with Organic FETs. 1070-1079 - Stijn De Vusser, Soeren Steudel, Kris Myny, Jan Genoe, Paul Heremans:
A 2V Organic Complementary Inverter. 1082-1091 - Michael G. Kane, Larry Goodman, Arthur H. Firester, Paul C. van der Wilt, Alex B. Limanov, James S. Im:
CMOS-on-Plastic Technology using Sequential Laterally Solidified Silicon Thin-Film Transistors. 1092-1098 - Babak Vakili-Amini, Reza Abdolvand, Farrokh Ayazi:
A 4.5mW Closed-Loop ΔΣ Micro-Gravity CMOS-SOI Accelerometer. 1101-1110 - Wan-Thai Hsu, Andrew R. Brown, Kenneth R. Cioffi:
A Programmable MEMS FSK Transmitter. 1111-1120 - Tim Denison, Jinbo Kuang, John S. Shafran, Michael Judy, Kent H. Lundberg:
A Self-Resonant MEMS-based Electrostatic Field Sensor with 4V/m/Hz Sensitivity. 1121-1130 - Mattia Malfatti, David Stoppa, Andrea Simoni, Leandro Lorenzelli, Andrea Adami, Andrea Baschirotto:
A CMOS Interface for a Gas-Sensor Array with a 0.5%-Linearity over 500kΧ-to-1GΧ Range and 2.5°C Temperature Control Accuracy. 1131-1140 - Kofi A. A. Makinwa, Martijn F. Snoeij:
A CMOS Temperature-to-Frequency Converter with an Inaccuracy of 0.5°C (3 σ) from -40 to 105°C. 1141-1150 - Mario Motz, Udo Ausserlechner, Wolfgang Scherr, Bernhard Schaffer:
An Integrated Magnetic Sensor with Two Continuous-Time ΔΣ-Converters and Stress Compensation Capability. 1151-1160 - Nana Akahane, Rie Ryuzaki, Satoru Adachi, Koichi Mizobuchi, Shigetoshi Sugawa:
A 200dB Dynamic Range Iris-less CMOS Image Sensor with Lateral Overflow Integration Capacitor using Hybrid Voltage and Current Readout Operation. 1161-1170 - Shin Iwabuchi, Yasushi Maruyama, Yuko Ohgishi, Masafumi Muramatsu, Nobuhiro Karasawa, Teruo Hirayama:
A Back-Illuminated High-Sensitivity Small-Pixel Color CMOS Image Sensor with Flexible Layout of Metal Wiring. 1171-1178 - Brian Aull, Jim Burns, Chenson Chen, Bradley Felton, Helen Hanson, Craig L. Keast, Jeffrey M. Knecht, Andrew Loomis, Matthew Renzi, Antonio M. Soares, Vyshnavi Suntharalingam, Keith Warner, Deanna Wolfson, Donna Yost, Douglas Young:
Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit Layers. 1179-1188 - Mitsuo Usami, Akira Sato, Hisao Tanabe, Toshiaki Iwamatsu, Shigeto Maegawa, Yuzuru Ohji:
An SOI-Based 7.5µm-Thick 0.15x0.15mm2 RFID Chip. 1191-1200 - Hiroyuki Nakamoto, Daisuke Yamazaki, Takuji Yamamoto, Hajime Kurata, Satoshi Yamada, Kenji Mukaida, Tsuzumi Ninomiya, Takashi Ohkawa, Shoichi Masui, Kunihiko Gotoh:
A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM Technology. 1201-1210 - B. Gomez, Gilles Masson, Patrick Villard, Gérard Robert, François Dehmas, Jacques Reverdy:
A 3.4Mb/s RFID Front-end for Proximity Applications Based on a Delta-modulator. 1211-1217 - Daquan Huang, William Hant, Ning-Yi Wang, Tai W. Ku, Qun Gu, Raymond Wong, Mau-Chung Frank Chang:
A 60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise Reduction. 1218-1227 - Mohammed Aissi, Eric Tournier, Marc-Alexandre Dubois, Guy Parat, Robert Plana:
A 5.4GHz 0.35µm BiCMOS FBAR Resonator Oscillator in Above-IC Technology. 1228-1235 - Dana Weinstein, Hengky Chandrahalim, Lih Feng Cheow, Sunil A. Bhave:
Dielectrically Transduced Single-Ended to Differential MEMS Filter. 1236-1243 - Jérémie Chabloz, Claude Müller, Franz Pengg, Aurélie Pezous, Christian C. Enz, Marc-Alexandre Dubois:
A Low-Power 2.4GHz CMOS Receiver Front-End Using BAW Resonators. 1244-1253 - Chieh-Min Lo, Chin-Shen Lin, Huei Wang:
A Miniature V-band 3-Stage Cascode LNA in 0.13µm CMOS. 1254-1263 - Christian Kromer, Gion Sialm, Christian Menolfi, Martin L. Schmatz, Frank Ellinger, Heinz Jäckel:
A 25Gb/s CDR in 90nm CMOS for High-Density Interconnects. 1266-1275 - Michael H. Perrott, Yunteng Huang, Rex T. Baird, Bruno W. Garlepp, Ligang Zhang, Jerrell P. Hein:
A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop Filter. 1276-1285 - Yusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Yasuyuki Doi, Makoto Hattori:
A 0.03mm2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface. 1286-1295 - Haechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, Stefanos Sidiropoulos, Mark Horowitz:
Improving CDR Performance via Estimation. 1296-1303 - Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker:
A 3.2Gb/s Semi-Blind-Oversampling CDR. 1304-1313 - Hamid Partovi, Wolfgang Walthes, Luca Ravezzi, Paul Lindt, Sivaraman Chokkalingam, Karthik Gopalakrishnan, Andreas Blum, Otto Schumacher, Claudio Andreotti, Michael Bruennert, Bruno Celli-Urbani, Dirk Friebe, Ivo Koren, Michael Verbeck, Ulrich Lange:
Data Recovery and Retiming for the Fully Buffered DIMM 4.8Gb/s Serial Links. 1314-1323 - Sangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu:
A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase Detector. 1324-1333 - Bryan Casper, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, K. Canagasaby, Joe Kennedy, Randy Mooney:
A 20Gb/s Embedded Clock Transceiver in 90nm CMOS. 1334-1343 - Flemming Nyboe, Cetyn Kaya, Lars Risbo, Pietro Andreani:
A 240W Monolithic Class-D Audio Amplifier Output Stage. 1346-1355 - Ronan A. R. van der Zee, Remko van Heeswijk:
Frequency Compensation of an SOI Bipolar-CMOSDMOS Car Audio PA. 1356-1365 - Toru Ido, Sonny Ishizuka, Lars Risbo, Fumitaka Aoyagi, Toshi Hamasaki:
A Digital Input Controller for Audio Class-D Amplifiers with 100W 0.004% THD+N and 113dB DR. 1366-1375 - Stefano D'Amico, Matteo Conta, Andrea Baschirotto:
A 4.1mW 79dB-DR 4th-order Source-FollowerBased Continuous-Time Filter for WLAN Receivers. 1378-1387 - Rod Burt, Joy Zhang:
A Micropower Chopper-Stabilized Operational Amplifier using a SC Notch Filter with Synchronous Integration inside the ContinuousTime Signal Path. 1388-1397 - Siamak Abedinpour, Bertan Bakkaloglu, Sayfe Kiaei:
A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18µ SiGe process. 1398-1407 - Tsz Yin Man, Philip K. T. Mok, Mansun Chan:
A CMOS-Control Rectifier for DiscontinuousConduction Mode Switching DC-DC Converters. 1408-1417 - Yorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, Mostafa A. Elmala, Ralph E. Bishop, Gaurab Banerjee, Rich B. Nicholls, Stanley K. Ling, Stewart S. Taylor, Krishnamurthy Soumyanath:
A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOS. 1420-1429 - Lalitkumar Nathawad, David Weber, Shahram Abdollahi-Alibeik, Phoebe Chen, Syed Enam, Brian J. Kaczynski, Alireza Kheirkhahi, MeeLan Lee, Sotirios Limotyrakis, Keith Onodera, Katelijn Vleugels, Masoud Zargari, Bruce A. Wooley:
An IEEE 802.11a/b/g SoC for Embedded WLAN Applications. 1430-1439 - Tony Montalvo, C. Angell, David J. McLaurin, Corey Petersen, Eric Fogleman, Janet Brunsilius, Phil Brown, Ege Yetis, Jeff Bray, M. Kessler, Bernard Tenbroek:
A Wireless Transceiver with Integrated Data Converters for 802.11a/b/g Access Points. 1440-1449 - C. Paul Lee, Arya Behzad, Dayo Ojo, Michael S. Kappes, Stephen Au, Meng-An Pan, Keith A. Carter, Shirley Tian:
A Highly Linear Direct-Conversion Transmit Mixer Transconductance Stage with Local Oscillation Feedthrough and I/Q Imbalance Cancellation Scheme. 1450-1459 - Ben W. Cook, Axel D. Berny, Alyosha C. Molnar, Steven Lanzisera, Kristofer S. J. Pister:
An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm CMOS with 400mV Supply and an Integrated Passive RX Front-End. 1460-1469 - Wolfram Kluge, Frank Poegel, Hendrik Roller, Matthias Lange, Tilo Ferchland, Lutz Dathe, Dietmar Eggert:
A Fully Integrated 2.4GHz IEEE 802.15.4 Compliant Transceiver for ZigBee Applications. 1470-1479 - George Hayashi, Akihiro Sawada, Takashi Morie, Kazuhiro Matsuyama, Ryangsu Kim, Seichiro Yoshida, Akinori Matsumoto, Katsumasa Hijikata, Kazuo Matsukawa, Yoshihiro Tamura, Jun Ogawa, Toshio Takita:
A 10.8mA Single Chip Transceiver for 430MHz Narrowband Systems in 0.15µm CMOS. 1480-1489 - Jia-Yi Chen, Michael P. Flynn, John P. Hayes:
A Fully Integrated Auto-Calibrated SuperRegenerative Receiver. 1490-1499 - Daniel J. Allen, Adam L. Carley:
Free-Running Ring Frequency Synthesizer. 1502-1511 - Simon Tam, Justin Leung, Rahul Dilip Limaye, Sam Choy, Sujal Vora, Mitsuhiro Adachi:
Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 Cache. 1512-1521 - Michael G. R. Thomson, Phillip J. Restle, Norman K. James:
A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 Microprocessor. 1522-1529 - Xiaoling Guo, Dong-Jun Yang, Ran Li, Kenneth K. O:
A Receiver with Start-up Initialization and Programmable Delays for Wireless Clock Distribution. 1530-1539 - Visvesh S. Sathe, Juang-Ying Chueh, Marios Papaefthymio:
A 1.1ghz charge-recovery logic. 1540-1549 - John Wood, Tim Edwards, Conrad Ziesler:
A 3.5GHz Rotary-Traveling-Wave-Oscillator Clocked Dynamic Logic Family in 0.25µm CMOS. 1550-1557 - Anup P. Jose, Kenneth L. Shepard:
Distributed Loss Compensation for Low-latency On-chip Interconnects. 1558-1567 - Tsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang, Chen-Yi Lee:
A 125µw, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications. 1576-1585 - Yu-Wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Chung-Jr Lian, Shao-Yi Chien, Liang-Gee Chen:
124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory. 1586-1595 - C. C. Lin, J. I. Guo, H. C. Chang, Y. C. Yang, J. W. Chen, M. C. Tsai, J. S. Wang:
A 160kgate 4.5kB SKRAM H.264 video decoder for HDTV applications. 1596-1605 - Chang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim:
A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applications. 1606-1615 - Masami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu:
A 40GOPS 250mW massively parallel processor based on matrix architecture. 1616-1625 - Chia-Ping Lin, Po-Chih Tseng, Yao-Ting Chiu, Siou-Shen Lin, Chih-Chi Cheng, Hung-Chi Fang, Wei-Min Chao, Liang-Gee Chen:
A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications. 1626-1635 - Yoshitaka Ueda, Hideki Yamauchi, Mamoru Mukuno, Shinji Furuichi, Mayumi Fujisawa, Fei Qiao, Huazhong Yang:
6.33mW MPEG audio decoding on a multimedia processor. 1636-1645 - Rajesh Duggirala, Hui Li, Amit Lal:
Active circuits for ultra-high efficiency micropower generators using nickel-63 radioisotope. 1648-1655 - Christian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, Michael Gostkowski, Gerhard Knoblinger, Andrew Marshall, Thomas Nirschl, Jörg Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer:
Circuit design issues in multi-gate FET CMOS technologies. 1656-1665 - Ralf Brederlow, Ramesh Prakash, Christian Paulus, Roland Thewes:
A low-power true random number generator using random telegraph noise of single oxide-traps. 1666-1675 - Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda:
A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data link. 1676-1685 - Keishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, Muneo Fukaishi, Masayuki Mizuno, Koichi Nose, Ichiro Ogura, Yutaka Urino, Toshio Baba:
Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonics. 1686-1695 - Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, Mandeep Singh, Bevan M. Baas:
An asynchronous array of simple processors for dsp applications. 1696-1705 - Kouichi Kumagai, Changqi Yang, Hitoshi Izumino, Nobuyuki Narita, Keisuke Shinjo, Shin-ichi Iwashita, Yuji Nakaoka, Tomohiro Kawamura, Hideo Komabashiri, Tsukasa Minato, Atsushi Ambo, Takamasa Suzuki, Zhenyu Liu, Yang Song, Satoshi Goto, Takeshi Ikenaga, Yoshihiro Mabuchi, Kenji Yoshida:
System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTV. 1706-1715 - David S. Ricketts, Donhee Ham:
A chip-scale electrical soliton modelocked oscillator. 1716-1725 - Brian W. Curran, Bradley D. McCredie, Leonid Sigal, Eric M. Schwarz, Bruce M. Fleischer, Yuen H. Chan, D. Webber, Vaden Vaden, A. Goyal:
4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processor. 1728-1734 - Sean Kao, Radu Zlatanovici, Borivoje Nikolic:
A 240ps 64b carry-lookahead adder in 90nm CMOS. 1735-1744 - Kian Haur Chong, Larry McMurchie, Carl Sechen:
A 64b adder using self-calibrating differential output prediction logic. 1745-1754 - Yolin Lih, Nestoras Tzartzanis, William W. Walker:
A leakage current replica keeper for dynamic circuits. 1755-1764 - Peter Caputa, Christer Svensson:
An on-chip delay- and skew-insensitive multicycle communication scheme. 1765-1774 - Masaya Sumita, T. Wada:
A 14: 1 dynamic MUX FF with select activity detection. 1775-1784 - Steven K. Hsu, Amit Agarwal, Mark A. Anders, Sanu Mathew, Ram Krishnamurthy, Shekhar Borkar:
An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOS. 1785-1797 - Rameswor Shrestha, Eisse Mensink, Eric A. M. Klumperink, Gerard J. M. Wienk, Bram Nauta:
A multipath technique for canceling harmonics and sidebands in a wideband power upconverter. 1800-1809 - Supisa Lerstaveesin, Bang-Sup Song:
A complex image rejection circuit with sign detection only. 1810-1819 - Mohammad Hajirostam, Ken Martin:
On-chip image rejection in a low-if cmos receiver. 1820-1829 - Minghui Chen, Yue Wu, M. Frank Chang:
Active 2nd-order intermodulation calibration for direct-conversion receivers. 1830-1839 - Henry C. Jen, Steven C. Rose, Robert G. Meyer:
A 2.2GHz sub-harmonic mixer for directconversion receivers in 0.13µm CMOS. 1840-1849 - Atsushi Yoshizawa, Yannis P. Tsividis:
A Blocker-Vigilant Channel-Select Filter with Adaptive IIP3 and Power Dissipation. 1850-1859 - Hooman Darabi, Hea Joung Kim, Janice Chiu, Brima Ibrahim, Louie Serrano:
An IP2 Improvement Technique for Zero-IF Down-Converters. 1860-1869 - Rajasekhar Pullela, Tirdad Sowlati, Dmitriy Rozenblit:
Low Flicker-Noise Quadrature Mixer Topology. 1870-1879 - Massimo Brandolini, Marco Sosio, Francesco Svelto:
A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOS. 1882-1891 - Antonio Liscidini, Andrea Mazzanti, Riccardo Tonietto, Luca Vandi, Pietro Andreani, Rinaldo Castello:
A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCO. 1892-1901 - Valentina Della Torre, Matteo Conta, Ramesh Chokkalingam, Giuseppe Cusmai, Paolo Rossi, Francesco Svelto:
A 20mw 3.24mm2 fully integrated gps radio for cell-phones. 1902-1911 - Koji Maeda, Willy Hioe, Yasuyuki Kimura, Satoshi Tanaka:
Wideband Image-Rejection Circuit for Low-IF Receivers. 1912-1921 - Manoj Gupta, Bang-Sup Song:
A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain Calibration. 1922-1931 - Rahim Bagheri, Ahmad Mirzaei, Saeed Chehrazi, Mohammad E. Heidari, Minjae Lee, Mohyee Mikhemar, Wai K. Tang, Asad A. Abidi:
An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOS. 1932-1941 - Pierre-Henri Bonnaud, Markus Hammes, Andre Hanke, Jens Kissing, Rudolf Koch, Eric Labarre, Christoph Schwoerer:
A Fully Integrated SoC for GSM/GPRS in 0.13µm CMOS. 1942-1951 - Srenik S. Mehta, William W. Si, Hirad Samavati, Manolis Terrovitis, Michael P. Mack, Keith Onodera, Steve H. Jen, Susan Luschas, Justin A. Hwang, Suni Mendis, David K. Su, Bruce A. Wooley:
A 1.9GHz Single-Chip CMOS PHS Cellphone. 1952-1961 - Naratip Wongkomet, Luns Tee, Paul R. Gray:
A 1.7GHz 1.5W CMOS RF Doherty Power Amplifier for Wireless Communications. 1962-1971 - Jere A. M. Järvinen, Kari Halonen:
A 1.2V Dual-Mode GSM/WCDMA - Modulator in 65nm CMOS. 1972-1981 - Satoshi Yoshihara, Masaru Kikuchi, Yoshiharu Ito, Yoshiaki Inada, Souichiro Kuramochi, Hayato Wakabayashi, Masafumi Okano, Ken Koseki, Hiromi Kuriyama, Junichi Inutsuka, Akari Tajima, Tadashi Nakajima, Yoshiharu Kudoh, Fumihiko Koga, Yasuo Kasagi, Shinya Watanabe, Tetsuo Nomoto:
A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode Change. 1984-1993 - Young Chan Kim, Yi Tae Kim, Sung Ho Choi, Hae Kyung Kong, Sung In Hwang, Juhyun Ko, Bumsuk Kim, Tetsuo Asaba, Su Hun Lim, June Soo Hahn, Joon Hyuk Im, Tae Seok Oh, Duk Min Yi, Jong Moon Lee, Woon Phil Yang, Jung Chak Ahn, Eun Seung Jung, Yong Hee Lee:
1/2-inch 7.2MPixel CMOS Image Sensor with 2.25µm Pixels Using 4-Shared Pixel Structure for Pixel-Level Summation. 1994-2003 - Jungwook Yang, Keith Fife, Lane Brooks, Charles G. Sodini, Andrew Betts, Pavan Mudunuru, Hae-Seung Lee:
A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor. 2004-2013 - Martijn F. Snoeij, Albert Theuwissen, Kofi A. A. Makinwa, Johan H. Huijsing:
A CMOS Imager with Column-Level ADC Using Dynamic Column FPN Reduction. 2014-2023 - Yoshikazu Nitta, Yoshinori Muramatsu, Kiyotaka Amano, Takayuki Toyama, Jun Yamamoto, Koji Mishina, Atsushi Suzuki, Tadayuki Taura, Akihiko Kato, Masaru Kikuchi, Yukihiro Yasui, Hideo Nomura, Noriyuki Fukushima:
High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel Sensor. 2024-2031 - Ronald A. Kapusta, Shingo Hatanaka, Steven J. Decker, Jianrong Chen, David Foley, Anthony Wellinger, Murat Ozbas, Dan F. Kelly, Mark T. Sayuk, William G. Schofield, Katsu Nakamura:
A 14b 74MS/s CMOS AFE for True High-Definition Camcorders. 2032-2039 - Alex Krymski, Kenji Tajima:
CMOS Image Sensor with integrated 4Gb/s Camera Link Transmitter. 2040-2049 - Ralf M. Philipp, Ralph Etienne-Cummings:
A 128 x128 33mW 30frames/s single-chip stereo imager. 2050-2059 - Patrick Lichtsteiner, Christoph Posch, Tobias Delbrück:
A 128 X 128 120db 30mw asynchronous vision sensor that responds to relative intensity change. 2060-2069 - Eduard Säckinger, Aner Tennen, Dima Shulman, Barkat Wani, Marta Rambaud, Drahoslav Lím, Fred Larsen, George S. Moschytz:
A 5V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size Reduction. 2072-2081 - Jonas R. M. Weiss, Marcel A. Kossel, Christian Menolfi, Thomas Morf, Martin L. Schmatz, Thomas Toifl, Heinz Jäckel:
A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth Enhancement. 2082-2091 - Chih-Fan Liao, Shen-Iuan Liu:
A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb Ethernet. 2092-2101 - Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda:
A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor Hybrid. 2102-2111 - Koichi Nose, Mikihiro Kajita, Masayuki Mizuno:
A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter Oversampling. 2112-2121 - Toshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe:
1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE Applications. 2122-2131 - James S. Humble, Patrick J. Zabinski, Barry K. Gilbert, Erik S. Daniel:
A Clock Duty-Cycle Correction and Adjustment Circuit. 2132-2141 - Jean-Olivier Plouchart, Jonghae Kim, Victor Karam, Robert Trzcinski, Jeff Gross:
Performance Variations of a 66GHz Static CML Divider in 90nm CMOS. 2142-2151 - Byung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu:
A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOS. 2152-2159 - Torgil Kjellberg, Joakim Hallin, Thomas Swahn:
104Gb/s 2"-1 and 110Gb/s 2-1 PRBS Generator in InP HBT Technology. 2160-2169 - Hendrik F. Hamann, Alan J. Weger, James A. Lacey, Erwin B. Cohen, Craig Atherton:
Power Distribution Measurements of the Dual Core PowerPCTM 970MP Microprocessor. 2172-2179 - Peter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik:
A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC Converters. 2180-2189 - Héctor Sánchez, Bill Johnstone, Doug Roberts, Om Mandhana, Brad Melnick, Muhsin Celik, Mike Baker, Jim Hayden, Byoung Min, John Edgerton, Bruce White:
Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling Capacitors. 2190-2199 - Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie:
Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU Processor. 2200-2209 - Toshihiro Hattori, Takahiro Irita, Masayuki Ito, Eiji Yamamoto, Hisashi Kato, Go Sado, Tetsuhiro Yamada, Kunihiko Nishiyama, Hiroshi Yagi, Takao Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, Kenji Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, Nobuto Arai, Tomohiro Akiyama, Koji Ohno:
A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile Processor. 2210-2219 - Violeta Petrescu, Marcel J. M. Pelgrom, Harry J. M. Veendrick, Praveen Pavithran, Jean Wieling:
A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICs. 2220-2229 - Ming-Dou Ker, Wei-Jen Chang, Chang-Tzu Wang, Wen-Yi Chen:
ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOS. 2230-2237 - Eskinder Hailu, David W. Boerstler, Kazuhiko Miki, Jieming Qi, Michael Wang, Mack W. Riley:
A Circuit for Reducing Large Transient Current Effects on Processor Power Grids. 2238-2245 - Stephen O'Driscoll, Teresa H. Meng, Krishna V. Shenoy, Caleb Kemere:
Neurons to Silicon: Implantable Prosthesis Processor. 2248-2257 - Reid R. Harrison, Paul T. Watkins, Ryan J. Kier, Robert O. Lovejoy, Daniel J. Black, Richard A. Normann, Florian Solzbacher:
A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System. 2258-2267 - Bo Wen, Kwabena Boahen:
A 360-Channel Speech Preprocessor that Emulates the Cochlear Amplifier. 2268-2277 - Seong-Jun Song, Namjun Cho, Sunyoung Kim, Jerald Yoo, Hoi-Jun Yoo:
A 2Mb/s Wideband Pulse Transceiver with Direct-Coupled Interface for Human Body Communications. 2278-2287 - Nobuhiro Gemma, Shin-ichi O'Uchi, Hideyuki Funaki, Jun Okada, Sadato Hongo:
CMOS Integrated DNA Chip for Quantitative DNA Analysis. 2288-2297 - Chun-Hao Chen, Rong-Zhang Hwang, Long-Sun Huang, Shi-Ming Lin, Hsiao-Chin Chen, Yu-Che Yang, Yu-Tso Lin, Shih-An Yu, Yo-Sheng Lin, Yiao-Hong Wang, Nai-Kuan Chou, Shey-Shi Lu:
A Wireless Bio-MEMS Sensor for C-Reactive Protein Detection Based on Nanomechanics. 2298-2307 - Geert Van der Plas, Stefaan Decoutere, Stéphane Donnay:
A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS Process. 2310- - Pedro M. Figueiredo, Paulo Cardoso, Ana Lopes, Carlos Fachada, Naoyuki Hamanishi, Ken Tanabe, João C. Vital:
A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC. 2320-2329 - Sunghyun Park, Yorgos Palaskas, Michael P. Flynn:
A 4GS/s 4b Flash ADC in 0.18µm CMOS. 2330-2339 - Peter Schvan, Daniel Pollex, Shing-Chi Wang, Chris Falt, Naim Ben-Hamida:
A 22GS/s 5b adc in 0.13µm SiGe BiCMOS. 2340-2349 - Mike Shuo-Wei Chen, Robert W. Brodersen:
A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOS. 2350-2359 - Sandeep Gupta, Michael Choi, Michael A. Inerfield, Jingbo Wang:
A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOS. 2360-2369 - Shahin Mehdizad Taleie, Tino Copani, Bertan Bakkaloglu, Sayfe Kiaei:
A Bandpass ΔΣ RF-DAC with Embedded FIR Reconstruction Filter. 2370-2379 - Dalius Baranauskas, Denis Zelenin:
A 0.36W 6b up to 20GS/s DAC for UWB Wave Formation. 2380-2389 - Kok Lim Chan, Ian Galton:
A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching. 2390-2399 - Hyung-Rok Lee, Ook Kim, Keewook Jung, John Shin, Deog-Kyoon Jeong:
A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µm. 2402-2411 - Merrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon:
A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated Tuning. 2412-2421 - Shiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie:
A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution. 2422-2431 - Tai-Cheng Lee, Wei-Liang Lee:
A Spur Suppression Technique for Phase-Locked Frequency Synthesizers. 2432-2441 - Richard Gu, Ah-Lyan Yee, Yiqun Xie, Wai Lee:
A 6.25GHz 1V LC-PLL in 0.13µm CMOS. 2442-2451 - Nestoras Tzartzanis, William W. Walker:
A Reversible Poly-Phase Distributed VCO. 2452-2461 - George von Büren, Christian Kromer, Frank Ellinger, Alex Huber, Martin L. Schmatz, Heinz Jäckel:
A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS. 2462-2471 - Ken Yamamoto, Minoru Fujishima:
70GHz CMOS Harmonic Injection-Locked Divider. 2472-2481 - Hui Wu, Lin Zhang:
A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3 Injection-Locked Frequency Divider. 2482-2491 - Iason Vassiliou, Kostis Vavelidis, Stamatis Bouras, Spyros Kavadias, Yiannis Kokolakis, George Kamoulakos, Aristeidis Kyranas, Charalampos Kapnistis, Nikos Haralabidis:
A 0.18µm CMOS Dual-Band Direct-Conversion DVB-H Receiver. 2494-2503 - Young-Jin Kim, Jae-Wan Kim, Viktor N. Parkhomenko, Donghyun Baek, Jae-heon Lee, Eun-yung Sung, Iiku Nam, Byeong-Ha Park:
A Multi-Band Multi-Mode CMOS DirectConversion DVB-H Tuner. 2504-2513 - Michael Womac, Armin Deiss, Tom Davis, Ron Spencer, Buddhika Abesingha, Philip Hisayasu:
Dual-band Single-Ended-Input Direct-Conversion DVB-H Receiver. 2514-2523 - Vincenzo Peluso, Yang Xu, Peter Gazzerro, Yiwu Tang, Li Liu, Zhenbiao Li, Wei Xiong, Charles J. Persico:
A Dual-Channel Direct-Conversion CMOS Receiver for Mobile Multimedia Broadcasting. 2524-2533 - Bonkee Kim, Tae Wook Kim, Youngho Cho, Minsu Jeong, Seyeob Kim, Heeyong Yoo, Seong-Mo Moon, Tae-Ju Lee, Jin-Kyu Lim, Boeun Kim:
A 100mW Dual-Band CMOS Mobile-TV Tuner IC for T-DMB/DAB and ISDB-T. 2534-2543 - Myung-woon Hwang, Sungho Beck, Sunki Min, Sanghoon Lee, Seungyup Yoo, Kyoohyun Lim, Hyosun Jung, Jeong-Cheol Lee, Seokyong Hong, ChangHee Lee, Kyunglok Kim, Hyunji Song, Gyu-Hyeong Cho, Sangwoo Han:
A 1.8dB NF 112mW Single-Chip Diversity Tuner for 2.6GHz S-DMB Applications. 2544-2551 - Adrian Maxim, R. Poorfard, J. Kao:
A sub-1.5°rms Phase-Noise Ring-Oscillator-Based Frequency Synthesizer for Low-IF Single-Chip DBS Satellite Tuner-Demodulator SoC. 2552-2561 - John Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr:
A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM Processor. 2564-2571 - Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. 2572-2581 - Chih Tseng, Jae-Hyeong Kim, Suzanne Chen, Mu-Hsiang Huang, Chungji Lu, Ikio Hashiguchi, Yoshifumi Miyazima, Masahiro Ichihashi, Kentaro Maki, Katsuya Nakashima, Patrick Chuang:
A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data Bandwidth. 2582-2591 - Benton H. Calhoun, Anantha P. Chandrakasan:
A 256kb Sub-threshold SRAM in 65nm CMOS. 2592-2601 - Koichi Takeda, Hidetoshi Ikeda, Yasuhiko Hagihara, Masahiro Nomura, Hiroyuki Kobatake:
Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit. 2602-2611 - Rich Roy, Farid Nemati, Ken Young, Bruce Bateman, Rajesh Chopra, Seong-Ook Jung, Chiming Show, Hyun-Jin Cho:
Thyristor-Based Volatile Memory in Nano-Scale CMOS. 2612-2621
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