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ORCIDISSCC 2007: San Francisco, CA, USA
- 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. IEEE 2007, ISBN 1-4244-0853-9
- J. Morris Chang:
Foundry Future: Challenges in the 21st Century. 18-23 - Lewis W. Counts:
Analog and Mixed-Signal Innovation: The Process-Circuit-System-Application Interaction. 24-30 - Joël Hartmann:
Towards a New Nanoelectronic Cosmology. 31-37 - Sung Min Park, Yuriy M. Greshishchev:
Optical Communications. 40-41 - Adithyaram Narasimha, Behnam Analui, Yi Liang, Thomas J. Sleboda, Cary Gunn:
A Fully Integrated 4ÿ10Gb/s DWDM Optoelectronic Transceiver in a standard 0.13μm CMOS SOI. 42-586 - Samuel Palermo, Azita Emami-Neyestanak
, Mark Horowitz:
A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects. 44-586 - Jri Lee, Mingchung Liu:
A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique. 46-586 - Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu:
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS. 48-586 - Quan Le, Sang-Gug Lee, Ho-Yong Kang, Sang-Hoon Chang:
A CMOS Burst-Mode TIA with Step AGC and Selective Internally Created Reset for 1.25Gb/s EPON. 50-51 - Chia-Ming Tsai, Wen-Tsao Chen:
A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation. 52-586 - Chih-Fan Liao, Shen-Iuan Liu:
A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS. 54-586 - Kwisung Yoo, Dongmyung Lee, Gunhee Han, Sung Min Park, Wonseok Oh:
A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation. 56-57 - Axel Thomsen, Ligang Zhang, Doug Frey, Q. Yu, Lizhong Sun, Akhil K. Garlapati, R. Hulfachor, Douglas F. Pastorello, Richard J. Juhn:
A Fractional-N PLL for SONET-Quality Clock-Syntlhesis Applicationis. 58-587 - Eugenio Cantatore, Shuichi Tahara:
TD: Emerging Devices Devices and Circuits. 60-61 - Hélène Lhermet, Cyril Condemine, Marc Plissonnier, Raphael Salot, Patrick Audebert, Marion Rosset:
Efficient Power Management Circuit: Thermal Energy Harvesting to Above-IC Microbattery Energy Storage. 62-587 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
Minimum Energy Tracking Loop with Embedded DC-DC Converter Delivering Voltages down to 250mV in 65nm CMOS. 64-587 - Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada:
LAGS System Using Data/Instruction Grain Power Control. 66-587 - Zhihong Chen, Jörg Appenzeller, Paul M. Solomon, Yu-Ming Lin, Phaedon Avouris:
Gate Work Function Engineering for Nanotube-Based Circuits. 68-587 - Jie Deng, Nishant Patil, Koungmin Ryu, Alexander Badmaev, Chongwu Zhou, Subhasish Mitra, H.-S. Philip Wong:
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections. 70-588 - Ivan Nausieda, Kyungbum Kevin Ryu, Ioannis Kymissis, Akintunde Ibitayo Akinwande, Vladimir Bulovic, Charles G. Sodini:
An Organic Imager for Flexible Large Area Electronics. 72-73 - Reiji Hattori, Michihiro Asakawa, Yoshitomo Masuda, Norio Nihei, Akihiko Yokoo, Shuhei Yamada, Itsuo Tanuma:
Passive-Matrix Flexible Electronic Paper Using Quick-Response Liquid Powder Display (QR-LPD) Technollogy and Custom Driver Circuits. 74-588 - Nikolaus Klemmer, Satoshi Tanaka:
RF Building Blocks. 76-77 - Amirpouya Kavousian, David K. Su, Bruce A. Wooley:
A Digitally Modulated Polar CMOS PA with 20MHz Signal BW. 78-588 - Francesco Carrara, Calogero D. Presti, Antonino Scuderi, Carmelo Santagati, Giuseppe Palmisano:
A 3W 55% PAE CMOS PA with Closed-Loop 20: 1 VSWR Protection. 80-588 - Jennifer Kitchen, Wing-Yee Chu, Ilker Deligoz, Sayfe Kiaei, Bertan Bakkaloglu:
Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar Transmitters. 82-588 - Hooman Darabi:
A Blocker Filtering Technique for Wireless Receivers. 84-588 - Krzysztof Dufrene, Zdravko Boos, Robert Weigel:
A 0.13μm 1.5V CMOS I/Q Downconverter with Digital Adaptive IIP2 Calibration. 86-589 - Hong-Sing Kao, Ming-Jen Yang, Tai-Cheng Lee:
A Delay-Line-Based GFSK Demodulator for Low-IF Receivers. 88-589 - Aleksander Dec, Ken Suyama, Tomomitsu Kitamura:
A 4.5GHz LC-VCO with Self-Regulating Technique. 90-589 - Giuseppe Cusmai, Matteo Repossi, Guido Albasini, Francesco Svelto:
A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning. 92-589 - Stefan Rusu, Jim Warnock:
Microprocessors. 94-95 - Joshua Friedrich, Bradley D. McCredie, Norman K. James, Bill Huott, Brian W. Curran, Eric Fluhr, Gaurav Mittal, Eddie Chan, Yuen H. Chan, Donald W. Plass, Sam G. Chu, Hung Q. Le, Leo Clark, John R. Ripley, Scott A. Taylor, Jack DiLullo, Mary Yvonne Lanzerotti:
Design of the Power6 Microprocessor. 96-97 - Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar:
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. 98-589 - Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara:
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. 100-590 - J. Dorsey, S. Searles, Michael Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, R. Kumar:
An Integrated Quad-Core Opteron Processor. 102-103 - Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong:
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. 104-105 - Nabeel Sakran, Marcelo Yuffe, Moty Mehalel, Jack Doweck, Ernest Knoll, Avi Kovacs:
The Implementation of the 65nm Dual-Core 64b Merom Processor. 106-590 - Umesh Gajanan Nawathe, Mahmudul Hassan, Lynn Warriner, King C. Yen, Bharat Upputuri, David Greenhill, Ashok Kumar, Heechoul Park:
An 8-Core 64-Thread 64b Power-Efficient SPARC SoC. 108-590 - Sang-Gug Lee, Ranjit Gharpurey:
UWB and mm-Wave Communications Systems. 110-111 - Jos Bergervoet, Harish Kundur Subramaniyan, S. Lee, Domine Leenaerts, Remco van de Beek, Gerard van der Weide, Raf Roovers:
A WiMedia-Compliant UWB Transceiver in 65nm CMOS. 112-590 - Yuanjin Zheng, King-Wah Wong, M. Annamalai Asaru, Dan Shen, Wen Hu Zhao, Yen Ju The, P. Andrew, Fujiang Lin, Wooi Gan Yeoh, Rajinder Singh:
A 0.18μm CMOS Dual-Band UWB Transceiver. 114-590 - Fred S. Lee, Anantha P. Chandrakasan:
A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS. 116-590 - David D. Wentzloff, Anantha P. Chandrakasan:
A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS. 118-591 - Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx:
A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. 120-591 - Ville Saari, Mikko Kaltiokallio, Saska Lindfors, Jussi Ryynänen, Kari Halonen:
A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver. 122-591 - Harish Krishnaswamy, Hossein Hashemi:
A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable-Phase Ring Oscillator and PLL Architecture. 124-591 - Hoon Hee Chung, Umar Lyles, Tino Copani, Bertan Bakkaloglu, Sayfe Kiaei:
A Bandpass ΔΣ DDFS-Driven 19GHz Frequency Synthesizer for FMCW Automotive Radar. 126-591 - Hiroyuki Hirashima, Oh-Kyong Kwon:
Display Electronics. 128-129 - Yong-Sung Park, Do-Youb Kim, Keum-Nam Kim, Yojiro Matsueda, Jong-Hyun Choi, Chul-Kyu Kang, Hye-Dong Kim, Ho Kyoon Chung, Oh-Kyong Kwon:
An 8b Source Driver for 2.0 inch Full-Color Active-Matrix OLEDs Made with LTPS TFTs. 130-592 - Chris J. Brown, Ben Hadwen, Hiromi Kato:
A 2.6 inch VGA LCD with Optical Input Function using a 1-Transistor Active-Pixel Sensor. 132-592 - Yoon-Kyung Choi, Hyoung-Rae Kim, Won-Gab Jung, Min-Soo Cho, Zhong-Yuan Wu, Hyo-Sun Kim, Young-Hun Lee, KyungMyun Kim, Kyu-Sam Lee, Jongseon Kim, Myunghee Lee:
An Integrated LDI with Readout Function for Touch-Sensor-Embedded Display Panels. 134-135 - Chang-Seok Chae, Hanh-Phuc Le, Kwang-Chan Lee, Min-Chul Lee, Gyu-Hyeong Cho, Gyu-Ha Cho:
A Single-Inductor Step-Up DC-DC Switching Converter with Bipolar Outputs for Active Matrix OLED Mobile Display Panels. 136-592 - Jin-Seong Kang, Jin-Ho Kim, Seon-Yung Kim, Jun-Yong Song, Oh-Kyong Kwon, Yuen-Joong Lee, Byung-Hoon Kim, Chan-Woo Park, Kyoung-Soo Kwon, Won-Tae Choi, Sang-Kyeong Yun, Injae Yeo, Kyu-Bum Han, Taek-Soo Kim, Sang-il Park:
A 10b Driver IC for a Spatial Optical Modulator for Full HDTV Applications. 138-592 - Kyung-suc Nah, Hyeokchul Kwon, Jae-Youl Lee, Dukmin Lee, Jun-Seok Han, Young-Hun Lee, Hyeyeong Rho, Jongseon Kim, Bongnam Kim, Myunghee Lee:
A 16.7M Color VGA Display Driver IC with Partial Graphic RAM and 500Mb/s/ch Serial Interface for Mobile a-Si TFT-LCDs. 140-592 - Young-Suk Son, Ji-Hun Kim, Hyun-Ho Cho, Ju-Pyo Hong, Joon-Ho Na, Dae-Seong Kim, Dae-Keun Han, Jin-Cheol Hong, Yong-Joon Jeon, Gyu-Hyeong Cho:
A Column Driver with Low-Power Area-Efficient Push-Pull Buffer Amplifiers for Active-Matrix LCDs. 142-143 - Nicky Lu, C. K. Wang, Philip Wong, Sreedhar Natarajan:
E1 Ultimate Limits of Integrated Electronics. 146-147 - Larry DeVito, Yusuke Ohtomo:
SE3 Last Mile Access Options: PON/DSL/Cable/Wireless. 144-145 - Toru Shimizu, Ram Krishnamurthy:
SE4 Automotive Signal Processing Technologies. 148-149 - Roland Thewes, Dennis Polla:
Biomedical Devices. 150-151 - Maurits Ortmanns, N. Linger, André Rocke, S. Rackow, Marcus Gehrke, Hans-Jürgen Tiedtke:
A 232-Channel Visual Prosthesis ASIC with Production-Compliant Safety and Testability. 152-593 - Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo:
A Fully Integrated Digital Hearing-Aid Chip with Human-Factors Considerations. 154-593 - Mingcui Zhou, Wentai Liu:
A Non-Coherent PSK Receiver with Interference-Canceling for Transcutaneous Neural Implants. 156-593 - Urs Frey, Flavio Heer, René Pedron, Sadik Hafizovic, Frauke Greve, Jan Sedivý, Kay-Uwe Kirstein, Andreas Hierlemann:
An 11k-Electrode 126-Channel High-Density Microelectrode Array to Interact with Electrogenic Cells. 158-593 - Joseph N. Y. Aziz, Roman Genov, Miron Derchansky, Berj L. Bardakjian, Peter L. Carlen:
256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes. 160-594 - Timothy Denison, Kelly Consoer, Andy Kelly, April Hachenburg, Wesley Santa:
A 2.2μW 94nV/√Hz, Chopper-Stabilized Instrumentation Amplifier for EEG Detection in Chronic Implants. 162-594 - Giorgio Ferrari, Fabio Gozzini, Marco Sampietro:
A Current-Sensitive Front-End Amplifier for Nano-Biosensors with a 2MHz BW. 164-165 - Long-Sheng Fan, Shawn S. H. Hsu, Jun-De Jin, Cheng-Vu Hsieh, Wei-Chen Lin, H. C. Hao, Hsin-Li Cheng, Kuo-Chin Hsueh, Chen-Zong Lee:
Miniaturization of Magnetic Resonance Microsystem Components for 3D Cell Imaging. 166-594 - Shu-Jen Han, Heng Yu, Boris Murmann, Nader Pourmand, Shan X. Wang:
A High-Density Magnetoresistive Biosensor Array with Drift-Compensation Mechanism. 168-594 - Thucydides Xanthopoulos, Atila Alvandpour:
Clocking. 170-171 - Alexander V. Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli:
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. 172-173 - Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno:
A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. 174-594 - Yong Liu, Woogeun Rhee, Daniel J. Friedman, Donhee Ham:
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. 176-595 - Chi-Nan Chuang, Shen-Iuan Liu:
A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology. 178-595 - Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda:
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique. 180-595 - Li-min Lee, Chih-Kong Ken Yang:
An Adaptive Low-Jitter LC-Based Clock Distribution. 182-595 - Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. 184-595 - Ali M. Niknejad, Hiroyuki Sakai:
mm-Wave Tranceivers and Building Blocks. 186-187 - Behzad Razavi:
A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider. 188-596 - Sohrab Emami, Chinh H. Doan, Ali M. Niknejad, Robert W. Brodersen:
A Highly Integrated 60GHz CMOS Front-End Receiver. 190-191 - Chi-Hsueh Wang, Hong-Yeh Chang, Pei-Si Wu, Kun-You Lin, Tian-Wei Huang, Huei Wang, Chun-Hsiung Chen:
A 60GHz Low-Power Six-Port Transceiver for Gigabit Software-Defined Transceiver Applications. 192-596 - KaChun Kwok, John R. Long, John J. Pekarik:
A 23-to-29GHz Differentially Tuned Varactorless VCO in 0.13μm CMOS. 194-596 - Chihun Lee, Shen-Iuan Liu:
A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS. 196-596 - Pierre Mayr, Christopher Weyers, Ulrich Langmann:
A 90GHz 65nm CMOS Injection-Locked Frequency Divider. 198-596 - Babak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad:
Low-Power mm-Wave Components up to 104GHz in 90nm CMOS. 200-597 - Arun Natarajan, Brian A. Floyd, Ali Hajimiri:
A Bidirectional RF-Combining 60GHz Phased-Array Front-End. 202-597 - David Su, Bud Taddiken:
TV Tuner / RFID. 204-205 - Manoj Gupta, Supisa Lerstaveesin, David Kang, Bang-Sup Song:
A 48-to-860MHz CMOS Direct-Conversion TV Tuner. 206-597 - Vincent Fillatre, Jean-Robert Tourret, Sébastien Amiot, Maxime Bernard, Mohamed Bouhamame, Claude Caron, Olivier Crand, Alexandre Daubenfeld, Gilles Denise, Thibault Kervaon, Markus Kristen, Luca Lo Coco, Frederic Mercier, Jean Marc Paris, Sébastien Prouet, Vincent Rambeau, Sebastien Robert, Francois Seneschal, Jan van Sinderen, Olivier Susplugas:
A SiP Tuner with Integrated LC Tracking Filter for both Cable and Terrestrial TV Reception. 208-597 - Jan-Michael Stevenson, Philip Hisayasu, Armin Deiss, Buddhika Abesingha, Kim Beumer, José Esquivel:
A Multi-Standard Analog and Digital TV Tuner for Cable and Terrestrial Applications. 210-597 - Takae Sakai, Shinya Ito, Nobuyoshi Kaiki, Atsushi Sakai, Mamoru Okazaki, Masayuki Natsumi, Akira Saito, Kazumasa Kioi, Masato Koutani, Koutani Kagoshima, Shuichi Kawama, Hiroshi Kijima, Shinji Toyoyama, Nobutoshi Matsunaga, Mutsumi Hamaguchi, Hiroshi Kawamura, Kunihiko Iizuka:
A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications. 212-597 - Issy Kipnis, Scott Chiu, Marc Loyer, J. Carrigan, Jan Rapp, Peter Johansson, David Westberg, Jonas Johansson:
A 900MHz UHF RFID Reader Transceiver IC. 214-598 - Ickjin Kwon, Heemun Bang, Kyudon Choi, Sangyoon Jeon, Sungjae Jung, Donghyun Lee, Yunseong Eo, Heungbae Lee, Bongyoung Chung:
A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader. 216-598 - Aminghasem Safarian, Amin Shameli, Ahmadreza Rofougaran, Maryam Rofougaran, Franco De Flaviis:
An Integrated RFID Reader. 218-598 - John T. Stonick, Jri Lee:
Gigabit CDRs Equalizers. 220-221 - Do-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO. 222-598 - Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. 224-598 - Thomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. 226-598 - Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe:
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. 228-599 - Matt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman:
A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver. 230-599 - David Hernandez-Garduno, José Silva-Martínez:
A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells. 232-599 - Zheng Gu, Peter Gregorius, Daniel Kehrer, Lydia Neumann, Evelyn Neuscheler, Thomas Rickes, Hermann Ruckerbauer, Ralf Schledz, Martin Streibl, Jürgen Zielbauer:
Cascading Techniques for a High-Speed Memory Interface. 234-599 - Zhongyuan Chang, Tatsuji Matsuura:
ΔΣ ADCs and Converter Techniques. 236-237 - Lucien J. Breems, Robert Rutten, Robert H. M. van Veldhoven, Gerard van der Weide, Henk A. H. Termeer:
A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band. 238-599 - Thomas Christen, Thomas Burger, Qiuting Huang:
A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD. 240-599 - Sotir Ouzounov, Robert H. M. van Veldhoven, Corné Bastiaansen, K. Vongehr, Roland Van Wegberg, Govert Geelen, Lucien J. Breems, Arthur H. M. van Roermund:
A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS. 242-600 - Bas M. Putter:
A 5, th-order CT/DT Multi-Mode ΔΣ Modulator. 244-245 - Jan Craninckx, Geert Van der Plas:
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. 246-600 - M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske:
A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS. 248-600 - Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori:
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS. 250-600 - Steffen Paul, Tzi-Dar Chiueh:
Baseband Signal Processing. 252-253 - Ping-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang:
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. 254-600 - Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. 256-600 - Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens:
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. 258-601 - Chiara Martelli, Robert Reutemann, Christian Benkeser, Qiuting Huang:
A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End. 260-601 - Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair,