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ORCIDISSCC 2007: San Francisco, CA, USA
- 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007, Digest of Technical Papers, San Francisco, CA, USA, February 11-15, 2007. IEEE 2007, ISBN 1-4244-0853-9
- J. Morris Chang:
Foundry Future: Challenges in the 21st Century. 18-23 - Lewis W. Counts:
Analog and Mixed-Signal Innovation: The Process-Circuit-System-Application Interaction. 24-30 - Joël Hartmann:
Towards a New Nanoelectronic Cosmology. 31-37 - Sung Min Park, Yuriy M. Greshishchev:
Optical Communications. 40-41 - Adithyaram Narasimha, Behnam Analui, Yi Liang, Thomas J. Sleboda, Cary Gunn:
A Fully Integrated 4ÿ10Gb/s DWDM Optoelectronic Transceiver in a standard 0.13μm CMOS SOI. 42-586 - Samuel Palermo, Azita Emami-Neyestanak
, Mark Horowitz:
A 90nm CMOS 16Gb/s Transceiver for Optical Interconnects. 44-586 - Jri Lee, Mingchung Liu:
A 20Gb/s Burst-Mode CDR Circuit Using Injection-Locking Technique. 46-586 - Lan-Chou Cho, Chihun Lee, Shen-Iuan Liu:
A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS. 48-586 - Quan Le, Sang-Gug Lee, Ho-Yong Kang, Sang-Hoon Chang:
A CMOS Burst-Mode TIA with Step AGC and Selective Internally Created Reset for 1.25Gb/s EPON. 50-51 - Chia-Ming Tsai, Wen-Tsao Chen:
A 40mW 3.5kΩ 3Gb/s CMOS Differential Transimpedance Amplifier Using Negative-Impedance Compensation. 52-586 - Chih-Fan Liao, Shen-Iuan Liu:
A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS. 54-586 - Kwisung Yoo, Dongmyung Lee, Gunhee Han, Sung Min Park, Wonseok Oh:
A 1.2V 5.2mW 40dB 2.5Gb/s Limiting Amplifier in 0.18μm CMOS Using Negative-Impedance Compensation. 56-57 - Axel Thomsen, Ligang Zhang, Doug Frey, Q. Yu, Lizhong Sun, Akhil K. Garlapati, R. Hulfachor, Douglas F. Pastorello, Richard J. Juhn:
A Fractional-N PLL for SONET-Quality Clock-Syntlhesis Applicationis. 58-587 - Eugenio Cantatore, Shuichi Tahara:
TD: Emerging Devices Devices and Circuits. 60-61 - Hélène Lhermet, Cyril Condemine, Marc Plissonnier, Raphael Salot, Patrick Audebert, Marion Rosset:
Efficient Power Management Circuit: Thermal Energy Harvesting to Above-IC Microbattery Energy Storage. 62-587 - Yogesh K. Ramadass, Anantha P. Chandrakasan:
Minimum Energy Tracking Loop with Embedded DC-DC Converter Delivering Voltages down to 250mV in 65nm CMOS. 64-587 - Makoto Ikeda, Taku Sogabe, Ken Ishii, Masayuki Mizuno, Toru Nakura, Koichi Nose, Kunihiro Asada:
LAGS System Using Data/Instruction Grain Power Control. 66-587 - Zhihong Chen, Jörg Appenzeller, Paul M. Solomon, Yu-Ming Lin, Phaedon Avouris:
Gate Work Function Engineering for Nanotube-Based Circuits. 68-587 - Jie Deng, Nishant Patil, Koungmin Ryu, Alexander Badmaev, Chongwu Zhou, Subhasish Mitra, H.-S. Philip Wong:
Carbon Nanotube Transistor Circuits: Circuit-Level Performance Benchmarking and Design Options for Living with Imperfections. 70-588 - Ivan Nausieda, Kyungbum Kevin Ryu, Ioannis Kymissis, Akintunde Ibitayo Akinwande, Vladimir Bulovic, Charles G. Sodini:
An Organic Imager for Flexible Large Area Electronics. 72-73 - Reiji Hattori, Michihiro Asakawa, Yoshitomo Masuda, Norio Nihei, Akihiko Yokoo, Shuhei Yamada, Itsuo Tanuma:
Passive-Matrix Flexible Electronic Paper Using Quick-Response Liquid Powder Display (QR-LPD) Technollogy and Custom Driver Circuits. 74-588 - Nikolaus Klemmer, Satoshi Tanaka:
RF Building Blocks. 76-77 - Amirpouya Kavousian, David K. Su, Bruce A. Wooley:
A Digitally Modulated Polar CMOS PA with 20MHz Signal BW. 78-588 - Francesco Carrara, Calogero D. Presti, Antonino Scuderi, Carmelo Santagati, Giuseppe Palmisano:
A 3W 55% PAE CMOS PA with Closed-Loop 20: 1 VSWR Protection. 80-588 - Jennifer Kitchen, Wing-Yee Chu, Ilker Deligoz, Sayfe Kiaei, Bertan Bakkaloglu:
Combined Linear and Δ-Modulated Switched-Mode PA Supply Modulator for Polar Transmitters. 82-588 - Hooman Darabi:
A Blocker Filtering Technique for Wireless Receivers. 84-588 - Krzysztof Dufrene, Zdravko Boos, Robert Weigel:
A 0.13μm 1.5V CMOS I/Q Downconverter with Digital Adaptive IIP2 Calibration. 86-589 - Hong-Sing Kao, Ming-Jen Yang, Tai-Cheng Lee:
A Delay-Line-Based GFSK Demodulator for Low-IF Receivers. 88-589 - Aleksander Dec, Ken Suyama, Tomomitsu Kitamura:
A 4.5GHz LC-VCO with Self-Regulating Technique. 90-589 - Giuseppe Cusmai, Matteo Repossi, Guido Albasini, Francesco Svelto:
A 3.2-to-7.3GHz Quadrature Oscillator with Magnetic Tuning. 92-589 - Stefan Rusu, Jim Warnock:
Microprocessors. 94-95 - Joshua Friedrich, Bradley D. McCredie, Norman K. James, Bill Huott, Brian W. Curran, Eric Fluhr, Gaurav Mittal, Eddie Chan, Yuen H. Chan, Donald W. Plass, Sam G. Chu, Hung Q. Le, Leo Clark, John R. Ripley, Scott A. Taylor, Jack DiLullo, Mary Yvonne Lanzerotti:
Design of the Power6 Microprocessor. 96-97 - Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar:
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. 98-589 - Yutaka Yoshida, Tatsuya Kamei, Kiyoshi Hayase, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa, Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka, Kiwamu Takada, Keiji Kimura, Hironori Kasahara:
A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption. 100-590 - J. Dorsey, S. Searles, Michael Ciraula, S. Johnson, N. Bujanos, D. Wu, M. Braganza, S. Meyers, E. Fang, R. Kumar:
An Integrated Quad-Core Opteron Processor. 102-103 - Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong:
A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems. 104-105 - Nabeel Sakran, Marcelo Yuffe, Moty Mehalel, Jack Doweck, Ernest Knoll, Avi Kovacs:
The Implementation of the 65nm Dual-Core 64b Merom Processor. 106-590 - Umesh Gajanan Nawathe, Mahmudul Hassan, Lynn Warriner, King C. Yen, Bharat Upputuri, David Greenhill, Ashok Kumar, Heechoul Park:
An 8-Core 64-Thread 64b Power-Efficient SPARC SoC. 108-590 - Sang-Gug Lee, Ranjit Gharpurey:
UWB and mm-Wave Communications Systems. 110-111 - Jos Bergervoet, Harish Kundur Subramaniyan, S. Lee, Domine Leenaerts, Remco van de Beek, Gerard van der Weide, Raf Roovers:
A WiMedia-Compliant UWB Transceiver in 65nm CMOS. 112-590 - Yuanjin Zheng, King-Wah Wong, M. Annamalai Asaru, Dan Shen, Wen Hu Zhao, Yen Ju The, P. Andrew, Fujiang Lin, Wooi Gan Yeoh, Rajinder Singh:
A 0.18μm CMOS Dual-Band UWB Transceiver. 114-590 - Fred S. Lee, Anantha P. Chandrakasan:
A 2.5nJ/b 0.65V 3-to-5GHz Subbanded UWB Receiver in 90nm CMOS. 116-590 - David D. Wentzloff, Anantha P. Chandrakasan:
A 47pJ/pulse 3.1-to-5GHz All-Digital UWB Transmitter in 90nm CMOS. 118-591 - Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx:
A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a. 120-591 - Ville Saari, Mikko Kaltiokallio, Saska Lindfors, Jussi Ryynänen, Kari Halonen:
A 1.2V 240MHz CMOS Continuous-Time Low-Pass Filter for a UWB Radio Receiver. 122-591 - Harish Krishnaswamy, Hossein Hashemi:
A Fully Integrated 24GHz 4-Channel Phased-Array Transceiver in 0.13μm CMOS Based on a Variable-Phase Ring Oscillator and PLL Architecture. 124-591 - Hoon Hee Chung, Umar Lyles, Tino Copani, Bertan Bakkaloglu, Sayfe Kiaei:
A Bandpass ΔΣ DDFS-Driven 19GHz Frequency Synthesizer for FMCW Automotive Radar. 126-591 - Hiroyuki Hirashima, Oh-Kyong Kwon:
Display Electronics. 128-129 - Yong-Sung Park, Do-Youb Kim, Keum-Nam Kim, Yojiro Matsueda, Jong-Hyun Choi, Chul-Kyu Kang, Hye-Dong Kim, Ho Kyoon Chung, Oh-Kyong Kwon:
An 8b Source Driver for 2.0 inch Full-Color Active-Matrix OLEDs Made with LTPS TFTs. 130-592 - Chris J. Brown, Ben Hadwen, Hiromi Kato:
A 2.6 inch VGA LCD with Optical Input Function using a 1-Transistor Active-Pixel Sensor. 132-592 - Yoon-Kyung Choi, Hyoung-Rae Kim, Won-Gab Jung, Min-Soo Cho, Zhong-Yuan Wu, Hyo-Sun Kim, Young-Hun Lee, KyungMyun Kim, Kyu-Sam Lee, Jongseon Kim, Myunghee Lee:
An Integrated LDI with Readout Function for Touch-Sensor-Embedded Display Panels. 134-135 - Chang-Seok Chae, Hanh-Phuc Le, Kwang-Chan Lee, Min-Chul Lee, Gyu-Hyeong Cho, Gyu-Ha Cho:
A Single-Inductor Step-Up DC-DC Switching Converter with Bipolar Outputs for Active Matrix OLED Mobile Display Panels. 136-592 - Jin-Seong Kang, Jin-Ho Kim, Seon-Yung Kim, Jun-Yong Song, Oh-Kyong Kwon, Yuen-Joong Lee, Byung-Hoon Kim, Chan-Woo Park, Kyoung-Soo Kwon, Won-Tae Choi, Sang-Kyeong Yun, Injae Yeo, Kyu-Bum Han, Taek-Soo Kim, Sang-il Park:
A 10b Driver IC for a Spatial Optical Modulator for Full HDTV Applications. 138-592 - Kyung-suc Nah, Hyeokchul Kwon, Jae-Youl Lee, Dukmin Lee, Jun-Seok Han, Young-Hun Lee, Hyeyeong Rho, Jongseon Kim, Bongnam Kim, Myunghee Lee:
A 16.7M Color VGA Display Driver IC with Partial Graphic RAM and 500Mb/s/ch Serial Interface for Mobile a-Si TFT-LCDs. 140-592 - Young-Suk Son, Ji-Hun Kim, Hyun-Ho Cho, Ju-Pyo Hong, Joon-Ho Na, Dae-Seong Kim, Dae-Keun Han, Jin-Cheol Hong, Yong-Joon Jeon, Gyu-Hyeong Cho:
A Column Driver with Low-Power Area-Efficient Push-Pull Buffer Amplifiers for Active-Matrix LCDs. 142-143 - Nicky Lu, C. K. Wang, Philip Wong, Sreedhar Natarajan:
E1 Ultimate Limits of Integrated Electronics. 146-147 - Larry DeVito, Yusuke Ohtomo:
SE3 Last Mile Access Options: PON/DSL/Cable/Wireless. 144-145 - Toru Shimizu, Ram Krishnamurthy:
SE4 Automotive Signal Processing Technologies. 148-149 - Roland Thewes, Dennis Polla:
Biomedical Devices. 150-151 - Maurits Ortmanns, N. Linger, André Rocke, S. Rackow, Marcus Gehrke, Hans-Jürgen Tiedtke:
A 232-Channel Visual Prosthesis ASIC with Production-Compliant Safety and Testability. 152-593 - Sunyoung Kim, Seungjin Lee, Namjun Cho, Seong-Jun Song, Hoi-Jun Yoo:
A Fully Integrated Digital Hearing-Aid Chip with Human-Factors Considerations. 154-593 - Mingcui Zhou, Wentai Liu:
A Non-Coherent PSK Receiver with Interference-Canceling for Transcutaneous Neural Implants. 156-593 - Urs Frey, Flavio Heer, René Pedron, Sadik Hafizovic, Frauke Greve, Jan Sedivý, Kay-Uwe Kirstein, Andreas Hierlemann:
An 11k-Electrode 126-Channel High-Density Microelectrode Array to Interact with Electrogenic Cells. 158-593 - Joseph N. Y. Aziz, Roman Genov, Miron Derchansky, Berj L. Bardakjian, Peter L. Carlen:
256-Channel Neural Recording Microsystem with On-Chip 3D Electrodes. 160-594 - Timothy Denison, Kelly Consoer, Andy Kelly, April Hachenburg, Wesley Santa:
A 2.2μW 94nV/√Hz, Chopper-Stabilized Instrumentation Amplifier for EEG Detection in Chronic Implants. 162-594 - Giorgio Ferrari, Fabio Gozzini, Marco Sampietro:
A Current-Sensitive Front-End Amplifier for Nano-Biosensors with a 2MHz BW. 164-165 - Long-Sheng Fan, Shawn S. H. Hsu, Jun-De Jin, Cheng-Vu Hsieh, Wei-Chen Lin, H. C. Hao, Hsin-Li Cheng, Kuo-Chin Hsueh, Chen-Zong Lee:
Miniaturization of Magnetic Resonance Microsystem Components for 3D Cell Imaging. 166-594 - Shu-Jen Han, Heng Yu, Boris Murmann, Nader Pourmand, Shan X. Wang:
A High-Density Magnetoresistive Biosensor Array with Drift-Compensation Mechanism. 168-594 - Thucydides Xanthopoulos, Atila Alvandpour:
Clocking. 170-171 - Alexander V. Rylyakov, José A. Tierno, George English, Daniel J. Friedman, M. Megheli:
A Wide Power-Supply Range (0.5V-to-1.3V) Wide Tuning Range (500 MHz-to-8 GHz) All-Static CMOS AD PLL in 65nm SOI. 172-173 - Shunichi Kaeriyama, Mikihiro Kajita, Masayuki Mizuno:
A 1-to-2GHz 4-Phase On-Chip Clock Generator with Timing-Margin Test Capability. 174-594 - Yong Liu, Woogeun Rhee, Daniel J. Friedman, Donhee Ham:
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs. 176-595 - Chi-Nan Chuang, Shen-Iuan Liu:
A 40GHz DLL-Based Clock Generator in 90nm CMOS Technology. 178-595 - Mamoru Sasaki, Mitsuru Shiozaki, Atsushi Mori, Atsushi Iwata, Hiroaki Ikeda:
12GHz Low-Area-Overhead Standing-Wave Clock Distribution with Inductively-Loaded and Coupled Technique. 180-595 - Li-min Lee, Chih-Kong Ken Yang:
An Adaptive Low-Jitter LC-Based Clock Distribution. 182-595 - Dongsuk Shin, Janghoon Song, Hyunsoo Chae, Kwan-Weon Kim, Young-Jung Choi, Chulwoo Kim:
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC. 184-595 - Ali M. Niknejad, Hiroyuki Sakai:
mm-Wave Tranceivers and Building Blocks. 186-187 - Behzad Razavi:
A mm-Wave CMOS Heterodyne Receiver with On-Chip LO and Divider. 188-596 - Sohrab Emami, Chinh H. Doan, Ali M. Niknejad, Robert W. Brodersen:
A Highly Integrated 60GHz CMOS Front-End Receiver. 190-191 - Chi-Hsueh Wang, Hong-Yeh Chang, Pei-Si Wu, Kun-You Lin, Tian-Wei Huang, Huei Wang, Chun-Hsiung Chen:
A 60GHz Low-Power Six-Port Transceiver for Gigabit Software-Defined Transceiver Applications. 192-596 - KaChun Kwok, John R. Long, John J. Pekarik:
A 23-to-29GHz Differentially Tuned Varactorless VCO in 0.13μm CMOS. 194-596 - Chihun Lee, Shen-Iuan Liu:
A 58-to-60.4GHz Frequency Synthesizer in 90nm CMOS. 196-596 - Pierre Mayr, Christopher Weyers, Ulrich Langmann:
A 90GHz 65nm CMOS Injection-Locked Frequency Divider. 198-596 - Babak Heydari, Mounir Bohsali, Ehsan Adabi, Ali M. Niknejad:
Low-Power mm-Wave Components up to 104GHz in 90nm CMOS. 200-597 - Arun Natarajan, Brian A. Floyd, Ali Hajimiri:
A Bidirectional RF-Combining 60GHz Phased-Array Front-End. 202-597 - David Su, Bud Taddiken:
TV Tuner / RFID. 204-205 - Manoj Gupta, Supisa Lerstaveesin, David Kang, Bang-Sup Song:
A 48-to-860MHz CMOS Direct-Conversion TV Tuner. 206-597 - Vincent Fillatre, Jean-Robert Tourret, Sébastien Amiot, Maxime Bernard, Mohamed Bouhamame, Claude Caron, Olivier Crand, Alexandre Daubenfeld, Gilles Denise, Thibault Kervaon, Markus Kristen, Luca Lo Coco, Frederic Mercier, Jean Marc Paris, Sébastien Prouet, Vincent Rambeau, Sebastien Robert, Francois Seneschal, Jan van Sinderen, Olivier Susplugas:
A SiP Tuner with Integrated LC Tracking Filter for both Cable and Terrestrial TV Reception. 208-597 - Jan-Michael Stevenson, Philip Hisayasu, Armin Deiss, Buddhika Abesingha, Kim Beumer, José Esquivel:
A Multi-Standard Analog and Digital TV Tuner for Cable and Terrestrial Applications. 210-597 - Takae Sakai, Shinya Ito, Nobuyoshi Kaiki, Atsushi Sakai, Mamoru Okazaki, Masayuki Natsumi, Akira Saito, Kazumasa Kioi, Masato Koutani, Koutani Kagoshima, Shuichi Kawama, Hiroshi Kijima, Shinji Toyoyama, Nobutoshi Matsunaga, Mutsumi Hamaguchi, Hiroshi Kawamura, Kunihiko Iizuka:
A Digital TV Receiver RF and BB Chipset with Adaptive Bias-Current Control for Mobile Applications. 212-597 - Issy Kipnis, Scott Chiu, Marc Loyer, J. Carrigan, Jan Rapp, Peter Johansson, David Westberg, Jonas Johansson:
A 900MHz UHF RFID Reader Transceiver IC. 214-598 - Ickjin Kwon, Heemun Bang, Kyudon Choi, Sangyoon Jeon, Sungjae Jung, Donghyun Lee, Yunseong Eo, Heungbae Lee, Bongyoung Chung:
A Single-Chip CMOS Transceiver for UHF Mobile RFID Reader. 216-598 - Aminghasem Safarian, Amin Shameli, Ahmadreza Rofougaran, Maryam Rofougaran, Franco De Flaviis:
An Integrated RFID Reader. 218-598 - John T. Stonick, Jri Lee:
Gigabit CDRs Equalizers. 220-221 - Do-Hwan Oh, Deok-Soo Kim, Suhwan Kim, Deog-Kyoon Jeong, Wonchan Kim:
A 2.8Gb/s All-Digital CDR with a 10b Monotonic DCO. 222-598 - Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker:
A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX. 224-598 - Thomas Toifl, Christian Menolfi, Peter Buchmann, Christoph Hagleitner, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. 226-598 - Brian S. Leibowitz, Jade Kizer, Haechang Lee, Fred Chen, Andrew Ho, Metha Jeeradit, Akash Bansal, Trey Greer, Simon Li, Ramin Farjad-Rad, William F. Stonecypher, Yohan Frans, Barry Daly, Fred Heaton, Bruno W. Garlepp, Carl W. Werner, Nhat Nguyen, Vladimir Stojanovic, Jared Zerbe:
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR. 228-599 - Matt Park, John F. Bulzacchelli, Michael P. Beakes, Daniel J. Friedman:
A 7Gb/s 9.3mW 2-Tap Current-Integrating DFE Receiver. 230-599 - David Hernandez-Garduno, José Silva-Martínez:
A CMOS 1Gb/s 5-Tap Transversal Equalizer Based on Inductorless 3rd-Order Delay Cells. 232-599 - Zheng Gu, Peter Gregorius, Daniel Kehrer, Lydia Neumann, Evelyn Neuscheler, Thomas Rickes, Hermann Ruckerbauer, Ralf Schledz, Martin Streibl, Jürgen Zielbauer:
Cascading Techniques for a High-Speed Memory Interface. 234-599 - Zhongyuan Chang, Tatsuji Matsuura:
ΔΣ ADCs and Converter Techniques. 236-237 - Lucien J. Breems, Robert Rutten, Robert H. M. van Veldhoven, Gerard van der Weide, Henk A. H. Termeer:
A 56mW CT Quadrature Cascaded ΣΔ Modulator with 77dB DR in a Near Zero-IF 20MHz Band. 238-599 - Thomas Christen, Thomas Burger, Qiuting Huang:
A 0.13μm CMOS EDGE/UMTS/WLAN Tri-Mode ΔΣ ADC with -92dB THD. 240-599 - Sotir Ouzounov, Robert H. M. van Veldhoven, Corné Bastiaansen, K. Vongehr, Roland Van Wegberg, Govert Geelen, Lucien J. Breems, Arthur H. M. van Roermund:
A 1.2V 121-Mode CT ΔΣ Modulator for Wireless Receivers in 90nm CMOS. 242-600 - Bas M. Putter:
A 5, th-order CT/DT Multi-Mode ΔΣ Modulator. 244-245 - Jan Craninckx, Geert Van der Plas:
A 65fJ/Conversion-Step 0-to-50MS/s 0-to-0.7mW 9b Charge-Sharing SAR ADC in 90nm Digital CMOS. 246-600 - M. Hesener, T. Eichler, A. Hanneberg, D. Herbison, F. Kuttner, H. Wenske:
A 14b 40MS/s Redundant SAR ADC with 480MHz Clock in 0.13pm CMOS. 248-600 - Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico, Luca Gori:
A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS. 250-600 - Steffen Paul, Tzi-Dar Chiueh:
Baseband Signal Processing. 252-253 - Ping-Ying Wang, Meng-Ta Yang, Shang-Ping Chen, Meng-Hsueh Lin, Jing-Bing Yang:
RTL-based Clock Recovery Architecture with All-Digital Duty-Cycle Correction. 254-600 - Mark A. Anders, Sanu Mathew, Steven Hsu, Ram Krishnamurthy, Shekhar Borkar:
A 1.9Gb/s 358mW 16-to-256 State Reconfigurable Viterbi Accelerator in 90nm CMOS. 256-600 - Didier Lattard, Edith Beigné, Christian Bernard, Catherine Bour, Fabien Clermidy, Yves Durand, Jean Durupt, Didier Varreau, Pascal Vivet, Pierre Penard, Arnaud Bouttier, Friedbert Berens:
A Telecom Baseband Circuit based on an Asynchronous Network-on-Chip. 258-601 - Chiara Martelli, Robert Reutemann, Christian Benkeser, Qiuting Huang:
A 50mW HSDPA Baseband Receiver ASIC with Multimode Digital Front-End. 260-601 - Sanjive Agarwala, Arjun Rajagopal, Anthony M. Hill, Mayur Joshi, Steven Mullinnix, Timothy Anderson, Raguram Damodaran, Lewis Nardini, Paul Wiley, Peter Groves, John Apostol, Michael Gill, Jose Flores, Abhijeet Chachad, Alan Hales, Kai Chirca, Krishna Panda, Rama Venkatasubramanian, Patrick Eyres, Rajasekhar Velamuri, Anand Rajaram, Manjeri Krishnan, Jonathan Nelson, Jose Frade, Mujibur Rahman, Nuruddin Mahmood, Usha Narasimha, Snehamay Sinha, Sridhar Krishnan, William Webster, Duc Bui, Shriram Moharil, Neil Common, Rejitha Nair, Rajesh Ramanujam, Monica Ryan:
A 65nm C64x+ Multi-Core DSP Platform for Communications Infrastructure. 262-601 - Markus Hammes, Christian Kranz, Jens Kissing, Dietolf Seippel, Pierre-Henri Bonnaud, Enrico Pelos:
A GSM Baseband Radio in 0.13μm CMOS with Fully Integrated Power-Management. 264-602 - Paul Petrus, Qinfang Sun, Sam Ng, James Cho, Ning Zhang, Don Breslin, Matt Smith, Bill McFarland, Sundar Sankaran, John Thomson, Rich Mosko, Augusta Chen, Tuofu Lu, Yi-Hsiu Wang, Xioaru Zhang, Dave Nakahira, Yixiang Li, Ravi Subramanian, Arun Venkataraman, Prem Kumar, Sudhakar Swaminathan, Jeffrey M. Gilbert, Won-Joon Choi, Huanchun Ye:
An Integrated Draft 802.11n Compliant MIMO Baseband and MAC Processor. 266-602 - Michel Harrand, Liang-Gee Chen:
Multimedia and Parrallel Signal Processors. 268-269 - Anteneh A. Abbo, Richard P. Kleihorst, Vishal Choudhary, Leo Sevat, Paul Wielage, Sebastien Mouy, Marc J. M. Heijligers:
XETAL-II: A 107 GOPS, 600mW Massively-Parallel Processor for Video Scene Analysis. 270-602 - Brucek Khailany, Ted Williams, Jim Lin, Eileen Long, Mark Rygh, DeForest Tovey, William J. Dally:
A Programmable 512 GOPS Stream Processor for Signal, Image, and Video Processing. 272-602 - Masayuki Ito, Toshihiro Hattori, Takahiro Irita, Ken Tatezawa, Fumihito Tanaka, Kenji Hirose, Shinichi Yoshioka, Koji Ohno, Reiko Tsuchihashi, Minoru Sakata, Masayuki Yamamoto, Yuji Aral:
A 390MHz Single-Chip Application and Dual-Mode Baseband Processor in 90nm Triple-Vt CMOS. 274-602 - Seok-Hoon Kim, Jae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Kyusik Chung, Han Shin Lim, HyunWook Park, Lee-Sup Kim:
A 36fps SXGA 3D Display Processor with a Programmable 3D Graphics Rendering Engine. 276-602 - Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seungjin Lee, Hoi-Jun Yoo:
A 52.4mW 3D Graphics Processor with 141Mvertices/s Vertex Shader and 3 Power Domains of Dynamic Voltage and Frequency Scaling. 278-603 - Hsiu-Cheng Chang, Jia-Wei Chen, Ching-Lung Su, Yao-Chang Yang, Yao Li, Chun-Hao Chang, Ze-Min Chen, Wei-Sen Yang, Chien-Chang Lin, Ching-Wen Chen, Jinn-Shyan Wang, Jiun-In Guo:
A 7mW-to-183mW Dynamic Quality-Scalable H.264 Video Encoder Chip. 280-603 - Chih-Da Chien, Chien-Chang Lin, Yi-Hung Shih, He-Chun Chen, Chia-Jui Huang, Cheng-Yen Yu, Chih-Liang Chen, Ching-Hwa Cheng, Jiun-In Guo:
A 252kgate/71mW Multi-Standard Multi-Channel Video Decoder for High Definition Video Applications. 282-603 - Alice Wang, Jos Huisken:
Power Distribution and Management. 284-285 - Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor:
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. 286-603 - Mitsuya Fukazawa, Tetsuro Matsuno, Toshifumi Uemura, Rei Akiyama, Tetsuya Kagemoto, Hiroshi Makino, Hidehiro Takata, Makoto Nagata:
Fine-Grained In-Circuit Continuous-Time Probing Technique of Dynamic Supply Variations in SoCs. 288-603 - Tomio Sato, Atsuki Inoue, Tetsuyoshi Shiota, Tomoko Inoue, Yukihito Kawabe, Tetsutaro Hashimoto, Toshifumi Imamura, Yoshitaka Murasaka, Makoto Nagata, Atsushi Iwata:
On-Die Supply-Voltage Noise Sensor with Real-Time Sampling Mode for Low-Power Processor Applications. 290-603 - James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De:
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. 292-604 - Jinn-Shyan Wang, Jian-Shiun Chen, Yi-Ming Wang, Chingwei Yeh:
A 230mV-to-500mV 375KHz-to-16MHz 32b RISC Core in 0.18μm CMOS. 294-604 - Makoto Saen, Kenichi Osada, Satoshi Misaka, Tetsuya Yamada, Yoshitaka Tsujimoto, Yuki Kondo, Tatsuya Kamei, Yutaka Yoshida, Ei Nagahama, Yusuke Nitta, Takayasu Ito, Tadashi Kameyama, Naohiko Irie:
Embedded SoC Resource Manager to Control Temperature and Data Bandwidth. 296-604 - Norman K. James, Phillip J. Restle, Joshua Friedrich, Bill Huott, Bradley D. McCredie:
Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor. 298-604 - Vadim Gutnik, Stefan Heinen:
Analog Techniques and PLLs. 300-301 - Ashok Swaminathan, Kevin J. Wang, Ian Galton:
A Wide-Bandwidth 2.4GHz ISM-Band Fractional-N PLL with Adaptive Phase-Noise Cancellation. 302-604 - Shih-An Yu, Peter R. Kinget:
A 0.65V 2.5GHz Fractional-N Frequency Synthesizer in 90nm CMOS. 304-604 - Young-Sang Kim, Seung-Jin Park, Yong-Sub Kim, Dong-Bi Jang, Seh-Woong Jeong, Hong-June Park, Jae-Yoon Sim:
A 40-to-800MHz Locking Multi-Phase DLL. 306-605 - Shaishav Desai, Pradeep Trivedi, Vincent Von Kanael:
A Dual-Supply 0.2-to-4GHz PLL Clock Multiplier in a 65nm Dual-Oxide CMOS Process. 308-605 - WooYoung Jung, HyoungChul Choi, ChangWon Jeong, KwiYoung Kim, WooSeok Kim, HaJun Jeon, GyeSoo Koo, Jihyun Kim, JinHo Seo, MyeongLyong Ko, JaeWhui Kim:
A 1.2mW 0.02mm2 2GHz Current-Controlled PLL Based on a Self-Biased Voltage-to-Current Converter. 310-605 - Fadi H. Gebara, Jeremy D. Schaub, Tuyet Nguyen, Jarom Peña, Ivan Vo, David Boerstler, Kevin J. Nowka:
A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology. 312-313 - Daniël Schinkel, Eisse Mensink, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
A Double-Tail Latch-Type Voltage Sense Amplifier with 18ps Setup+Hold Time. 314-605 - Bernhard Goll, Horst Zimmermann:
A 0.12μm CMOS Comparator Requiring 0.5V at 600MHz and 1.5V at 6GHz. 316-605 - Matti Paavola, Mika Kämäräinen, Jere A. M. Järvinen, Mikko Saukoski, Mika Laiho, Kari Halonen:
A 62μA Interface ASIC for a Capacitive 3-Axis Micro-Accelerometer. 318-605 - Kevin Zhang, Hiroyuki Yamauchi:
SRAM. 320-321 - Jürgen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel:
Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V. 322-606 - Yih Wang, Hong Jo Ahn, Uddalak Bhattacharya, Tom Coan, Fatih Hamzaoglu, Walid M. Hafez, Chia-Hong Jan, Pramod Kolar, Sarvesh H. Kulkarni, Jie-Feng Lin, Yong-Gee Ng, Ian Post, Liqiong Wei, Yih Zhang, Kevin Zhang, Mark Bohr:
A 1.1GHz 12μA/Mb-Leakage SRAM Design in 65nm Ultra-Low-Power CMOS with Integrated Leakage Reduction for Mobile Applications. 324-606 - Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara:
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations. 326-606 - Naveen Verma, Anantha P. Chandrakasan:
A 65nm 8T Sub-Vt SRAM Employing Sense-Amplifier Redundancy. 328-606 - Tony Tae-Hyoung Kim, Jason Liu, John Keane, Chris H. Kim:
A High-Density Subthreshold SRAM with Data-Independent Bitline Leakage and Virtual Ground Replica Scheme. 330-606 - Bo Zhai, David T. Blaauw, Dennis Sylvester, Scott Hanson:
A Sub-200mV 6T SRAM in 0.13μm CMOS. 332-606 - Tony Montalvo, Aarno Pärssinen:
Cellular and Multi-Mode Transceivers. 334-335 - Christopher Jones, Bernard Tenbroek, Paul Fowers, Christophe Beghein, Jonathan Strange, Federico Beffa, Dimitris Nalbantis:
Direct-Conversion WCDMA Transmitter with 163dBc/Hz Noise at 190MHz Offset. 336-607 - Dimitris Papadopoulos, Qiuting Huang:
A Linear Uplink WCDMA Modulator with 156dBc/Hz Downlink SNR. 338-607 - Petri Eloranta, Pauli Seppinen, Sami Kallioinen, Tuomas Saarela, Aarno Pärssinen:
A WCDMA Transmitter in 0.13μm CMOS Using Direct-Digital RF Modulator. 340-607 - Josef Zipper, Rastislav Vazny, Linus Maurer, Michael Wilhelm, Thomas Greifeneder, Andreas Holm:
A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13μm CMOS. 342-607 - Zhenbiao Li, Wenhai Ni, Jie Ma, Ming Li, Dequn Ma, Dong Zhao, Jesal Mehta, David Hartman, Xianfeng Wang, Ken K. O, Kai Che:
A Dual-Band CMOS Transceiver for 3G TD-SCDMA. 344-607 - Jan Craninckx, M. Liu, Dries Hauspie, Vito Giannini, T. Kim, Jaehoon Lee, Mike Libois, Björn Debaillie, Charlotte Soens, Andrea Baschirotto, Joris Van Driessche, Liesbet Van der Perre, Peter Vanbekbergen:
A Fully Reconfigurable Software-Defined Radio Transceiver in 0.13μm CMOS. 346-607 - Yukinori Akamine, Satoshi Tanaka, Manabu Kawabe, Takao Okazaki, Yasuo Shima, Masahiko Yamamoto, Ryoichi Takano, Yasuyuki Kimura:
A Polar Loop Transmitter with Digital Interface including a Loop-Bandwidth Calibration System. 348-608 - Nishiki Mizusawa, Shinichiro Tsuda, Tomoari Itagaki, Kotaro Takagi:
A Polynomial-Predistortion Transmitter for WCDMA. 350-608 - Mark A. Ferriss, Michael P. Flynn:
A 14mW Fractional-N PLL Modulator with an Enhanced Digital Phase Detector and Frequency Switching Scheme. 352-608 - Chris Van Hoof, Philippe Royannez:
TD: Proximity Data and Power Transmission. 354-355 - Alberto Fazzi, Roberto Canegallo, Luca Ciccarelli, Luca Magagni, Federico Natali, Erik Jung, Pier Luigi Rolandi, Roberto Guerrieri:
3D Capacitive Interconnections with Mono- and Bi-Directional Capabilities. 356-608 - Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda:
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping. 358-608 - Hiroki Ishikuro, Toshihiko Sugahara, Tadahiro Kuroda:
An Attachable Wireless Chip Access Interface for Arbitrary Data Rate Using Pulse-Based lnductive-Coupling through LSI Package. 360-608 - Makoto Takamiya, Tsuyoshi Sekitani, Yoshio Miyamoto, Yoshiaki Noguchi, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai:
Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches. 362-609 - Jui-Yuan Yu, Ching-Che Chung, Wan-Chun Liao, Chen-Yi Lee:
A sub-mW Multi-Tone CDMA Baseband Transceiver Chipset for Wireless Body Area Network Applications. 364-609 - Seong-Jun Song, Namjun Cho, Sunyoung Kim, Jerald Yoo, Sungdae Choi, Hoi-Jun Yoo:
A 0.9V 2.6mW Body-Coupled Scalable PHY Transceiver for Body Sensor Applications. 366-609 - David Hopkins, Alex Chow, Robert Bosnyak, Bill Coates, Jo C. Ebergen, Scott Fairbanks, Jonathan Gainsley, Ron Ho, Jon K. Lexau, Frankie Liu, Tarik Ono, Justin Schauer, Ivan E. Sutherland, Robert J. Drost:
Circuit Techniques to Enable 430Gb/s/mm2 Proximity Communication. 368-609 - Chris Rudell, Qiuting Huang, Thomas Lee:
E2 Digital RF Fundamentally a New Technology or Just Marketing Hype? 374-375 - Albert Theuwissen, Ernesto Perea:
SE5 Highlights of IEDM 2006. 370-371 - David Money Harris, Norman J. Rohrer:
SE6 Secure Digital Systems. 372-373 - Reid Harrison, Ken Wise:
SE7 Implantable and Prosthetic Devices: Life-Changing Circuits. 376-377 - Euisik Yoon, Farrokh Ayazi:
Sensors and MEMS. 378-379 - Michael A. Suster, Jun Guo, Nattapon Chaimanonart, Wen H. Ko, Darrin J. Young:
A Wireless Strain Sensing Microsystem with External RF Power Source and Two-Channel Data Telemetry Capability. 380-609 - Christian Schott, Robert Racz, Samuel Huber, Angelo Manco, Markus Gloor, Nicolas Simonne:
A CMOS Single-Chip Electronic Compass with Microcontroller. 382-609 - Fabrice Gayral, Elisabeth Delevoye, Cyril Condemine, Éric Colinet, Marc Béranger, Fabien Mieyeville, Frédéric Gaffiot:
A 100Hz 5nT/Hz Low-Pass ΔΣ Servo-Controlled Microfluxgate Magnetometer Using Pulsed Excitation. 384-610 - Ajit Sharma, Faisal Zaman, Farrokh Ayazi:
A 0.2°/hr Micro-Gyroscope with Automatic CMOS Mode Matching. 386-610 - Werner Magnes, Matthias Oberst, Aris Valavanoglou, Ulrich Reichold, Harald Neubauer, Hans Hauer, Peter Falkner:
A 92dB-DR 13mW ΔΣ Modulator for Spaceborn Fluxgate Sensors. 388-610 - Andrea Baschirotto, Enrico Dallago, Vincenzo Ferragina, Massimo Ferri, Marco Grassi, Piero Malcovati, Marco Marchesi, Enrico Melissano, Marco Morelli, Andrea Rossini, Stefano Ruzza, Pietro Siciliano, Giuseppe Venchi:
A CMOS 2D Micro-Fluxgate Earth Magnetic Field Sensor with Digital Output. 390-610 - Marcin K. Augustyniak, W. Weber, Gottfried Beer, Hans Mulatz, L. Elbrecht, H.-J. Timme, Marc Tiebout, Werner Simbürger, Christian Paulus, Björn Eversmann, Doris Schmitt-Landsiedel, Roland Thewes, Ralf Brederlow:
An Integrated Gravimetric FBAR Circuit for Operation in Liquids Using a Flip-Chip Extended 0.13μm CMOS Technology. 392-610 - Maximilian Sergio, Cristiano Niclass, Edoardo Charbon:
A 128×2 CMOS Single-Photon Streak Camera with Timing-Preserving Latchless Pipeline Readout. 394-610 - David T. Blaauw, Georgios Konstandinidis:
Digital Circuit Innovations. 396-397 - Alan J. Drake, Robert M. Senger, Harmander Deogun, Gary D. Carpenter, Soraya Ghiasi, Tuyet Nguyen, Norman K. James, Michael S. Floyd, Vikas Pokala:
A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor. 398-399 - Saibal Mukhopadhyay, Keunwoo Kim, Keith A. Jenkins, Ching-Te Chuang, Kaushik Roy:
Statistical Characterization and On-Chip Measurement Methods for Local Random Variability of a Process Using Sense-Amplifier-Based Test Structure. 400-611 - Toru Nakura, Koichi Nose, Masayuki Mizuno:
Fine-Grain Redundant Logic Using Defect-Prediction Flip-Flops. 402-611 - Carlos Tokunaga, David T. Blaauw, Trevor N. Mudge:
True Random Number Generator with a Metastability-Based Quality Control. 404-611 - Ying Su, Jeremy Holleman, Brian P. Otis:
A 1.6pJ/bit 96% Stable Chip-ID Generating Circuit using Process Variations. 406-611 - Young-Ho Kwak, Inhwa Jung, Hyung-Dong Lee, Young-Jung Choi, Yogendera Kumar, Chulwoo Kim:
A One-Cycle Lock Time Slew-Rate-Controlled Output Driver. 408-611 - Shashank Shastry, Ajay Bhatia, Sagar Reddy:
A Single-Cycle-Access 128-Entry Fully Associative TLB for Multi-Core Multi-Threaded Server-on-a-Chip. 410-612 - Ron Ho, Tarik Ono, Frankie Liu, Robert David Hopkins, Alex Chow, Justin Schauer, Robert J. Drost:
High-Speed and Low-Energy Capacitively-Driven On-Chip Wires. 412-612 - Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta:
A 0.28pJ/b 2Gb/s/ch Transceiver in 90nm CMOS for 10mm On-Chip interconnects. 414-612 - Tom Schiltz, Kari Halonen:
Broadband RF and Radar. 416-417 - S. Lee, Jos Bergervoet, Harish Kundur Subramaniyan, Domine Leenaerts, Raf Roovers, Remco van de Beek, Gerard van der Weide:
A Broadband Receive Chain in 65nm CMOS. 418-612 - Andrea Bevilacqua, Alessio Vallese, Christoph Sandner, Marc Tiebout, Andrea Gerosa, Andrea Neviani:
A 0.13μm CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers. 420-612 - Jonathan Borremans, Piet Wambacq, Dimitri Linten:
An ESD-Protected DC-to-6GHz 9.7mW LNA in 90nm Digital CMOS. 422-613 - Rashad Ramzan, Stefan Back Andersson, Jerzy J. Dabrowski, Christer Svensson:
A 1.4V 25mW Inductorless Wideband LNA in 0.13μm CMOS. 424-613 - Ta-Shun Chu, Jonathan Roderick, Hossein Hashemi:
A 4-Channel UWB Beam-Former in 0.13μm CMOS using a Path-Sharing True-Time-Delay Architecture. 426-613 - Behzad Razavi:
Heterodyne Phase Locking: A Technique for High-Frequency Division. 428-429 - Saverio Trotta, Herbert Knapp, Donald Dibra, Klaus Aufinger, Thomas F. Meister, Josef Böck, Werner Simbürger, Arpad L. Scholtz:
A 79GHz SiGe-Bipolar Spread-Spectrum TX for Automotive Radar. 430-613 - Jri Lee:
A 75-GHz PLL in 90-nm CMOS Technology. 432-613 - Robert Payne, Muneo Fukaishi:
Multi-GB/s Transceivers. 434-435 - Mike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth:
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery. 436-591 - Takashi Masuda, Hideyuki Suzuki, Hiroshi Iizuka, Akio Igarashi, Kaneyoshi Takeshita, Takayuki Mogi, Takayuki Shoji, Jeremy Chatwin, Iain Butler, Derek Mellor:
A 250mW Full-Rate 10Gb/s Transceiver Core in 90nm CMOS Using a Tri-State Binary PD with 100ps Gated Digital Output. 438-614 - Robert Palmer, John Poulton, William J. Dally, John G. Eyles, Andrew M. Fuller, Trey Greer, Mark Horowitz, Mark Kellam, F. Quan, F. Zarkeshvari:
A 14mW 6.25Gb/s Transceiver in 90nm CMOS for Serial Chip-to-Chip Communications. 440-614 - Yasuo Hidaka, Weixin Gai, Akira Hattori, Takeshi Horie, Jian Jiang, Kouichi Kanda, Yoichi Koyanagi, Satoshi Matsubara, Hideki Osone:
A 4-Channel 3.1/10.3Gb/s Transceiver Macro with a Pattern-Tolerant Adaptive Equalizer. 442-443 - Jri Lee, Huaide Wang:
A 20Gb/s Broadband Transmitter with Auto-Configuration Technique. 444-614 - Christian Menolfi, Thomas Toifl, Peter Buchmann, Marcel A. Kossel, Thomas Morf, Jonas R. M. Weiss, Martin L. Schmatz:
A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI. 446-614 - Qun Gu, Zhiwei Xu, Jenwei Ko, Mau-Chung Frank Chang:
Two 10Gb/s/pin Low-Power Interconnect Methods for 3D ICs. 448-614 - Dieter Draxelmayr, Venu Gopinathan:
Nyquist ADC Techniques. 450-451 - Masato Yoshioka, Masahiro Kudo, Toshihiko Mori, Sanroku Tsukamoto:
A 0.8V 10b 8OMS/s 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing. 452-614 - Dan J. Huber, Rodney J. Chandler, Asad A. Abidi:
A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS. 454-615 - Young-Deuk Jeon, Seung-Chul Lee, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim:
A 4.7mW 0.32mm2 10b 30MS/s Pipelined ADC Without a Front-End S/H in 90nm CMOS. 456-615 - Seung-Chul Lee, Young-Deuk Jeon, Kwi-Dong Kim, Jong-Kee Kwon, Jongdae Kim, Jeong-Woong Moon, Woo-Yol Lee:
A 10b 205MS/s 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications. 458-615 - Lane Brooks, Hae-Seung Lee:
A Zero-Crossing-Based 8b 200MS/s Pipelined ADC. 460-615 - Bjørnar Hernes, Johnny Bjørnsen, Terje N. Andersen, Anders Vinje, Havard Korsvoll, Frode Telstø, Atle Briskemyr, Christian Holdo, Øystein Moldsvor:
A 92.5mW 205MS/s 10b Pipeline IF ADC Implemented in 1.2V/3.3V 0.13μm CMOS. 462-615 - Cheng-Chung Hsu, Fong-Ching Huang, Chih-Yung Shih, Chen-Chih Huang, Ying-Hsi Lin, Chao-Cheng Lee, Behzad Razavi:
An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration. 464-615 - Jaesik Lee, Yves Baeyens, Joseph Weiner, Young-Kai Chen:
A 50GS/s Distributed T/H Amplifier in 0.18μm SiGe BiCMOS. 466-616 - Ybe Creten, Patrick Merken, Willy Sansen, Robert Mertens, Chris Van Hoof:
A Cryogenic ADC operating Down to 4.2K. 468-616 - Hideto Hidaka, Yair Sofer:
Non-Volatile Memories. 470-471 - KwangJin Lee, Beak-Hyung Cho, Woo-Yeong Cho, Sangbeom Kang, Byung-Gil Choi, Hyung-Rok Oh, Changsoo Lee, Hye-Jin Kim, Joon-min Park, Qi Wang, Mu-Hui Park, Yu-Hwan Ro, Joon-Yong Choi, Ki-Sung Kim, Young-Ran Kim, In-Cheol Shin, Ki-won Lim, Ho-Keun Cho, ChangHan Choi, Won-ryul Chung, Du-Eung Kim, Kwang-Suk Yu, Gitae Jeong, Hongsik Jeong, Choong-Keun Kwak, Chang-Hyun Kim, Kinam Kim:
A 90nm 1.8V 512Mb Diode-Switch PRAM with 266MB/s Read Throughput. 472-616 - Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara:
A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. 474-616 - Corrado Villa, Daniele Vimercati, Stefan Schippers, Salvatore Polizzi, Andrea Scavuzzo, Maurizio Perroni, Maurizio Gaibotti, Mauro Luigi Sali:
A 65nm 1Gb 2b/Cell NOR Flash with 2.25MB/s Program Throughput and 400MB/s DDR interface. 476-616 - Christoph Demi, Maciej Jankowski, Carmen Thalmaier:
A 0.13μm 2.125MB 23.5ns Embedded Flash with 2GB/s Read Throughput for Automotive Microcontrollers. 478-617 - Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno:
2Mb Spin-Transfer Torque RAM (SPRAM) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read. 480-617 - Mitsuo Usami, Hisao Tanabe, Akira Sato, Isao Sakama, Yukio Maki, Toshiaki Iwamatsu, Takashi Ipposhi, Yasuo Inoue:
A 0.05�?0.05mm2 RFID Chip with Easily Scaled-Down ID-Memory. 482-483 - Martin Brox, Kazuhiko Kajigaya:
DRAM and eRAM. 484-485 - John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar A. Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer:
A 500MHz Random Cycle 1.5ns-Latency, SOI Embedded DRAM Macro Featuring a 3T Micro Sense Amplifier. 486-617 - Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara:
A 65nm Embedded SRAM with Wafer-Level Burn-In Mode, Leak-Bit Redundancy and E-Trim Fuse for Known Good Die. 488-617 - Masaru Haraguchi, Tokuya Osawa, Akira Yamazaki, Chikayoshi Morishima, Toshinori Morihara, Yoshikazu Morooka, Yoshihiro Okuno, Kazutami Arimoto:
A Continuous-Adaptive DDR2 Interface with Flexible Round-Trip-Time and Full Self Loop-Backed AC Test. 490-491 - Jeong-Don Ihm, Seung-Jun Bae, Kwang-Il Park, Ho-Young Song, Woo-Jin Lee, Hyun-Jin Kim, Kyoung-Ho Kim, Ho-Kyung Lee, Min-Sang Park, Sam-Young Bang, Mi-Jin Lee, Gil-Shin Moon, Young-Wook Jang, Suk-Won Hwang, Young-Chul Cho, Sang-Jun Hwang, Dae-Hyun Kim, Ji-Hoon Lim, Jae-Sung Kim, Su-Jin Park, Ok-Joo Park, Se-Mi Yang, Jin-Yong Choi, Young-Wook Kim, Hyun-Kyu Lee, Sunghoon Kim, Seong-Jin Jang, Young-Hyun Jun, Soo-In Cho:
An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. 492-617 - Brian Johnson, Brent Keeth, Feng Lin, Hua Zheng:
Phase-Tolerant Latency Control for a Combination 512Mb 2.0Gb/s/pin GDDR3 and 2.5Gb/s/pin GDDR4 SDRAM. 494-617 - Byung-Guk Kim, Lee-Sup Kim, Kwang-Il Park, Young-Hyun Jun, Soo-In Cho:
A DLL with Jitter-Reduction Techniques for DRAM Interfaces. 496-497 - Johannes Solhusvik, Hirofumi Sumi:
Image Sensors. 498-499 - Christoph Posch, Michael Hofstätter, Daniel Matolin, Guy Vanstraelen, Peter Schön, Nikolaus Donath, Martin Litzenberger:
A Dual-Line Optical Transient Sensor with On-Chip Precision Time-Stamp Generation. 500-618 - Jaehyuk Choi, Sang-Wook Han, Seong-Jin Kim, Sun-Il Chang, Euisik Yoon:
A Spatial-Temporal Multi-Resolution CMOS Image Sensor with Adaptive Frame Rates for Moving Objects in the Region-of-Interest. 502-618 - Sam Kavusi, Kunal Ghosh, Abbas El Gamal:
A Per-Pixel Pulse-FM Background Subtraction Circuit with 175ppm Accuracy for Imaging Applications. 504-618 - Martijn F. Snoeij, P. Donegan, Albert J. P. Theuwissen, Kofi A. A. Makinwa, Johan H. Huijsing:
A CMOS Image Sensor with a Column-Level Multiple-Ramp Single-Slope ADC. 506-618 - Kwang-Bo Cho, Chiajen Lee, Siri Eikedal, Aaron Baum, Jutao Jiang, Chen Xu, Xiaofeng Fan, Ralph Kauffman:
A 1/2.5 inch 8.1Mpixel CMOS Image Sensor for Digital Cameras. 508-618 - Hidekazu Takahashi, Tomoyuki Noda, Takashi Matsuda, Takanori Watanabe, Mashito Shinohara, Toshiaki Endo, Shunsuke Takimoto, Ryuichi Mishima, Shigeru Nishimura, Ktuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue:
A 1/2.7 inch Low-Noise CMOS Image Sensor for Full HD Camcorders. 510-618 - Peter Centen, Steffen Lehr, Volker Neiss, Sabine Roth, Jeroen Rotte, Heinrich Schemmann, Michael Schreiber, Patrick Vogel, Boon-Keng Teng, Klaas Damstra:
A 2/3 inch CMOS Image Sensor for HDTV Applications with Multiple High-DR Modes and Flexible Scanning. 512-619 - Kimiaki Toshikiyo, Takanori Yogo, Motonori Ishii, Kazuhiko Yamanaka, Toshinobu Matsuno, Kazutoshi Onozawa, Takumi Yamaguchi:
A MOS Image Sensor with Microlenses Built by Sub-Wavelength Patterning. 514-515 - Doug Smith, JoAnn Close:
Analog and Power Management Techniques. 516-517 - Tae-Woo Kwak, Min-Chul Lee, Bae-Kun Choi, Hanh-Phuc Le, Gyu-Hyeong Cho:
A 2W CMOS Hybrid Switching Amplitude Modulator for EDGE Polar Transmitters. 518-619 - Vishal Gupta, Gabriel A. Rincón-Mora:
A 5mA 0.6μm CMOS Miller-Compensated LDO Regulator with -27dB Worst-Case Power-Supply Rejection Using 60pF of On-Chip Capacitance. 520-521 - Anna Richelli, Luca Mensi, Luigi Colalongo, Pier Luigi Rolandi, Zsolt Miklós Kovács-Vajna:
A 1.2-to-8V Charge-Pump with Improved Power Efficiency for Non-Volatille Memories. 522-619 - Bert Serneels, Michiel Steyaert, Wim Dehaene:
A 237mW aDSL2+ CO Line Driver in Standard 1.2V 0.13μ CMOS. 524-619 - Edoardo Bonizzoni, Fausto Borghetti, Piero Malcovati, Franco Maloberti, Bernhard Niessen:
A 200mA 93% Peak Efficiency Single-Inductor Dual-Output DC-DC Buck Converter. 526-619 - Michael D. Mulligan, Bill Broach, Thomas H. Lee:
A 3MHz Low-Voltage Buck Converter with Improved Light Load Efficiency. 528-620 - Giuseppe de Vita, Giuseppe Iannaccone:
A Voltage Regulator for Subthreshold Logic with Low Sensitivity to Temperature and Process Variations. 530-620 - Mehdi Alimadadi, Samad Sheikhaei, Guy Lemieux, Shahriar Mirabbasi, Patrick R. Palmer:
A 3GHz Switching DC-DC Converter Using Clock-Tree Charge-Recycling in 90nm CMOS with Integrated Output Filter. 532-620 - Hanh-Phuc Le, Chang-Seok Chae, Kwang-Chan Lee, Gyu-Hyeong Cho, Se-Won Wang, Gyu-Ha Cho, Sung-il Kim:
A Single-Inductor Switching DC-DC Converter with 5 Outputs and Ordered Power-Distributive Control. 534-620 - Michael M. Green, Thomas Burger:
Building Blocks for High-Speed Transceivers. 536-537 - Jun-Chau Chien, Liang-Hung Lu:
40Gb/s High-Gain Distributed Amplifiers with Cascaded Gain Stages in 0.18μm CMOS. 538-620 - Daeik D. Kim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Weipeng Li, Daihyun Lim, Robert Trzcinski, Mahender Kumar, Christine Norris, David Ahlgren:
A 70GHz Manufacturable Complementary LC-VCO with 6.14GHz Tuning Range in 65nm SOI CMOS. 540-620 - Daihyun Lim, Jonghae Kim, Jean-Olivier Plouchart, Choongyeun Cho, Daeik D. Kim, Robert Trzcinski, Duane S. Boning:
Performance Variability of a 90GHz Static CML Frequency Divider in 65nm SOI CMOS. 542-621 - Jun-Chau Chien, Liang-Hung Lu:
40GHz Wide-Locking-Range Regenerative Frequency Divider and Low-Phase-Noise Balanced VCO in 0.18μm CMOS. 544-621 - Waleed Khalil, Bertan Bakkaloglu, Sayfe Kiaei:
A Self-Calibrated On-chip Phase-Noise-Measurement Circuit with -75dBc Single-Tone Sensitivity at 100kHz Offset. 546-621 - Kambiz K. Moez, Mohamed I. Elmasry:
A 10dB 44GHz Loss-Compensated CMOS Distributed Amplifier. 548-621 - Wolfgang Soldner, Moon-Jung Kim, Martin Streibl, Harald Gossner, Thomas H. Lee, Doris Schmitt-Landsiedel:
A 10GHz Broadband Amplifier with Bootstrapped 2kV ESD Protection. 550-551 - Emre Ayranci, Kenn Christensen, Pietro Andreani:
45% Power Saving in a 0.25μm BiCMOS 10Gb/s 50Ω-Terminated Packaged Active-Load Laser Driver. 552-553 - Daniel Micusik, Horst Zimmermann:
A 240MHz-BW 112dB-DR TIA. 554-621 - George Chien, Mototsugu Hamada:
WLAN/Bluetooth. 556-557 - Bojko Marholev, Michael Pan, Ed Chien, L. Zhang, Rozi Roufoogaran, Steve Wu, Iqbal Bhatti, Tsung-Hsien Lin, Michael S. Kappes, Shahla Khorram, Seema Butala Anand, Alireza Zolfaghari, Jesse Castaneda, C. M. Chien, Brima Ibrahim, Henrik Jensen, H. Kim, Paul Lettieri, Siukai Mak, Jack Lin, Y. C. Wong, R. Lee, M. Syed, Maryam Rofougaran, Ahmadreza Rofougaran:
A Single-Chip Bluetooth EDR Device in 0.13μm CMOS. 558-759 - Arya Behzad, Keith A. Carter, Ed Chien, Steve Wu, Michael Pan, C. Paul Lee, Tom Li, John C. Leete, Stephen Au, Michael S. Kappes, Zhimin Zhou, Dayo Ojo, Lijun Zhang, Alireza Zolfaghari, Jesse Castaneda, Hooman Darabi, Benson Yeung, Reza Rofougaran, Maryam Rofougaran, Jason Trachewsky, Tushar Moorti, Rohit V. Gaikwad, Amit Bagchi, Jacob J. Rael, Bojko Marholev:
A Fully Integrated MIMO Multi-Band Direct-Conversion CMOS Transceiver for WLAN Applications (802.11n). 560-622 - Martin Simon, Peter Laaser, Voicu Filimon, Hans Geltinger, Dirk Friedrich, Yalcin Raman, Robert Weigel:
An 802.11a/b/g RF Transceiver in an SoC. 562-622 - Richard Chang, David Weber, MeeLan Lee, David K. Su, Katelijn Vleugels, S. Simon Wong:
A Fully Integrated RF Front-End with Independent RX/TX Matching and +20dBm Output Power for WLAN Applications. 564-622 - Donhee Ham, Siva G. Narendra:
TD: Trends in Wireless Systems. 566-567 - Liesbet Van der Perre, Bruno Bougard, Jan Craninckx, Wim Dehaene, Lieven Hollevoet, Murali Jayapala, Pol Marchal, Miguel Miranda, Praveen Raghavan, Thomas Schuster, Piet Wambacq, Francky Catthoor, Peter Vanbekbergen:
Architectures and Circuits for Software-Defined Radios: Scaling and Scalability for Low Cost and Low Energy. 568-569 - Cary Gunn, Drew Guckenberger, Thierry Pinguet, Deana Gunn, Danny Eliyahu, Barmak Mansoorian, Daniel A. Van Blerkom, Olli Salminen:
A Low Phase Noise 10GHz Optoelectronic RF Oscillator Implemented Using CMOS Photonics. 570-622 - William R. Deal, Larry Yujiri, Mansoor Siddiqui, Richard Lai:
Advanced MMIC for Passive Millimeter and Submillimeter Wave Imaging. 572-622 - Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma, Daisuke Ohgarane, Satoru Saito, Koji Dairiki, Hidekazu Takahashi, Yutaka Shionoiri, Tomoaki Atsumi, Takeshi Osada, Kei Takahashi, Takanori Matsuzaki, Hiroyuki Takashina, Yoshinari Yamashita, Shunpei Yamazaki:
UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems. 574-575 - Shailesh Rai, Brian P. Otis:
A 1V 600μW 2.1GHz Quadrature VCO Using BAW Resonators. 576-623 - Kuan-Hung Chen, Tzi-Dar Chiueh:
A 1.8V 165mW Discrete Wavelet Multi-Tone Baseband Receiver for Cognitive Radio Applications. 578-623 - S. Razafimandimby, Andreia Cathelin, Jerome Lajoinie, Andreas Kaiser, Didier Belot:
A 2GHz 0.25μm SiGe BiCMOS Oscillator with Flip-Chip Mounted BAW Resonator. 580-623 - Raymond E. Barnett, Ganesh K. Balachandran, Steve Lazar, Brad Kramer, George Konnail, Sribhotla Rajasekhar, Vladimir Drobny:
A Passive UHF RFID Transponder for EPC Gen 2 with -14dBm Sensitivity in 0.13μm CMOS. 582-623 - Ian Galton, Matt Miller, Robert Bogdan Staszewski, Bram Nauta, Michiel Steyaert:
Analog, Mixed-Signal, and RF Circuit Design in Nanometer CMOS. 635-636
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