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ORCIDISSCC 2014: San Francisco, CA, USA
- 2014 IEEE International Conference on Solid-State Circuits Conference, ISSCC 2014, Digest of Technical Papers, San Francisco, CA, USA, February 9-13, 2014. IEEE 2014, ISBN 978-1-4799-0918-6
- Mark Horowitz:
1.1 Computing's energy problem (and what we can do about it). 10-14 - Ming-Kai Tsai:
1.2 Cloud 2.0 clients and connectivity - Technology and challenges. 15-19 - Erik H. M. Heijne:
1.3 How chips pave the Road to the Higgs particle and the attoworld beyond. 22-28 - Susie J. Wee:
1.4 The next generation of networked experiences. 29-35 - Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Shiva Kotagiri, Lijun Li, Christopher J. Abel, Freeman Zhong:
2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. 38-39 - Ullas Singh, Adesh Garg, Bharath Raghavan, Nick Huang, Heng Zhang, Zhi Huang, Afshin Momtaz, Jun Cao:
2.2 A 780mW 4×28Gb/s transceiver for 100GbE gearbox PHY in 40nm CMOS. 40-41 - Ping-Chuan Chiang, Hao-Wei Hung, Hsiang-Yun Chu, Guan-Sing Chen, Jri Lee:
2.3 60Gb/s NRZ and PAM4 transmitters for 400GbE in 65nm CMOS. 42-43 - Jun Won Jung, Behzad Razavi:
2.4 A 25Gb/s 5.8mW CMOS equalizer. 44-45 - Rui Bai, Samuel Palermo, Patrick Yin Chiang:
2.5 A 0.25pJ/b 0.7V 16Gb/s 3-tap decision-feedback equalizer in 65nm CMOS. 46-47 - Dong Hoon Baek, Byungsub Kim, Hong-June Park, Jae-Yoon Sim:
2.6 A 5.67mW 9Gb/s DLL-based reference-less CDR with pattern-dependent clock-embedded signaling for intra-panel interface. 48-49 - Seungho Han, Sooeun Lee, Minsoo Choi, Jae-Yoon Sim, Hong-June Park, Byungsub Kim:
2.7 A coefficient-error-robust FFE TX with 230% eye-variation improvement without calibration in 65nm CMOS technology. 50-51 - Jun-Chau Chien, Parag Upadhyaya, Howard Jung, Stanley Chen, Wayne Fang, Ali M. Niknejad, Jafar Savoj, Ken Chang:
2.8 A pulse-position-modulation phase-noise-reduction technique for a 2-to-16GHz injection-locked ring oscillator in 20nm CMOS. 52-53 - Giovanni Marzin, Salvatore Levantino
, Carlo Samori, Andrea L. Lacaita:
2.9 A Background calibration technique to control bandwidth in digital PLLs. 54-55 - Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka:
3.1 polar antenna impedance detection and tuning for efficiency improvement in a 3G/4G CMOS Power Amplifier. 58-59 - Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Seitaro Kawai, Shinji Yamaura, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori:
3.2 A 1.95GHz fully integrated envelope elimination and restoration CMOS power amplifier with envelope/phase generator and timing aligner for WCDMA and LTE. 60-61 - Brecht François, Patrick Reynaert:
3.3 A transformer-coupled true-RMS power detector in 40nm CMOS. 62-63 - Ercan Kaymaksut, Patrick Reynaert:
3.4 A dual-mode transformer-based doherty LTE power amplifier in 40nm CMOS. 64-65 - Michiel C. M. Soer, Eric A. M. Klumperink, Bram Nauta, Frank E. van Vliet:
3.5 A 1.0-to-2.5GHz beamforming receiver with constant-Gm vector modulator consuming. 66-67 - David Murphy, Hooman Darabi, Hao Xu:
3.6 A noise-cancelling receiver with enhanced resilience to harmonic blockers. 68-69 - In-Young Lee, Sang-Sung Lee, Donggu Im, Seungjin Kim, Jeongki Choi, Sang-Gug Lee, Jinho Ko:
3.7 A fully integrated TV tuner front-end with 3.1dB NF, >+31dBm OIP3, >83dB HRR3/5 and >68dB HRR7. 70-71 - Massoud Tohidian, Iman Madadi, Robert Bogdan Staszewski:
3.8 A fully integrated highly reconfigurable discrete-time superheterodyne receiver. 1-3 - Fujian Lin, Pui-In Mak, Rui Paulo Martins:
3.9 An RF-to-BB current-reuse wideband receiver with parallel N-path active/passive mixers and a single-MOS pole-zero LPF. 74-75 - Chen Kong Teh, Atsushi Suzuki, Manabu Yamada, Mototsugu Hamada, Yasuo Unekawa:
4.1 A 3-phase digitally controlled DC-DC converter with 88% ripple reduced 1-cycle phase adding/dropping scheme and 28% power saving CT/DT hybrid current control. 78-79 - Min Kyu Song, Joseph Sankman, Dongsheng Ma:
4.2 A 6A 40MHz four-phase ZDS hysteretic DC-DC converter with 118mV droop and 230ns response time for a 5A/5ns load transient. 80-81 - Danzhu Lu, Yao Qian, Zhiliang Hong:
4.3 An 87%-peak-efficiency DVS-capable single-inductor 4-output DC-DC buck converter with ripple-based adaptive off-time control. 82-83 - Lin Cheng, Yonggen Liu, Wing-Hung Ki:
4.4 A 10/30MHz Wide-duty-cycle-range buck converter with DDA-based Type-III compensator and fast reference-tracking responses for DVS applications. 84-85 - Kapil Kesarwani, Rahul Sangwan, Jason T. Stauth:
4.5 A 2-phase resonant switched-capacitor converter delivering 4.3W at 0.6W/mm2 with 85% efficiency. 86-87 - Loai G. Salem, Patrick P. Mercier:
4.6 An 85%-efficiency fully integrated 15-ratio recursive switched-capacitor DC-DC converter with 0.1-to-2.2V output voltage range. 88-89 - Toke Meyer Andersen, Florian Krismer, Johann W. Kolar, Thomas Toifl, Christian Menolfi, Lukas Kull, Thomas Morf, Marcel A. Kossel, Matthias Braendli, Peter Buchmann, Pier Andrea Francese:
4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. 90-91 - Ravi Karadi, Gerard Villar Pique:
4.8 3-phase 6/1 switched-capacitor DC-DC boost converter providing 16V at 7mA and 70.3% efficiency in 1.1mm3. 92-93 - Eric J. Fluhr, Joshua Friedrich, Daniel M. Dreps, Victor V. Zyuban, Gregory S. Still, Christopher J. Gonzalez, Allen Hall, David Hogenmiller, Frank Malgioglio, Ryan Nett, Jose Paredes, Juergen Pille, Donald W. Plass, Ruchir Puri, Phillip J. Restle, David Shan, Kevin Stawiasz, Zeynep Toprak Deniz, Dieter F. Wendel, Matthew M. Ziegler:
5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth. 96-97 - Zeynep Toprak Deniz, Michael A. Sperling, John F. Bulzacchelli, Gregory S. Still, Ryan Kruse, Seongwon Kim, David Boerstler, Tilman Gloekler, Raphael Robertazzi, Kevin Stawiasz, Tim Diemoz, George English, David Hui, Paul Muench, Joshua Friedrich:
5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. 98-99 - Phillip J. Restle, David Shan, David Hogenmiller, Yong Kim, Alan J. Drake, Jason Hibbeler, Thomas J. Bucelot, Gregory S. Still, Keith A. Jenkins, Joshua Friedrich:
5.3 Wide-frequency-range resonant clock with on-the-fly mode changing for the POWER8TM microprocessor. 100-101 - Stefan Rusu, Harry Muljono, David Ayers, Simon M. Tam, Wei Chen, Aaron Martin, Shenggao Li, Sujal Vora, Raj Varada, Eddie Wang:
5.4 Ivytown: A 22nm 15-core enterprise Xeon® processor family. 102-103 - Kevin Gillespie, Harry R. Fair III, Carson Henrion, Ravi Jotwani, Stephen V. Kosonocky, Robert S. Orefice, Donald A. Priore, Jonathan White, Kathryn Wilcox:
5.5 Steamroller: An x86-64 core implemented in 28nm bulk CMOS. 104-105 - Aaron Grenat, Sanjay Pant, Ravinder Rachala, Samuel Naffziger:
5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. 106-107 - Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. 108-109 - Alfred Yeung, Hamid Partovi, Qawi Harvard, Luca Ravezzi, John Ngai, Russell Homer, M. Ashcraft, Greg Favor:
5.8 A 3GHz 64b ARM v8 processor in 40nm bulk CMOS technology. 110-111 - Nasser A. Kurd, Muntaquim Chowdhury, Edward Burton, Thomas P. Thomas, Christopher Mozak, Brent Boswell, Manoj Lal, Anant Deval, Jonathan Douglas, Ali M. El-Husseini, Ankireddy Nalamalpu, Timothy M. Wilson, Matthew Merten, Srinivas Chennupaty, Wilfred Gomes, Rajesh Kumar:
5.9 Haswell: A family of IA 22nm processors. 112-113 - Dinesh Maheshwari:
6.1 memory and system architecture for 400Gb/s networking and beyond. 116-117 - Yutaka Miyamoto, Masahito Tomizawa:
6.2 High-capacity scalable optical communication for future Optical Transport Network. 118-119 - Christophe Erdmann, Donnacha Lowney, Adrian Lynam, Aidan Keady, John McGrath, Edward Cullen, Daire Breathnach, Denis Keane, Patrick Lynch, Marites De La Torre, Ronnie De La Torre, Peng Lim, Anthony Collins, Brendan Farley, Liam Madden:
6.3 A Heterogeneous 3D-IC consisting of two 28nm FPGA die and 32 reconfigurable high-performance data converters. 120-121 - JungChak Ahn, Kyungho Lee, Yitae Kim, Heegeun Jeong, Bumsuk Kim, Hongki Kim, Jongeun Park, Taesub Jung, Wonje Park, Taeheon Lee, Eunkyung Park, Sangjun Choi, Gyehun Choi, Haeyong Park, Yujung Choi, Seungwook Lee, Yunkyung Kim, Y. J. Jung, Donghyuk Park, Seungjoo Nah, Youngsun Oh, Mihye Kim, Yooseung Lee, Youngwoo Chung, Ihara Hisanori, Joon-Hyuk Im, Daniel-K J Lee, Byunghyun Yim, GiDoo Lee, Heesang Kown, Sungho Choi, Jeonsook Lee, Dongyoung Jang, Youngchan Kim, Tae Chan Kim, Hiroshige Goto, Chi-Young Choi, Duckhyung Lee, Gab-soo Han:
7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate. 124-125 - Seokjun Park, Jihyun Cho, Kyuseok Lee, Euisik Yoon:
7.2 243.3pJ/pixel bio-inspired time-stamp-based 2D optic flow sensor for artificial compound eyes. 126-127 - Cong Shi, Jie Yang, Ye Han, Zhongxiang Cao, Qi Qin, Liyuan Liu, Nanjian Wu, Zhihua Wang:
7.3 A 1000fps vision chip based on a dynamically reconfigurable hybrid architecture comprising a PE array and self-organizing map neural network. 128-129 - Sang-Man Han, Taishi Takasawa, Tomoyuki Akahori, Keita Yasutomi, Keiichiro Kagawa, Shoji Kawahito:
7.4 A 413×240-pixel sub-centimeter resolution Time-of-Flight CMOS image sensor with in-pixel background canceling using lateral-electric-field charge modulators. 130-131 - Keita Yasutomi, Takahiro Usui, Sang-Man Han, Taishi Takasawa, Keiichiro Kagawa, Shoji Kawahito:
7.5 A 0.3mm-resolution Time-of-Flight CMOS range imager with column-gating clock-skew calibration. 132-133 - Andrew D. Payne, Andy Daniel, Anik Mehta, Barry Thompson, Cyrus S. Bamji, Dane Snow, Hideaki Oshima, Larry Prather, Mike Fenton, Lou Kordus, Patrick O'Connor, Rich McCauley, Sheethal Nayak, Sunil Acharya, Swati Mehta, Tamer A. Elkhatib, Thomas Meyer, Tod O'Dwyer, Travis Perry, Vei-Han Chan, Vincent Wong, Vishali Mogallapu, William Qian, Zhanping Xu:
7.6 A 512×424 CMOS 3D Time-of-Flight image sensor with multi-frequency photo-demodulation up to 130MHz and 2GS/s ADC. 134-135 - Kyeongha Kwon, Jong-Hyeok Yoon, Soon-Won Kwon, Jaehyeok Yang, Joon-Yeong Lee, Hyosup Won, Hyeon-Min Bae:
8.1 A 6Gb/s transceiver with a nonlinear electronic dispersion compensator for directly modulated distributed-feedback lasers. 138-139 - Hiroshi Morita, Koki Uchino, Eiji Otani, Hiizu Ohtorii, Takeshi Ogura, Kazunao Oniki, Shuichi Oka, Shusaku Yanagawa, Hideyuki Suzuki:
8.2 A 12×5 two-dimensional optical I/O array for 600Gb/s chip-to-chip interconnect in 65nm CMOS. 140-141 - Enrico Mammei, Fabrizio Loi, Francesco Radice, Angelo Dati, Melchiorre Bruccoleri, Matteo Bassi, Andrea Mazzanti:
8.3 A power-scalable 7-tap FIR equalizer with tunable active delay line for 10-to-25Gb/s multi-mode fiber EDC in 28nm LP-CMOS. 142-143 - Tsung-Ching Huang, Tao-Wen Chung, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin, Fu-Lung Hsueh:
8.4 A 28Gb/s 1pJ/b shared-inductor optical receiver with 56% chip-area reduction in 28nm CMOS. 144-145 - Jan R. Westra, Jan Mulder, Yi Ke, Davide Vecchi, Xiaodong Liu, Erol Arslan, Jiansong Wan, Qiongna Zhang, Sijia Wang, Frank M. L. van der Goes, Klaas Bult:
8.5 A sub-1.75W full-duplex 10GBASE-T transceiver in 40nm CMOS. 146-147 - Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan, Karim Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu, Jenny Yu, Joseph N. Y. Aziz, Derek Tam, Ichiro Fujimori:
8.6 A full-duplex line driver for Gigabit Ethernet with rail-to-rail class-AB output stage in 28nm CMOS. 148-149 - Guanghua Shu, Woo-Seok Choi, Saurabh Saxena, Tejasvi Anand, Amr Elshazly, Pavan Kumar Hanumolu:
8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS. 150-151 - Sui Huang, Jun Cao, Michael M. Green:
8.8 An 8.2-to-10.3Gb/s full-rate linear reference-less CDR without frequency detector in 0.18μm CMOS. 152-153 - Yukito Tsunoda, Mariko Sugawara, Hideki Oku, Satoshi Ide, Kazuhiro Tanaka:
8.9 A 40Gb/s VCSEL over-driving IC with group-delay-tunable pre-emphasis for optical interconnection. 154-155 - Wee Liang Lien, Tieng Yi Choke, Ying Chow Tan, Ming Kong, Eng-Chuan Low, Dan Ping Li, Liming Jin, Huajiang Zhang, Chin Heng Leow, Soong Lin Chew, Uday Dasgupta, Chee-Hong Yong, Tianbao Gao, Geok Teng Ong, Wee Guan Tan, Weimin Shu, Chee-Lee Heng, Osama Shana'a:
9.1 A self-calibrating NFC SoC with a triple-mode reconfigurable PLL and a single-path PICC-PCD receiver in 0.11μm CMOS. 158-159 - Shuli Geng, Dang Liu, Yanfeng Li, Huiying Zhuo, Woogeun Rhee, Zhihua Wang:
9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications. 160-161 - Fei Chen, Yu Li, Dang Liu, Woogeun Rhee, Jongjin Kim, Dong-Wook Kim, Zhihua Wang:
9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability. 162-163 - Zhicheng Lin, Pui-In Mak, Rui Paulo Martins:
9.4 A 0.5V 1.15mW 0.2mm2 Sub-GHz ZigBee receiver supporting 433/860/915/960MHz ISM bands with zero external components. 164-165 - Yao-Hong Liu, Ao Ba, Johan H. C. van den Heuvel, Kathleen Philips, Guido Dolmans, Harmke de Groot:
9.5 A 1.2nJ/b 2.4GHz receiver with a sliding-IF phase-to-digital converter for wireless personal/body-area networks. 166-167 - Jiao Cheng, Nan Qi, Patrick Yin Chiang, Arun Natarajan:
9.6 A 1.3mW 0.6V WBAN-compatible sub-sampling PSK receiver in 65nm CMOS. 168-169 - Maja Vidojkovic, Xiongchuan Huang, Xiaoyan Wang, Cui Zhou, Ao Ba, Maarten Lont, Yao-Hong Liu, Pieter Harpe, Ming Ding, Ben Busze, Nauman F. Kiyani, Kouichi Kanda, Shoichi Masui, Kathleen Philips, Harmke de Groot:
9.7 A 0.33nJ/b IEEE802.15.6/proprietary-MICS/ISM-band transceiver with scalable data-rate from 11kb/s to 4.5Mb/s for medical applications. 170-171 - Vamshi Krishna Chillara, Yao-Hong Liu, Bindi Wang, Ao Ba, Maja Vidojkovic, Kathleen Philips, Harmke de Groot, Robert Bogdan Staszewski:
9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications. 172-173 - Martin Saint-Laurent, Paul Bassett, Ken Lin, Yuhe Wang, Son Le, Xufeng Chen, Maen Alradaideh, Tom Wernimont, Kartik Ayyar, Dan Bui, Dwight Galbi, Allan Lester, Willie Anderson:
10.1 A 28nm DSP powered by an on-chip LDO for high-performance and energy-efficient mobile applications. 176-177 - Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Noriaki Maeda, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori:
10.2 A 28nm HPM heterogeneous multi-core mobile application processor with 2GHz cores and low-power 1GHz cores. 178-179 - Alice Wang, Tsung-Yao Lin, Shichin Ouyang, Wei-Hung Huang, Jidong Wang, Shu-Hsin Chang, Sheng-Ping Chen, Chun-Hsiung Hu, J. C. Tai, Koan-Sin Tan, Meng-Nan Tsou, Ming-Hsien Lee, Gordon Gammie, Chi-Wei Yang, Chih-Chieh Yang, Yeh-Chi Chou, Shih-Hung Lin, Wuan Kuo, Chi-Jui Chung, Lee-Kee Yong, Chia-Wei Wang, Kin Hooi Dia, Cheng-Hsing Chien, You-Ming Tsao, N. K. Singh, Rolf Lagerquist, Chih-Cheng Chen, Uming Ko:
10.3 heterogeneous multi-processing quad-core CPU and dual-GPU design for optimal performance, power, and thermal tradeoffs in a 28nm mobile application processor. 180-181 - Gyeonghoon Kim, Youchang Kim, Kyuho Jason Lee, Seongwook Park, Injoon Hong, Kyeongryeol Bong, Dongjoo Shin, Sungpill Choi, Jinwook Oh, Hoi-Jun Yoo:
10.4 A 1.22TOPS and 1.52mW/MHz augmented reality multi-core processor with neural network NoC for HMD applications. 182-183 - Noboru Sakimura, Yukihide Tsuji, Ryusuke Nebashi, Hiroaki Honjo, Ayuka Morioka, Kunihiko Ishihara, Keizo Kinoshita, Shunsuke Fukami, Sadahiko Miura, Naoki Kasai, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Tadahiko Sugibayashi:
10.5 A 90nm 20MHz fully nonvolatile microcontroller for standby-power-critical applications. 184-185 - Christian Bachmann, Gert-Jan van Schaik, Ben Busze, Mario Konijnenburg, Yan Zhang, Jan Stuyt, Maryam Ashouei, Guido Dolmans, Tobias Gemmeke, Harmke de Groot:
10.6 A 0.74V 200μW multi-standard transceiver digital baseband in 40nm LP-CMOS for 2.4GHz Bluetooth Smart / ZigBee / IEEE 802.15.6 personal area networks. 186-187 - Benedikt Noethen, Oliver Arnold, Esther P. Adeva, Tobias Seifert, Erik Fischer, Steffen Kunze, Emil Matús, Gerhard P. Fettweis, Holger Eisenreich, Georg Ellguth, Stephan Hartmann, Sebastian Höppner, Stefan Schiefer, J.-U. Schlusler, Stefan Scholze, Dennis Walter, René Schüffny:
10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS. 188-189 - Michael Breschel, Peter Almers, Fredrik Angsmark, Alberth Arvidsson, Harald Bauer, Kees van Berkel, Joaquin Canovas, Minh Do, Anders Ekelund, Torsten Larsson, Bo Lincoln, Magnus Malmberg, Masao Naruse, Masashi Onishi, Christer Östberg, Jean-Paul Smeets, Mario Vergara Escobar, Juergen Voelkl, Emma Wittenmark:
10.8 A multi-standard 2G/3G/4G Cellular modem supporting carrier aggregation in 28nm CMOS. 190-191 - Pieter Harpe, Eugenio Cantatore, Arthur H. M. van Roermund:
11.1 An oversampled 12/14b SAR ADC with noise reduction and linearity enhancements achieving up to 79.1dB SNDR. 194-195 - Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, Hsin-Shu Chen:
11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS. 196-197 - Frank M. Yaul, Anantha P. Chandrakasan:
11.3 A 10b 0.6nW SAR ADC with data-dependent energy savings using LSB-first successive approximation. 198-199 - Frank M. L. van der Goes, Christopher M. Ward, Santosh Astgimath, Han Yan, Jeff Riley, Jan Mulder, Sijia Wang, Klaas Bult:
11.4 A 1.5mW 68dB SNDR 80MS/s 2× interleaved SAR-assisted pipelined ADC in 28nm CMOS. 200-201 - Yong Lim, Michael P. Flynn:
11.5 A 100MS/s 10.5b 2.46mW comparator-less pipeline ADC using self-biased ring amplifiers. 202-203 - Dong-Young Chang, Carlos E. Muñoz, Denis C. Daly, Soon-Kyun Shin, Kevin Guay, Thomas Thurston, Hae-Seung Lee, Kush Gulati, Matthew Z. Straayer:
11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. 204-205 - Hans Van de Vel, Joost Briaire, Corné Bastiaansen, Pieter C. W. van Beek, Govert Geelen, Harrie Gunnink, Yongjie Jin, Mustafa Kaba, Kerong Luo, Edward J. F. Paulus, Bang Pham, William Relyveld, Peter Zijlstra:
11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS with. 206-207 - Richard J. Przybyla, Hao-Yen Tang, Stefon E. Shelton, David A. Horsley, Bernhard E. Boser:
12.1 3D ultrasonic gesture recognition. 210-211 - Yingzhe Hu, Liechao Huang, Warren Rieutort-Louis, Josue Sanz-Robinson, Sigurd Wagner, James C. Sturm, Naveen Verma:
12.2 3D gesture-sensing system for interactive displays based on extended-range capacitive sensing. 212-213 - Mutsumi Hamaguchi, Akira Nagao, Masayuki Miyamoto:
12.3 A 240Hz-reporting-rate 143×81 mutual-capacitance touch-sensing analog front-end IC with 37dB SNR for 1mm-diameter stylus. 214-215 - Noriyuki Miura, Shiro Dosho, Satoshi Takaya, Daisuke Fujimoto, Takuya Kiriyama, Hiroyuki Tezuka, Takuji Miki, Hiroto Yanagawa, Makoto Nagata:
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan. 216-217 - Hongjae Jang, Hyungcheol Shin, Seunghoon Ko, Ilhyun Yun, Kwyro Lee:
12.5 2D Coded-aperture-based ultra-compact capacitive touch-screen controller with 40 reconfigurable channels. 218-219 - Hyunsoo Ha, Dennis Sylvester, David T. Blaauw, Jae-Yoon Sim:
12.6 A 160nW 63.9fJ/conversion-step capacitance-to-digital converter for ultra-low-power wireless sensor nodes. 220-221 - Kamran Souri, Youngcheol Chae, Frank Thus, Kofi A. A. Makinwa:
12.7 A 0.85V 600nW all-CMOS temperature sensor with an inaccuracy of ±0.4°C (3σ) from -40 to 125°C. 222-223 - Ali Heidary, Guijie Wang, Kofi A. A. Makinwa, Gerard C. M. Meijer:
12.8 A BJT-based CMOS temperature sensor with a 3.6pJ·K2-resolution FoM. 224-225 - Samira Zali Asl, Shouvik Mukherjee, Lijun Will Chen, Kimo Joo, Rajkumar Palwai, Niveditha Arumugam, P. Galle, Meghan Phadke, Charles Grosjean, Jim Salvia, Haechang Lee, Sudhakar Pamarti, Terri S. Fiez, Kofi A. A. Makinwa, Aaron Partridge, Vinod Menon:
12.9 A 1.55×0.85mm2 3ppm 1.0μA 32.768kHz MEMS-based oscillator. 226-227 - Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang:
13.1 A 1Gb 2GHz embedded DRAM in 22nm tri-gate CMOS technology. 230-231 - Taejoong Song, Woojin Rim, Jonghoon Jung, Giyong Yang, Jaeho Park, Sunghyun Park, Kang-Hyun Baek, Sanghoon Baek, Sang-Kyu Oh, Jinsuk Jung, Sungbong Kim, Gyu-Hong Kim, Jintae Kim, Young-Keun Lee, Kee Sup Kim, Sang-Pil Sim, Jong Shik Yoon, Kyu-Myung Choi:
13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. 232-233 - Makoto Yabuuchi, Yasumasa Tsukamoto, Masao Morimoto, Miki Tanaka, Koji Nii:
13.3 20nm High-density single-port and dual-port SRAMs with wordline-voltage-adjustment system for read/write assists. 234-235 - Toshikazu Fukuda, Koji Kohara, Toshiaki Dozaka, Yasuhisa Takeyama, Tsuyoshi Midorikawa, Kenji Hashimoto, Ichiro Wakiyama, Shinji Miyano, Takehiko Hojo:
13.4 A 7ns-access-time 25μW/MHz 128kb SRAM for low-power fast wake-up MCU in 65nm CMOS with 27fA/b retention current. 236-237 - Yen-Huei Chen, Wei-Min Chan, Wei-Cheng Wu, Hung-Jen Liao, Kuo-Hua Pan, Jhon-Jhy Liaw, Tang-Hsuan Chung, Quincy Li, George H. Chang, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu, Sreedhar Natarajan, Jonathan Chang:
13.5 A 16nm 128Mb SRAM in high-κ metal-gate FinFET technology with write-assist circuitry for low-VMIN applications. 238-239 - Koji Nii, Teruhiko Amano, Naoya Watanabe, Minoru Yamawaki, Kenji Yoshinaga, Mihoko Wada, Isamu Hayashi:
13.6 A 28nm 400MHz 4-parallel 1.6Gsearch/s 80Mb ternary CAM. 240-241 - Bharan Giridhar, Nathaniel Ross Pinckney, Dennis Sylvester, David T. Blaauw:
13.7 A reconfigurable sense amplifier with auto-zero calibration and pre-amplification in 28nm CMOS. 242-243 - Fabio Frustaci, Mahmood Khayatzadeh, David T. Blaauw, Dennis Sylvester, Massimo Alioto:
13.8 A 32kb SRAM for error-free and error-tolerant applications with dynamic energy-quality management in 28nm CMOS. 244-245 - Dixian Zhao, Patrick Reynaert:
14.1 A 0.9V 20.9dBm 22.3%-PAE E-band power amplifier with broadband parallel-series power combiner in 40nm CMOS. 248-249 - Vito Giannini, Davide Guermandi, Qixian Shi, Kristof Vaesen, Bertrand Parvais, Wim Van Thillo, André Bourdoux, Charlotte Soens, Jan Craninckx, Piet Wambacq:
14.2 A 79GHz phase-modulated 4GHz-BW CW radar TX in 28nm CMOS. 250-251 - Shailesh Kulkarni, Patrick Reynaert:
14.3 A Push-Pull mm-Wave power amplifier with. 252-253 - Seyed Yahya Mortazavi, Kwang-Jin Koh:
14.4 A Class F-1/F 24-to-31GHz power amplifier with 40.7% peak PAE, 15dBm OP1dB, and 50mW Psat in 0.13μm SiGe BiCMOS. 254-255 - Ullrich R. Pfeiffer, Yan Zhao, Janus Grzyb, Richard Al Hadi, Neelanjan Sarmah, Wolfgang Forster, Holger Rücker, Bernd Heinemann:
14.5 A 0.53THz reconfigurable source array with up to 1mW radiated power for terahertz imaging applications in 0.13μm SiGe BiCMOS. 256-257 - Yahya M. Tousi, Ehsan Afshari:
14.6 A scalable THz 2D phased array with +17dBm of EIRP at 338GHz in 65nm bulk CMOS. 258-259