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ORCIDISVLSI 2002: Pittsburgh, PA, USA
- 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 25-26 April 2002, Pittsburgh, PA, USA. IEEE Computer Society 2002, ISBN 0-7695-1486-3
Emerging Trends in VLSI Systems
- Wayne H. Wolf, I. Burak Özer, Tiehan Lv:
VLSI Systems for Embedded Video. 3-6 - Alice Wang, Anantha P. Chandrakasan, Stephen V. Kosonocky:
Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits. 7-14
System Level Design
- Asim Smailagic, Matthew Ettus:
System Design and Power Optimization for Mobile Computers. 15-19 - Ismail Kadayif, Mahmut T. Kandemir, Narayanan Vijaykrishnan, Mary Jane Irwin:
Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications. 20-25 - Ahmed M. Shams, Wendi Pan
, Archana Chidanandan, Magdy A. Bayoumi:
A Low Power High Performance Distributed DCT Architecture. 26-34
Advanced VLSI Design
- Vikas Chandra, Herman Schmit:
Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach. 35-40 - Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Optimal Timing for Skew-Tolerant High-Speed Domino Logic. 41-46 - Mitchell A. Thornton, Rolf Drechsler, D. Michael Miller:
Multi-Output Timed Shannon Circuits. 47-52 - Adnan Abdul-Aziz Gutub, Alexandre F. Tenca, Çetin Kaya Koç:
Scalable VLSI Architecture for GF(p) Montgomery Modular Inverse Computation. 53-58
Low Power VLSI System Design
- David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin:
Impact of Technology Scaling in the Clock System Power. 59-64 - Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna:
Datapath Scheduling using Dynamic Frequency Clocking. 65-70 - Kaveh Shakeri, James D. Meindl:
Temperature Variable Supply Voltage for Power Reduction. 71-74 - Suvodeep Gupta, Srinivas Katkoori:
Force-Directed Scheduling for Dynamic Power Optimization. 75-82
VLSI Circuits and Systems
- Jerry W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li:
Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. 83-88 - Mohamed A. Elgamel, Tarek Darwish, Magdy A. Bayoumi:
Noise Tolerant Low Power Dynamic TSPCL D Flip-Flops. 89-94 - Naotaka Ohsawa, Masanori Hariyama, Michitaka Kameyama:
High-Performance Field Programmable VLSI Processor Based on a Direct Allocation of a Control/Data Flow Graph. 95-100 - Shiuh-Rong Huang, Lan-Rong Dung:
VLSI Implementation for MAC-Level DWT Architecture. 101-106 - Scott C. Smith:
Speedup of Self-Timed Digital Systems Using Early Completion. 107-116
System-on-a-Chip Design
- Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani:
A Network on Chip Architecture and Design Methodology. 117-124 - Henry Y. H. Chuang, David P. Birch, Li-Chang Liu, Jong-Chih Chien, Steven P. Levitan, Ching-Chung Li:
A High Speed Shift-Invariant Wavelet Transform Chip for Video Compression. 125-134
Physical Design, Synthesis, and Optimization
- Ingmar Neumann, Kolja Sulimma, Wolfgang Kunz:
Accelerating Retiming Under the Coupled-Edge Timing Model. 135-140 - Anil Bahuman, Benjamin Bishop, Khaled Rasheed:
Automated Synthesis of Standard Cells using Genetic Algorithms. 141-150
Test and Verification
- Markus Wedler, Dominik Stoffel, Wolfgang Kunz:
Improving Structural FSM Traversal by Constraint-Satisfying Logic Simulation. 151-158 - Bassam Shaer, Khaled Dib:
An Efficient Partitioning Algorithm of Combinational CMOS Circuits. 159-164 - Srdjan Dragic, Martin Margala:
A 1.2V Built-In Architecture for High Frequency On-Line Iddq/delta Iddq Test. 165-170
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