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ORCID2. IVSW 2017: Thessaloniki, Greece
- IEEE 2nd International Verification and Security Workshop, IVSW 2017, Thessaloniki, Greece, July 3-5, 2017. IEEE 2017, ISBN 978-1-5386-1708-3
- David McCann, Elisabeth Oswald:
Practical evaluation of masking software countermeasures on an IoT processor. 1-6 - Jan Burchard, Ange-Salomé Messeng Ekossono, Jan Horácek, Mael Gay, Bernd Becker
, Tobias Schubert, Martin Kreuzer, Ilia Polian:
Towards mixed structural-functional models for algebraic fault attacks on ciphers. 7-12 - Seyed-Abdollah Aftabjahani, Amitabh Das:
Robust secure design by increasing the resilience of Attack Protection Blocks. 13-18 - Mohd Syafiq Mispan, Basel Halak, Mark Zwolinski:
Lightweight obfuscation techniques for modeling attacks resistant PUFs. 19-24 - Rachael J. Parker:
Entropy justification for metastability based nondeterministic random bit generator. 25-30 - Gregoire Gimenez, Abdelkarim Cherkaoui, Raphael Frisch, Laurent Fesquet:
Self-timed Ring based True Random Number Generator: Threat model and countermeasures. 31-38 - Kaibin Huang, Raylin Tso:
Provable secure dual-server public key encryption with keyword search. 39-44 - Mathieu Da Silva, Marie-Lise Flottes, Giorgio Di Natale, Bruno Rouzeyre:
Experimentations on scan chain encryption with PRESENT. 45-50 - Giorgio Di Natale, Marie-Lise Flottes, Sophie Dupuis, Bruno Rouzeyre:
Hacking the Control Flow error detection mechanism. 51-56 - Cyril Bresch, Adrien Michelet, Laurent Amato, Thomas Meyer, David Hély:
A red team blue team approach towards a secure processor design with hardware shadow stack. 57-62 - Padelis Papadopoulos, Anand Raman, Yorgos Koutsoyannopoulos, Nikolas Provatas, Magdy Abadir:
Challenges and trends in SOC Electromagnetic (EM) Crosstalk. 63-69 - Evan Chavis, Harrison Davis, Yijun Hou, Matthew Hicks, Salessawi Ferede Yitbarek, Todd M. Austin, Valeria Bertacco:
SNIFFER: A high-accuracy malware detector for enterprise-based systems. 70-75 - Elena Lai Leng Woo, Mark Zwolinski, Basel Halak:
Hardware performance counters for system reliability monitoring. 76-81 - Eli Weintraub:
Estimating Target Distribution in security assessment models. 82-87 - Marc Fyrbiak, Sebastian Strauss, Christian Kison, Sebastian Wallat, Malte Elson, Nikol Rummel, Christof Paar:
Hardware reverse engineering: Overview and open challenges. 88-94 - Sebastian Wallat, Marc Fyrbiak, Moritz Schlögel, Christof Paar:
A look at the dark side of hardware reverse engineering - a case study. 95-100 - Bozena Kaminska, Jasbir N. Patel, Hao Jiang:
Secure authentication of electronic systems with autonomous optical nano-devices. 101-104 - Ryan Berryhill, Neil Veira, Andreas G. Veneris, Zissis Poulos:
Learning lemma support graphs in Quip and IC3. 105-110 - Erwan Fabiani, Loïc Lagadec, Mohamed Ben Hammouda, Ciprian Teodorov:
Asserting causal properties in High Level Synthesis. 111-116 - Steve Trimberger, Steve McNeil:
Security of FPGAs in data centers. 117-122 - Karen Horovitz, Meha Kainth, Ryan Kenny:
Protecting partial regions in FPGA bitstreams. 123-127 - Elena-Ioana Vatajelu, Giorgio Di Natale, Paolo Prinetto:
Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories. 128-133 - Debapriya Basu Roy, Shivam Bhasin, Ivica Nikolic, Debdeep Mukhopadhyay:
Opening pandora's box: Implication of RLUT on secure FPGA applications and IP security. 134-139 - Jo Vliegen, Oscar Reparaz, Nele Mentens:
Maximizing the throughput of threshold-protected AES-GCM implementations on FPGA. 140-145 - Ugo Mureddu, Oto Petura, Nathalie Bochard, Lilian Bossuet, Viktor Fischer:
Efficient design of Oscillator based Physical Unclonable Functions on Flash FPGAs. 146-151
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