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ORCID11. IWLS 2002: New Orleans, Louisiana, USA
- 11th IEEE/ACM International Workshop on Logic & Synthesis, IWLS 2002, June 4-7, 2002, New Orleans, Louisiana, USA. 2002
Structured Logic Synthesis
- Prabhakar Kudva, Andrew Sullivan, William E. Dougherty:
Metrics for Structural Logic Synthesis. IWLS 2002: 1-6 - Fan Mo, Robert K. Brayton:
Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design. IWLS 2002: 7-12 - Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton:
Topologically Constrained Logic Synthesis. IWLS 2002: 13-20 - Anas Al-Rabadi, Lee W. Casperson:
Optical Realizations of Reversible Logic. IWLS 2002: 21-26 - Theodore W. Manikas, Gerald R. Kane:
Partitioning Effects on Estimated Wire Length for Mixed Macro and Standard Cell Placement. IWLS 2002: 27-30 - Pawel Kerntopf:
An Approach to Designing Complex Reversible Logic Gates. IWLS 2002: 31-36 - Mohamed A. Elgamel, Magdy A. Bayoumi:
On Low Power High Level Synthesis Using Genetic Algorithms. IWLS 2002: 37-40 - Hua Tang, Alex Doboli:
Layout-Aware Synthesis Methodology for Analog Systems Based on Combined Block Sizing, Floorplanning and Global Routing. IWLS 2002: 41-44 - Nina Yevtushenko, Tiziano Villa, Robert K. Brayton, Alexandre Petrenko, Alberto L. Sangiovanni-Vincentelli:
Equisolvability of Series vs. Controller's Topology in Synchronous Language Equations. IWLS 2002: 45-50 - Tomas Bengtsson, Andrés Martinelli, Elena Dubrova:
A Fast Heuristic Algorithm for Disjunctive. IWLS 2002: 51-56 - Nattawut Thepayasuwan, Alex Doboli:
A Methodology for Core Placement and Bus Synthesis under Time, Area and Energy Consumption Constraints. IWLS 2002: 57-60 - Yen-Jen Chang, Feipei Lai, Shanq-Jang Ruan:
An Efficient Two-Level Filter Scheme for Low Power Cache. IWLS 2002: 61-66 - Svetlana N. Yanushkevich, Vlad P. Shmerko, V. D. Malyugin, Piotr Dziurzanski:
Linearity of World-Level Circuit Models: New Understanding. IWLS 2002: 67-72 - Jorgiano Vidal, David Déharbe, Dominique Borrione:
Improving Static Ordering of BDDs for Reachability Analysis. IWLS 2002: 73-77 - Mukul R. Prasad, Michael S. Hsiao, Jawahar Jain:
Improving Sequential ATPG Using SAT Methods. IWLS 2002: 79-84 - Pawel Kerntopf:
Nonlinear Sifting of Decision Diagrams. IWLS 2002: 85-90
Reconfigurable Architectures
- Jason Cong, Joey Y. Lin, Wangning Long:
Enhanced SPFD Rewiring on Improving Rewiring Ability. IWLS 2002: 91-96 - Amit Prakash, Ramakrishna Kotla, Tanmoy Mandal, Adnan Aziz:
A Reconfigurable Architecture and Associated Synthesis Methodology for High Speed Packet Classification. IWLS 2002: 97-102 - Yoshihisa Kojima, Hiroshi Saito, Kenshu Seto, Satoshi Komatsu, Masahiro Fujita:
Field Modifiable Architecture and its Design Methodology: System Design Without Logic Synthesis. IWLS 2002: 103-108 - Silviu M. S. A. Chiricescu, Michael A. Schuette, Herman Schmit, Robin Glinton:
Synthesis of Morphable Multipliers. IWLS 2002: 109-113 - Alan Mishchenko, Tsutomu Sasao:
Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. IWLS 2002: 115-120
Novel Design Styles
- Petra Färm, Elena Dubrova:
Technology Mapping for Chemically Assembled Electronic Nanotechnology. IWLS 2002: 121-124 - Vivek V. Shende, Aditya K. Prasad, Igor L. Markov, John P. Hayes:
Reversible Logic Circuit Synthesis. IWLS 2002: 125-130
Poster Session #2
- Fadi A. Aloul, Maher N. Mneimneh, Karem A. Sakallah:
ZBDD-Based Backtrack Search SAT Solver. IWLS 2002: 131-136 - Fadi A. Aloul, Igor L. Markov, Karem A. Sakallah:
Efficient Gate and Input Ordering for Circuit-to-BDD Conversion. IWLS 2002: 137-142 - Mikael Kerttu, Per Lindgren, Rolf Drechsler, Mitchell A. Thornton:
Low Power Optimization Techniques for BDD Mapped Finite State Machines. IWLS 2002: 143-148 - Chia-Chih Yen, Kuang-Chien Chen, Jing-Yang Jou:
A Practical Approach to Cycle Bound Estimation for Property Checking. IWLS 2002: 149-154 - Agnes Madalinski, Alexandre V. Bystrov, Alexandre Yakovlev:
Visualization of Coding Conflicts in Asynchronous Circuit Design. IWLS 2002: 155-160 - S. G. Gibb, Laurence E. Turner:
The Automatic Generation of Application Specific Processors. IWLS 2002: 161-165 - Loïc Lagadec, Bernard Pottier, Oscar Villellas, Erwan Fabiani, Catherine Dezan:
A LUT based Approach for High Level Synthesis on FPGAs. IWLS 2002: 167-172 - Alan Mishchenko, Robert K. Brayton:
A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS 2002: 173-177 - Leyla Nazhandali, Karem A. Sakallah:
Majority-Based Decomposition of Carry Logic in Binary Adders. IWLS 2002: 179-184 - Jun Yuan, Ken Albin, Adnan Aziz, Carl Pixley:
Simplifying Constraint Solving in Random Simulation Generation. IWLS 2002: 185-190 - Anh Vu Dihn Duc, Laurent Fesquet, Marc Renaudin:
Synthesis of QDI Asynchronous Circuits from DTL-Style Petri-Net. IWLS 2002: 191-196 - Alan Mishchenko, Marek A. Perkowski:
Logic Synthesis of Reversible Wave Cascades. IWLS 2002: 197-202
Custom, PTL and Dynamic Circuits
- Hui-Yuan Song, R. Iris Bahar, Joel Grodstein:
Timing Analysis for Full-Custom Circuits Using Symbolic DC Formulations. IWLS 2002: 203-208 - Rupesh S. Shelar, Sachin S. Sapatnekar:
Efficient Layout Synthesis Algorithm for Pass Transistor Logic Circuits. IWLS 2002: 209-214 - Xinning Wang, Prashant Sawkar, Barbara A. Chappell:
A Constructive Matching Algorithm for Library-Based Domino Technology Mapping. IWLS 2002: 215-220 - Federico Politi:
Recognition of Transistor Level Complex Sequential and Dynamic Circuits using State Based BDD's. IWLS 2002: 221-226
Restructuring Logic Transformations
- Cliff C. N. Sze, Ting-Chi Wang:
Multi-Level Circuit Clustering for Delay Minimization. IWLS 2002: 227-232 - Jordi Cortadella:
Bi-Decomposition and Tree-Height Reduction for Timing Optimization. IWLS 2002: 233-238 - Alexandre V. Bystrov, Alexandre Yakovlev:
Synthesis of Asynchronous Circuits with Predictable Latency. IWLS 2002: 239-243 - Hiroshi Saito, Hiroshi Nakamura, Masahiro Fujita, Takashi Nanya:
Logic Optimization for Asynchronous SI Controllers using Transduction Method. IWLS 2002: 245-250
Poster Session #3
- Whitney J. Townsend, Mitchell A. Thornton, Parag K. Lala:
On-line Error Detection in a Carry-free Adder. IWLS 2002: 251-254 - Amit Tandon, Federico Politi:
Model Generation and Gate Level Abstraction of Complex CMOS Custom Design for Functional and DFT Validation. IWLS 2002: 255-260 - Andrei B. Khlopotine, Marek A. Perkowski, Pawel Kerntopf:
Reversible Logic Synthesis by Iterative Compositions. IWLS 2002: 261-266 - Ankur Srivastava, Majid Sarrafzadeh:
Predictability: Definition, Analysis and Optimization. IWLS 2002: 267-272 - Anas Al-Rabadi:
Symmetry as a Base for a New Decomposition of Boolean Logic. IWLS 2002: 273-278 - Masayuki Tsukisaka, Masashi Imai, Takashi Nanya:
High Throughput Asynchronous Domino Using Dual output Buffer. IWLS 2002: 279-282 - Masanori Hashimoto, Yashiteru Hayashi, Hidetoshi Onodera:
Experimental Study on Cell-Base High-Performance Datapath Design. IWLS 2002: 283-287 - Geun Rae Cho, Tom Chen:
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis. IWLS 2002: 289-294 - Chang Woo Kang, Massoud Pedram:
Technology Mapping for Low Leakage Power with Hot-Carrier Effect Consideration. IWLS 2002: 295-300
Analysis Techniques
- Jie-Hong Roland Jiang, Robert K. Brayton:
On the Verification of Sequential Equivalence. IWLS 2002: 307-314 - Farzan Fallah:
Binary Time Frame Expansion. IWLS 2002: 314-319 - René Krenz, Elena Dubrova, Andreas Kuehlmann:
Circuit-Based Evaluation of the Arithmetic Transform of Boolean Functions. IWLS 2002: 321-326
Don't Cares and Logic Optimization
- Yunjian Jiang, Robert K. Brayton:
Don't Care Computation in Minimizing Extended Finite State Machines with Presburger Arithmetic. IWLS 2002: 327-332 - Alan Mishchenko, Robert K. Brayton:
Simplification of Non-Deterministic Multi-Valued Networks. IWLS 2002: 333-338 - Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton:
Reducing Multi-Valued Algebraic Operations to Binary. IWLS 2002: 339-344 - Anna Bernasconi, Valentina Ciriani, Fabrizio Luccio, Linda Pagli:
Implicit Test of Regularity for Not Completely Specified Boolean Functions. IWLS 2002: 345-350
Poster Session #4
- Jun Yuan, Kurt Shultz, John Havlicek, Ken Albin, Adnan Aziz:
A Method for Synthesizing Boolean Constrains. IWLS 2002: 351-353 - Tiberiu Chelcea, Steven M. Nowick:
Resynthesis and Peephole Transformations for the Optimization of Large-Scale Asynchronous Systems. IWLS 2002: 355-360 - Felipe Ribeiro Schneider, Vinícius P. Correia, Renato P. Ribas, André Inácio Reis:
Comparing Transistor-Level Implementations of 4-Input Logic Functions. IWLS 2002: 361-365 - Rajeev Murgai:
Net Buffering in the Presence of Multiple Timing Views. IWLS 2002: 367-372
SAT and BDD's
- DoRon B. Motter, Igor L. Markov:
Overcoming Resolution-Based Lower Bounds for SAT Solvers. IWLS 2002: 373-378 - Tsutomu Sasao, Yukihiro Iguchi, Munehiro Matsuura:
Comparison of Decision Diagrams for Multiple-Output Logic Functions. IWLS 2002: 379-384 - Christoph Meinel, Harald Sack, Volker Schillings:
VisBDD - A Web-based Visualization Framework for OBDD Algorithms. IWLS 2002: 385-390 - Christoph Meinel, Christian Stangier:
Modular Partitioning and Dynamic Conjunction Scheduling in Image Computation. IWLS 2002: 391-396
Optical and Mixed-Technology Systems: Where Election Meet Laser Beams
- Jaijeet S. Roychowdhury:
Optical Systems 101 for EDA Practitioners. IWLS 2002: 397 - Steven P. Levitan:
Giga = 1/Nano: CAD Tools and Modeling Challenges for Giga-Scale Mixed Technology Micro-Systems. IWLS 2002: 399
High-Level Language and Synthesis
- Stephen A. Edwards:
High-Level Synthesis from the Synchronous Language Esterel. IWLS 2002: 401-406 - Nick Savoiu, Sandeep K. Shukla, Rajesh K. Gupta:
Concurrency in System Level Design: Conflict Between Simulation and Synthesis Goals. IWLS 2002: 407-411
Power Issues
- Miodrag Vujkovic, Carl Sechen:
Optimized Power-Delay Curve Generation for Standard Cell ICs. IWLS 2002: 413-418 - Afshin Abdollahi, Farzan Fallah:
Runtime Mechanisms for Leakage Current Reduction in CMOS VLSI Circuits. IWLS 2002: 419-424
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