default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCID46th MICRO 2013: Davis, CA, USA
- Matthew K. Farrens, Christos Kozyrakis:
The 46th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-46, Davis, CA, USA, December 7-11, 2013. ACM 2013, ISBN 978-1-4503-2638-4
Approximate computing
- Swagath Venkataramani, Vinay K. Chippa, Srimat T. Chakradhar, Kaushik Roy, Anand Raghunathan
:
Quality programmable vector processors for approximate computing. 1-12 - Mehrzad Samadi, Janghaeng Lee, Davoud Anoushe Jamshidi, Amir Hormati, Scott A. Mahlke:
SAGE: self-tuning approximation for graphics engines. 13-24 - Adrian Sampson, Jacob Nelson, Karin Strauss, Luis Ceze:
Approximate storage in solid-state memories. 25-36
Energy optimizations
- Yuya Kora, Kyohei Yamaguchi, Hideki Ando:
MLP-aware dynamic instruction window resizing for adaptively exploiting both ILP and MLP. 37-48 - Andreas Sembrant, Erik Hagersten, David Black-Schaffer:
TLC: a tag-less cache for reducing dynamic first level cache energy. 49-61 - Somayeh Sardashti, David A. Wood:
Decoupled compressed cache: exploiting spatial locality for energy-optimized compressed caching. 62-73
Power-efficient GPUs
- Syed Zohaib Gilani, Nam Sung Kim, Michael J. Schulte:
Exploiting GPU peak-power and performance tradeoffs through reduced effective pipeline latency. 74-85 - Minsoo Rhu, Michael B. Sullivan, Jingwen Leng, Mattan Erez:
A locality-aware memory hierarchy for energy-efficient GPU architectures. 86-98 - Timothy G. Rogers, Mike O'Connor, Tor M. Aamodt:
Divergence-aware warp scheduling. 99-110 - Mohammad Abdel-Majeed, Daniel Wong, Murali Annavaram:
Warped gates: gating aware scheduling and power gating for GPGPUs. 111-122
Resilience
- Raghuraman Balasubramanian, Karthikeyan Sankaralingam:
Virtually-aged sampling DMR: unifying circuit failure prediction and circuit failure detection. 123-135 - Hyungjun Kim, Arseniy Vitkovskiy, Paul V. Gratz, Vassos Soteriou:
Use it or lose it: wear-out and lifetime in future chip multiprocessors. 136-147 - Ritesh Parikh, Valeria Bertacco:
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults. 148-159 - Yiannakis Sazeides, Emre Özer, Danny Kershaw, Panagiota Nikolaou, Marios Kleanthous, Jaume Abella:
Implicit-storing and redundant-encoding-of-attribute information in error-correction-codes. 160-171
Main memory
- Gennady Pekhimenko, Vivek Seshadri, Yoongu Kim, Hongyi Xin, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
Linearly compressed pages: a low-complexity, low-latency main memory compression framework. 172-184 - Vivek Seshadri, Yoongu Kim, Chris Fallin, Donghyuk Lee, Rachata Ausavarungnirun, Gennady Pekhimenko, Yixin Luo, Onur Mutlu, Phillip B. Gibbons, Michael A. Kozuch, Todd C. Mowry:
RowClone: fast and energy-efficient in-DRAM bulk data copy and initialization. 185-197 - Manjunath Shevgoor, Jung-Sik Kim, Niladrish Chatterjee, Rajeev Balasubramonian, Al Davis, Aniruddha N. Udipi:
Quantifying the relationship between the power delivery network and architectural policies in a 3D-stacked memory device. 198-209
Power management & interconnects
- Augusto Vega, Alper Buyuktosunoglu, Heather Hanson, Pradip Bose, Srinivasan Ramani:
Crank it up or dial it down: coordinated multiprocessor frequency and folding control. 210-221 - Arslan Zulfiqar, Pranay Koka, Herb Schwetman, Mikko H. Lipasti, Xuezhe Zheng, Ashok V. Krishnamoorthy:
Wavelength stealing: an opportunistic approach to channel sharing in multi-chip photonic interconnects. 222-233 - Mahdi Nazm Bojnordi, Engin Ipek:
DESC: energy-efficient data exchange using synchronized counters. 234-246
Prefetching
- Akanksha Jain, Calvin Lin:
Linearizing irregular memory accesses for improved correlated prefetching. 247-259 - Aasheesh Kolli, Ali G. Saidi, Thomas F. Wenisch:
RDIP: return-address-stack directed instruction prefetching. 260-271 - Cansu Kaynak, Boris Grot, Babak Falsafi:
SHIFT: shared history instruction fetch for lean-core server processors. 272-283
Cache management
- Daniel A. Jiménez:
Insertion and promotion for tree-based PseudoLRU last-level caches. 284-296 - Abhisek Pan, Vijay S. Pai:
Imbalanced cache partitioning for balanced data-parallel programs. 297-309 - Jorge Albericio, Pablo Ibáñez, Víctor Viñals, José M. Llabería:
The reuse cache: downsizing the shared last-level cache. 310-321
Programming, compilation, and provisioning
- Chao Li, Yang Hu, Ruijin Zhou, Ming Liu, Longjun Liu, Jingling Yuan, Tao Li:
Enabling datacenter servers to scale out economically and sustainably. 322-333 - Timothy Creech, Aparna Kotha, Rajeev Barua:
Efficient multiprogramming for multicores with SCAF. 334-345 - Hongbo Rong, Hyunchul Park, Cheng Wang, Youfeng Wu:
Allocating rotating registers by scheduling. 346-358
Coherence & memory management
- Jason Zebchuk, Babak Falsafi, Andreas Moshovos:
Multi-grain coherence directories. 359-370 - Xuehai Qian, Josep Torrellas, Benjamín Sahelices, Depei Qian:
BulkCommit: scalable and fast commit of atomic blocks in a lazy multiprocessor environment. 371-382 - Abhishek Bhattacharjee:
Large-reach memory management unit caches. 383-394
GPU memory management
- Jayesh Gaur, Raghuram Srinivasan, Sreenivas Subramoney, Mainak Chaudhuri:
Efficient management of last-level caches in graphics processors for 3D scene rendering workloads. 395-407 - Wilson W. L. Fung, Tor M. Aamodt:
Energy efficient GPU transactional memory via space-time optimizations. 408-420
Storage optimizations
- Jishen Zhao, Sheng Li, Doe Hyun Yoon, Yuan Xie, Norman P. Jouppi:
Kiln: closing the performance gap between systems with and without persistence support. 421-432 - Jie Fan, Song Jiang, Jiwu Shu, Youhui Zhang, Weimin Zhen:
Aegis: partitioning data block for efficient recovery of stuck-at-faults in phase change memory. 433-444
Heterogeneous computing
- Shruti Padmanabha, Andrew Lukefahr, Reetuparna Das, Scott A. Mahlke:
Trace based phase prediction for tightly-coupled heterogeneous cores. 445-456 - Jason Power, Arkaprava Basu, Junli Gu, Sooraj Puthoor, Bradford M. Beckmann, Mark D. Hill, Steven K. Reinhardt, David A. Wood:
Heterogeneous system coherence for integrated CPU-GPU systems. 457-467 - Yusuf Onur Koçberber, Boris Grot, Javier Picorel, Babak Falsafi, Kevin T. Lim, Parthasarathy Ranganathan:
Meet the walkers: accelerating index traversals for in-memory databases. 468-479
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-12-25 23:53 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
