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ORCIDMTDT 2002: Isle of Bendor, France
- 10th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT 2002), 10-12 July 2002, Isle of Bendor, France. IEEE Computer Society 2002, ISBN 0-7695-1617-3
- A. Kablanian:
Embedded Memory Test and Repair. MTDT 2002
Memory BIST Analysis and Application
- Alvin Jee:
Defect-Oriented Analysis of Memory BIST Tests. 7-11 - Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda
:
A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. 12-16 - Farzin Karimi, Fabrizio Lombardi:
A Scan-Bist Environment for Testing Embedded Memories. 17-
Memory ECC and Soft Errors
- Michael Nicolaidis:
Soft Error Protection for Embedded Memories. MTDT 2002 - Daniele Rossi, Cecilia Metra, Bruno Riccò:
Fast and Compact Error Correcting Scheme for Reliable Multilevel Flash Memories. 27-31 - Bernard Coloma, Patrick Delaunay, Olivier Husson:
High Speed 15 ns 4 Mbits SRAM for Space Application. 32-38
High Reliability in Railway and Automotive Systems
- Dominique Bied-Charreton, D. Guillon, B. Jacques:
The YATE Fail-Safe Interface: The User's Point of View. 39-43 - Alberto Manzone, Diego De Costantini:
Fault Tolerant Insertion and Verification: A Case Study. 44-48 - Luca Schiano, Cecilia Metra, Diego Marino:
Design and Implementation of a Self-Checking Scheme for Railway Trackside Systems. 49-56
Embedded Memory Yield Enhancement
- Emmanuel Rondey, Yann Tellier, Simone Borri:
A Silicon-Based Yield Gain Evaluation Methodology for Embedded-SRAMs with Different Redundancy Scenarios. 57-61 - Valery A. Vardanian, Yervant Zorian:
A March-Based Fault Location Algorithm for Static Random Access Memories. 62-67 - Rei-Fu Huang, Jin-Fu Li, Jen-Chieh Yeh, Cheng-Wen Wu:
A Simulator for Evaluating Redundancy Analysis Algorithms of Repairable Embedded Memories. 68- - M. Templeton:
Challenges and Opportunities Created by the SoC Shockwave. MTDT 2002
Embedded Memory Systems and Test Optimization
- Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu:
Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch. 83- - Toshiyuki Kaya, Isao Shirakawa, Ryusuke Miyamoto, Takao Onoye:
Design of Embedded System for Video Coding with Logic-Enhanced DRAM and Configurable Process. MTDT 2002 - Masashi Hashimoto:
Adder Merged DRAM Architecture. 88-94
Memory Test Strategies
- Said Hamdioui, Ad J. van de Goor, Mike Rodgers:
March SS: A Test for All Static Simple RAM Faults. 95-100 - Farzin Karimi, Fred J. Meyer, Fabrizio Lombardi:
Random Testing of Multi-Port Static Random Access Memories. 101-108
Fault Modeling
- Raja Venkatesh, Sailesh Kumar, Joji Philip, Sunil Shukla:
A Fault Modeling Technique to Test Memory BIST Algorithms. 109-116 - Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott, Yunan Xiang, Sue Ann Ung:
Fault Modeling and Pattern-Sensitivity Testing for a Multilevel DRAM. 117-122 - Michael Redeker, Bruce F. Cockburn, Duncan G. Elliott:
An Investigation into Crosstalk Noise in DRAM Structures. 123- - Philippe Magarshack:
SoC's Trends and Challenges going to 0.10µm. MTDT 2002
EPROM/EEPROM Design
- Jean-Michel Portal, L. Forli, Hassen Aziza, Didier Née:
An Automated Design Methodology for EEPROM Cell (ADE). 137-142 - Cyrille Dray, Philippe Gendrier:
A Novel Memory Array Based on an Annular Single-Poly EPROM Cell for Use in Standard CMOS Technology. 143-148 - Caroline Papaix, Jean Michel Daga:
A New Single Ended Sense Amplifier for Low Voltage Embedded EEPROM Non Volatile Memories. 149-156
Process Technology and Reliability
- Thierry Devoivre, M. Lunenborg, C. Julien, J.-P. Carrere, P. Ferreira, W. J. Toren, A. VandeGoor, P. Gayet, T. Berger, O. Hinsinger, P. Vannier, Y. Trouiller, Y. Rody, P.-J. Goirand, R. Palla, I. Thomas, F. Guyader, David Roy, B. Borot, Nicolas Planes, Sylvie Naudet, F. Pico, D. Duca, F. Lalanne, D. Heslinga, M. Haond:
Validated 90nm CMOS Technology Platform with Low-k Copper Interconnects for Advanced System-on-Chip (SoC). 157-162 - Mario R. Casu, Philippe Flatresse:
Converting an Embedded Low-Power SRAM from Bulk to PD-SOI. 163-167 - Romain Laffont, J. Razafindramora, Pierre Canet, Rachid Bouchakour, Jean-Michel Mirabel:
Decreasing EEPROM Programming Bias With Negative Voltage, Reliability Impact. 168-176
Advanced Memory Technologies Panel
- Bruce F. Cockburn:
Panel on Advanced Embedded Memory Technologies. 177-178
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