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ORCIDReCoSoC 2014: Montpellier, France
- 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2014, Montpellier, France, May 26-28, 2014. IEEE 2014, ISBN 978-1-4799-5810-8
- Bharath Sudev, Leandro Soares Indrusiak
:
Low overhead predictability enhancement in non-preemptive network-on-chip routers using Priority Forwarded Packet Splitting. 1-8 - Ping-Chun Lee, Ing-Jer Huang:
Reconfigurable Bus Monitor Tool Suite for on-chip SoC for performance and protocol monitoring. 1-6 - Thomas Carle, Manel Djemal, Daniela Genius, François Pêcheux, Dumitru Potop-Butucaru, Robert de Simone, Franck Wajsbürt, Zhen Zhang:
Reconciling performance and predictability on a many-core through off-line mapping. 1-8 - Alfonso Rodríguez, Juan Valverde, Eduardo de la Torre, Teresa Riesgo:
Dynamic management of multikernel multithread accelerators using Dynamic Partial Reconfiguration. 1-7 - Muhammad Amin Qureshi, Husain Parvez:
Design-space exploration between FPGA and ASIF. 1-5 - Chuan Shan, Dimitri Galayko, François Anceau, Eldar Zianbetov:
A reconfigurable distributed architecture for clock generation in large many-core SoC. 1-8 - Mohamed Amine Boussadi, Thierry Tixier, Alexis Landrault, Jean-Pierre Dérutin:
HNCP-II: A 16-core 65nm microprocessor ASIC for image processing algorithms. 1-7 - Fatma Karray, Mohamed Wassim Jmal, Mohamed Abid, Mohammed S. BenSaleh, Abdulfattah Mohammad Obeid:
A review on wireless sensor node architectures. 1-8 - Laurent Gantel, Mohamed El Amine Benkhelifa, François Verdier, Fabrice Lemonnier:
MRAPI resource management layer on reconfigurable systems-on-chip. 1-7 - Maha Kooli, Pascal Benoit, Giorgio Di Natale, Lionel Torres, Volkmar Sieh:
Fault injection tools based on Virtual Machines. 1-6 - Fynn Schwiegelshohn, Michael Hübner:
An application scenario for dynamically reconfigurable FPGAs. 1-8 - Moslem Amiri, Vaclav Prenosil:
General solutions for MTTF and steady-state availability of NMR systems. 1-4 - Kris Heid, Haoyuan Ying, Christian Hochberger, Klaus Hofmann:
LatEst: Latency estimation and high speed evaluation for wormhole switched Networks-on-Chip. 1-7 - Pierre-Emmanuel Gaillardon, Xifan Tang, Giovanni De Micheli:
Novel configurable logic block architecture exploiting controllable-polarity transistors. 1-3 - Christof Osewold, Wolfgang Büter, Alberto García Ortiz:
A coding-based configurable and asymmetrical redundancy scheme for 3-D interconnects. 1-8 - Parham Haririan, Alberto García Ortiz:
Non-intrusive DVFS emulation in gem5 with application to self-aware architectures. 1-7 - Arnaud Vena, Brice Sorli, Alain Foucaran, Yassin Belaizi:
A RFID-enabled sensor platform for pervasive monitoring. 1-4 - Haoyuan Ying, Thomas Hollstein, Klaus Hofmann:
A hardware/software co-design reconfigurable Network-on-Chip FPGA emulation method. 1-8 - Jaime Correa Rodriguez, Kurt Franz Ackermann:
Leveraging partial dynamic reconfiguration on Zynq SoC FPGAs. 1-6 - Yunfeng Ma, M. Norazizi Sham Mohd Sayuti, Leandro Soares Indrusiak:
Inexact End-to-End Response Time Analysis as fitness function in search-based task allocation heuristics for hard real-time network-on-chips. 1-8 - Thomas Schuster, Rolf Meyer, Rainer Buchty, Luca Fossati, Mladen Berekovic:
SoCRocket - A virtual platform for the European Space Agency's SoC development. 1-7 - Fabien Clermidy, O. Turkyimaz, Olivier Billoint, Pierre-Emmanuel Gaillardon:
3D technologies for reconfigurable architectures. 1-2 - Sophiane Senni, Lionel Torres, Gilles Sassatelli, Anastasiia Butko, Bruno Mussard:
Power efficient Thermally Assisted Switching Magnetic memory based memory systems. 1-6 - Loïc Lagadec, Jean-Christophe Le Lann, Théotime Bollengier:
A prototyping platform for virtual reconfigurable units. 1-7 - Sébastien Le Beux, Hui Li, Gabriela Nicolescu, Ian O'Connor:
A reconfigurable optical network on chip for streaming applications. 1-2 - Paul James Fox, A. Theodore Markettos, Simon W. Moore:
Reliably prototyping large SoCs using FPGA clusters. 1-8 - Piotr Dziurzanski, Hashem Ali Ghazzawi, Leandro Soares Indrusiak:
Feedback-based admission control for task allocation. 1-5 - Ali Ahari, Hossein Asadi, Mehdi Baradaran Tahoori:
Emerging Non-Volatile Memory technologies for future low power reconfigurable systems. 1-2 - Gregor Rebel, Francisco J. Estévez, Ioanna Tsekoura, Ingo Schulz, Peter Glösekötter:
Interrupt aware queue implementation for energy efficient multitasking systems based on Cortex-M3 architecture. 1-7 - Mokhtar Bouain, Venkatasubramanian Viswanathan, Rabie Ben Atitallah, Jean-Luc Dekeyser:
Communication-centric design for FMC based I/O system. 1-8 - Abdelkarim Cherkaoui, Lilian Bossuet, Ludwig Seitz, Göran Selander, Ravishankar Borgaonkar:
New paradigms for access control in constrained environments. 1-4 - Guy Wassi, Mohamed El Amine Benkhelifa, Geoff Lawday, François Verdier, Samuel Garcia:
Multi-shape tasks scheduling for online multitasking on FPGAs. 1-7 - Faycal Ait Aouda, Kevin Marquet, Guillaume Salagnac:
Incremental checkpointing of program state to NVRAM for transiently-powered systems. 1-4 - Alexandre Ingles da Silva, Fábio Dacêncio Pereira:
Sram-Based FPGA proposal for dynamic power management on sensor node. 1-7 - Ioanna Tsekoura, Gregor Rebel, Peter Glösekötter, Mladen Berekovic:
An evaluation of energy efficient microcontrollers. 1-5 - Baqar Raza, Husain Parvez, Muhammad Mohiuddin:
Exploring alternate trade-offs of placement quality versus runtime in Simulated Annealing algorithm. 1-5 - Philipp Wehner, Christina Piberger, Diana Göhringer:
Using JSON to manage communication between services in the Internet of Things. 1-4 - Ning Ma, Zhuo Zou, Zhonghai Lu, Li-Rong Zheng, Stefan Blixt:
A hierarchical reconfigurable micro-coded multi-core processor for IoT applications. 1-4
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