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ORCIDSBAC-PAD 2007: Gramado, RS, Brazil
- 19th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2007), 24-27 October 2007, Gramado, RS, Brazil. IEEE Computer Society 2007, ISBN 0-7695-3014-1
Applications I
- Carolina Ribeiro Xavier
, Rafael Sachetto Oliveira, Vinicius da Fonseca Vieira, Rodrigo Weber dos Santos, Wagner Meira Jr.:
Multi-level Parallelism in the Computational Modeling of the Heart. 3-10 - Jairo Panetta, Paulo R. P. de Souza Filho, Carlos A. da Cunha Filho, Fernando M. Roxo da Motta, Silvio Sinedino Pinheiro, Ivan Pedrosa Junior, Andre L. Romanelli Rosa, Luiz Rodolpho Monnerat, Leandro T. Carneiro, Carlos H. B. de Albrecht:
Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor Architectures. 11-18 - Gustavo Poli, João F. Mari, José Hiroki Saito, Alexandre L. M. Levada:
Voice Command Recognition with Dynamic Time Warping (DTW) using Graphics Processing Units (GPU) with Compute Unified Device Architecture (CUDA). 19-25 - Diego Rivera, Dana Schaa, Micha Moffie, David R. Kaeli:
Exploring Novel Parallelization Technologies for 3-D Imaging Applications. 26-33
Microarchitecture
- Emre Özer, Alastair Reid, Stuart Biles:
Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor. 37-44 - Elias Mizan, Tileli Amimeur, Margarida F. Jacome:
Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units. 45-53 - Md. Mafijul Islam:
Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications. 54-61 - Rafael Ubal, Julio Sahuquillo, Salvador Petit, Pedro López:
Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. 62-68
Applications II
- Claudio Schepke, Nicolas Maillard:
Performance Improvement of the Parallel Lattice Boltzmann Method Through Blocked Data Distributions. 71-78 - Walter Santos, Thiago Teixeira, Carla Machado, Wagner Meira Jr., Renato Ferreira, Dorgival Olavo Guedes Neto, Altigran Soares da Silva:
A Scalable Parallel Deduplication Algorithm. 79-86 - Guilherme Galante, Rogério Luís Rizzi, Tiarajú Asmuz Diverio:
A Multigrid-Schwarz Method for the Solution of Hydrodynamics and Heat Transfer Problems in Unstructured Meshes. 87-94
Benchmarking, Performance Measurements and Analysis
- Rod Fatoohi:
Performance Evaluation of the Dual-Core Based SGI Altix 4700. 97-104 - Youfeng Wu, Maurício Breternitz Jr., Victor Ying:
Impacts of Multiprocessor Configurations on Workloads in Bioinformatics. 105-113
Application-Specific Architectures
- Nadia Nedjah, Luiza de Macedo Mourelle:
Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning. 117-124 - Karlo Gusso Lenzi, Osamu Saotome:
Optimized Math Functions for a Fixed-Point DSP Architecture. 125-132
Grid Computing
- Elton N. Mathias, Françoise Baude, Vincent Cavé, Nicolas Maillard:
A Component-Oriented Support for Hierarchical MPI Programming on Multi-Cluster Grid Environments. 135-142 - Alexandre P. C. Silva, Mario A. R. Dantas:
A Selector of Grid Resources based on the Semantic Integration of Multiple Ontologies. 143-150 - Javier Echaiz, Jorge Ardenghi, Guillermo Ricardo Simari:
A Novel Algorithm for Indirect Reputation-Based Grid Resource Management. 151-158
Cache and Memory Architectures
- Rahul Nagpal, Y. N. Srikant:
Register File Energy Optimization for Snooping Based Clustered VLIW Architectures. 161-168 - Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa:
Queue Register File Optimization Algorithm for QueueCore Processor. 169-176 - Abel G. Silva-Filho, Carmelo J. A. Bastos Filho, Ricardo Massa Ferreira Lima, Davi M. A. Falcão, Filipe R. Cordeiro, Marília P. Lima:
An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance. 177-184 - Eduardo Braulio Wanderley Netto, Romain Vaslin, Guy Gogniat, Jean-Philippe Diguet:
A Code Compression Method to Cope with Security Hardware Overheads. 185-192
Interconnection Networks, Routing, and Communication
- Steen Larsen, Parthasarathy Sarangam, Ram Huggahalli:
Architectural Breakdown of End-to-End Latency in a TCP/IP Network. 195-202 - Hyacinthe Nzigou Mamadou, Takeshi Nanri, Kazuaki J. Murakami, Guilherme de Melo Baptista Domingues:
Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms. 203-210 - Seung Eun Lee, Jun Ho Bahn, Nader Bagherzadeh:
Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). 211-218
Tools for Parallel and Distributed Programming
- Yinglong Xia, Viktor K. Prasanna:
Node Level Primitives for Parallel Exact Inference. 221-228 - Bruno Coutinho, Dorgival Olavo Guedes Neto, Wagner Meira Jr., Renato Ferreira:
Fault-tolerance in filter-labeled-stream applications. 229-236 - Francisco Heron de Carvalho Junior, Ricardo Cordeiro Corrêa, Gisele Azevedo Araújo, Jefferson de Carvalho Silva, Rafael Dueire Lins:
High-Level Service Connectors for Component-Based High Performance Computing. 237-244
Load Balancing and Scheduling
- Guilherme P. Pezzi, Márcia C. Cera, Elton N. Mathias, Nicolas Maillard, Philippe Olivier Alexandre Navaux:
On-line Scheduling of MPI-2 Programs with Hierarchical Work Stealing. 247-254 - Lucas S. Casagrande, Rodrigo Fernandes de Mello, Ricardo Bertagna, Jose Augusto Andrade Filho, Francisco José Monaco:
Exigency-based real-time scheduling policy to provide absolute QoS for web services. 255-262 - Roberto Giorgi, Zdravko Popovic, Nikola Puzovic:
DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. 263-270 - Marluce Rodrigues Pereira, Patrícia Kayser Vargas, Maria Clicia Stelling de Castro, Felipe Maia Galvão França, Inês de Castro Dutra:
Automatic Constraint Partitioning to Speed Up CLP Execution. 271-278
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