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ORCIDSBAC-PAD 2008: Campo Grande, MS, Brazil
- Edson Norberto Cácares, Walfredo Cirne, Viktor K. Prasanna:
20th International Symposium on Computer Architecture and High Performance Computing, SBAC-PAD 2008, October 29 - November 1, 2008, Campo Grande, MS, Brazil. IEEE Computer Society 2008, ISBN 978-0-7695-3423-7
Architecture I
- Balaji Vijayn
, Dmitry V. Ponomarev:
Accurate and Low-Overhead Dynamic Detection and Prediction of Program Phases Using Branch Signatures. 3-10 - Jason Loew, Dmitry Ponomarev:
Aggressive Scheduling and Speculation in Multithreaded Architectures: Is it Worth its Salt? 11-18 - Abel G. Silva-Filho, Carmelo J. A. Bastos Filho, Davi M. A. Falcão, Filipe R. Cordeiro, Rodrigo M. C. S. Castro:
An Optimization Mechanism Intended for Two-Level Cache Hierarchy to Improve Energy and Performance Using the NSGAII Algorithm. 19-26
Applications I
- Rodrigo Fernandes de Mello, Luciano José Senger:
On Simulated Annealing for the Scheduling of Parallel Applications. 29-36 - Rodrigo da Rosa Righi, Laércio Lima Pilla, Alexandre Carissimi, Philippe Olivier Alexandre Navaux:
Controlling Processes Reassignment in BSP Applications. 37-44 - Thiago S. M. C. de Farias, Mozart W. S. Almeida, João Marcelo X. N. Teixeira, Veronica Teichrieb, Judith Kelner:
A High Performance Massively Parallel Approach for Real Time Deformable Body Physics Simulation. 45-52
Multicore
- Charles W. Lively, Valerie E. Taylor, Sadaf R. Alam, Jeffrey S. Vetter:
A Methodology for Developing High Fidelity Communication Models for Large-Scale Applications Targeted on Multicore Systems. 55-62 - Jesús Alastruey, Teresa Monreal, Francisco J. Cazorla, Víctor Viñals, Mateo Valero:
Selection of the Register File Size and the Resource Allocation Policy on SMT Processors. 63-70 - Xin Fu, Tao Li, José A. B. Fortes:
ORBIT: Effective Issue Queue Soft-Error Vulnerability Mitigation on Simultaneous Multithreaded Architectures Using Operand Readiness-Based Instruction Dispatch. 71-78
Applications II
- Gustavo Poli, José Hiroki Saito, João F. Mari, Marcelo R. Zorzan:
Processing Neocognitron of Face Recognition on High Performance Environment Based on GPU with CUDA Architecture. 81-88 - Mariana Luderitz Kolberg, Márcio Dorn, Luiz Gustavo Fernandes, Gerd Bohlender:
Parallel Verified Linear System Solver for Uncertain Input Data. 89-96 - Rodrigo N. Calheiros, Mauro Storch, Everton Alexandre, César A. F. De Rose, Marcus Breda:
Applying Virtualization and System Management in a Cluster to Implement an Automated Emulation Testbed for Grid Applications. 97-104
Architecture II
- Robert J. LaDuca, Joseph J. Sharkey, Dmitry V. Ponomarev:
Hiding Communication Delays in Clustered Microarchitectures. 107-114 - Eduardo Tavares, Bruno Silva, Paulo Romero Martins Maciel, Pedro Dallegrave:
Software Synthesis for Hard Real-Time Embedded Systems with Energy Constraints. 115-122 - Maurício Breternitz Jr., Gabriel H. Loh, Bryan Black, Jeff Rupley, Peter G. Sassone, Wesley Attrot, Youfeng Wu:
A Segmented Bloom Filter Algorithm for Efficient Predictors. 123-130
Grid, Cluster, and Operating Systems
- Petar Radojkovic, Vladimir Cakarevic, Javier Verdú, Alejandro Pajuelo, Roberto Gioiosa, Francisco J. Cazorla, Mario Nemirovsky, Mateo Valero:
Measuring Operating System Overhead on CMT Processors. 133-140 - Luis Daniel Benavides Navarro, Rémi Douence, Fabien Hermenier, Jean-Marc Menaud, Mario Südholt:
Aspect-Based Patterns for Grid Programming. 141-148 - Daniel Fireman, George Teodoro, André Cardoso, Renato Ferreira:
A Reconfigurable Run-Time System for Filter-Stream Applications. 149-156
Memory Systems
- James Poe, Chang-Burm Cho, Tao Li:
Using Analytical Models to Efficiently Explore Hardware Transactional Memory and Multi-Core Co-Design. 159-166 - Alessandro Bardine, Manuel Comparetti, Pierfrancesco Foglia, Giacomo Gabrielli, Cosimo Antonio Prete:
Performance Sensitivity of NUCA Caches to On-Chip Network Parameters. 167-174 - Felipe Goldstein, Alexandro Baldassin, Paulo Centoducatte, Rodolfo Azevedo, Leonardo A. G. Garcia:
A Software Transactional Memory System for an Asymmetric Processor Architecture. 175-182 - Leandro A. J. Marzulo, Felipe Maia Galvão França, Vítor Santos Costa:
Transactional WaveCache: Towards Speculative and Out-of-Order DataFlow Execution of Memory Operations. 183-190
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