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ORCID16. VDAT 2012: Shibpur, India
- Hafizur Rahaman, Sanatan Chattopadhyay, Santanu Chattopadhyay:
Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings. Lecture Notes in Computer Science 7373, Springer 2012, ISBN 978-3-642-31493-3
Lower Power 1
- Anu Gupta
, Subhrojyoti Sarkar:
An Efficient High Frequency and Low Power Analog Multiplier in Current Domain. 1-9 - Biswajit Maity, Pradip Mandal:
Design of Push-Pull Dynamic Leaker Circuit for a Low Power Embedded Voltage Regulator. 10-18 - Priyanka Choudhury, Sambhu Nath Pradhan:
Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm. 19-29
Analog VLSI Design I
- Rahul Shrestha, Roy P. Paily:
Design and Implementation of a Linear Feedback Shift Register Interleaver for Turbo Decoding. 30-39 - Gunti Nagendra Babu, Brajesh Kumar Kaushik, Anand Bulusu, Manoj Kumar Majumder:
Low Complexity Encoder for Crosstalk Reduction in RLC Modeled Interconnects. 40-45 - Ashutosh Nandi, Ashok K. Saxena, Sudeb Dasgupta:
Analog Performance Analysis of Dual-k Spacer Based Underlap FinFET. 46-51
Test and Verification I
- R. Jayagowri, K. S. Gurumurthy:
Implementation of Gating Technique with Modified Scan Flip-Flop for Low Power Testing of VLSI Chips. 52-58 - Surajit Kumar Roy, Dona Roy, Chandan Giri, Hafizur Rahaman:
Post-bond Stack Testing for 3D Stacked IC. 59-68 - Soumyadip Bandyopadhyay, Kunal Banerjee, Dipankar Sarkar, Chittaranjan A. Mandal:
Translation Validation for PRES+ Models of Parallel Behaviours via an FSMD Equivalence Checker. 69-78
Design Techniques I
- Prabir Saha, Arindam Banerjee, Anup Dandapat, Partha Bhattacharyya:
Design of High Speed Vedic Multiplier for Decimal Number System. 79-88 - Mamata Dalui, Biplab K. Sikdar:
An Efficient Test Design for CMPs Cache Coherence Realizing MESI Protocol. 89-98 - Debapriya Basu Roy, Debdeep Mukhopadhyay:
An Efficient High Speed Implementation of Flexible Characteristic-2 Multipliers on FPGAs. 99-110
Algorithms and Applications I
- Subrata Das, Parthasarathi Dasgupta, Samar Sen-Sarma:
Arithmetic Algorithms for Ternary Number System. 111-120 - Dushyant Juneja, Sougata Kumar Kar, Procheta Chatterjee, Siddhartha Sen:
SOI MEMS Based Over-Sampling Accelerometer Design with ΔΣ Output. 121-128 - Goutam Rana, Samir Kumar Lahiri, Chirasree Roy Chaudhuri:
Design Optimization of a Wide Band MEMS Resonator for Efficient Energy Harvesting. 129-138
Lower Power II
- Chandrabhan Kushwah, Santosh Kumar Vishvakarma:
Ultra-Low Power Sub-threshold SRAM Cell Design to Improve Read Static Noise Margin. 139-146 - Arun Dobriyal, Rahul Gonnabattula, Pallab Dasgupta, Chittaranjan A. Mandal:
Workload Driven Power Domain Partitioning. 147-155 - Rituparna Dasgupta, Dipankar Saha, Jagannath Samanta, Sayan Chatterjee, Chandan Kumar Sarkar:
Implementation of a New Offset Generator Block for the Low-Voltage, Low-Power Self Biased Threshold Voltage Extractor Circuit. 156-165
Analog VLSI Design II
- Manas Kumar Hati, Tarun Kanti Bhattacharyya:
A High Speed, Low Jitter and Fast Acquisition CMOS Phase Frequency Detector for Charge Pump PLL. 166-171 - Jaynarayan T. Tudu, Deepak Malani, Virendra Singh:
ILP Based Approach for Input Vector Controlled (IVC) Toggle Maximization in Combinational Circuits. 172-179 - Manodipan Sahoo, Bharadwaj Amrutur:
Comparison of OpAmp Based and Comparator Based Switched Capacitor Filter. 180-189
Test and Verification II
- Sanjay Burman, Ayan Palchaudhuri, Rajat Subhra Chakraborty, Debdeep Mukhopadhyay, Pranav Singh:
Effect of Malicious Hardware Logic on Circuit Reliability. 190-197 - P. R. Sruthi, M. Nirmala Devi:
A Modified Scheme for Simultaneous Reduction of Test Data Volume and Testing Power. 198-208 - Kiran Kumar Abburi, Siva Subrahmanya Evani, Sajeev Thomas, Anup Aprem:
Reusable and Scalable Verification Environment for Memory Controllers. 209-216
Design Techniques II
- Atin Mukherjee, Anindya Sundar Dhar:
Design of a Fault-Tolerant Conditional Sum Adder. 217-222 - Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita:
SEU Tolerant Robust Latch Design. 223-232 - Debaprasad Das, Avishek Sinha Roy, Hafizur Rahaman:
Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors. 233-242
Algorithms and Applications II
- Ayantika Chatterjee, Indranil Sengupta:
High-Speed Unified Elliptic Curve Cryptosystem on FPGAs Using Binary Huff Curves. 243-251 - Mahendra Sakare, Mohit Singh, Shalabh Gupta:
A 4 × 20 Gb/s 29-1 PRBS Generator for Testing a High-Speed DAC in 90nm CMOS Technology. 252-257 - Hafizur Rahaman, Jimson Mathew, Abusaleh M. Jabir, Dhiraj K. Pradhan:
VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. 258-269
Emerging Technologies
- Sudhindu Bikash Mandal, Amlan Chakrabarti, Susmita Sur-Kolay:
A Synthesis Method for Quaternary Quantum Logic Circuits. 270-280 - Lafifa Jamal, Md. Masbaul Alam Polash, M. A. Mottalib, Hafiz Md. Hasan Babu:
On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits. 281-288 - Debaprasad Das, Hafizur Rahaman:
Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects. 289-299
Algorithms and Applications III
- Santanu Halder, Debotosh Bhattacharjee, Mita Nasipuri, Dipak Kumar Basu:
A Fast FPGA Based Architecture for Sobel Edge Detection. 300-306 - Arun Kumarappan, P. V. Ramakrishna:
Speech Processor Design for Cochlear Implants. 307-316 - Rekha Govindaraj, Indranil Sengupta, Santanu Chattopadhyay:
An Efficient Technique for Longest Prefix Matching in Network Routers. 317-326
NoC and Physical Design
- Bapi Kar, Susmita Sur-Kolay, Sridhar H. Rangarajan, Chittaranjan A. Mandal:
A Faster Hierarchical Balanced Bipartitioner for VLSI Floorplans Using Monotone Staircase Cuts. 327-336 - Sanga Chaki, Chandan Giri:
Test Data Compression for NoC Based SoCs Using Binary Arithmetic Operations. 337-342 - Bibhas Ghoshal, Subhadip Kundu, Indranil Sengupta, Santanu Chattopadhyay:
Particle Swarm Optimization Based BIST Design for Memory Cores in Mesh Based Network-on-Chip. 343-349
Poster Presentation
- Bibhash Sen, Manojit Dutta, Divyam Saran, Biplab K. Sikdar:
An Efficient Multiplexer in Quantum-dot Cellular Automata. 350-351 - Vikram Singh Saun, Suman Chatterjee, Anand Arunachalam:
Integrated Placement and Optimization Flow for Structured and Regular Logic. 352-353 - K. Kalyani, S. Rajaram:
A Novel Symbol Estimation Algorithm for LTE Standard. 354-356 - Naushad Alam, Bulusu Anand, Sudeb Dasgupta:
Impact of Dummy Poly on the Process-Induced Mechanical Stress Enhanced Circuit Performance. 357-359 - Biswajit Patra, Sanatan Chattopadhyay, Amlan Chakrabarti:
A Novel Approach to Voltage-Drop Aware Placement in Large SoCs in Advanced Technology Nodes. 360-363 - P. Saravanan, P. Chandrasekar, Livya Chandran, Nikilla Sriram, P. Kalpana:
Design and Implementation of Efficient Vedic Multiplier Using Reversible Logic. 364-366 - Sauvagya Ranjan Sahoo, Kamala Kanta Mahapatra:
Design of Combinational and Sequential Circuits Using Novel Feedthrough Logic. 367-369 - Arpan Mondal, Santosh Ghosh, Abhijit Das, Dipanwita Roy Chowdhury:
Efficient FPGA Implementation of Montgomery Multiplier Using DSP Blocks. 370-372 - Naveen Kaushik, Brajesh Kumar Kaushik, Davinder Kaur, Manoj Kumar Majumder:
Independent Gate SRAM Based on Asymmetric Gate to Source/Drain Overlap-Underlap Device FinFET. 373-374 - Sudip Ghosh, Somsubhra Talapatra, Debasish Mondal, Navonil Chatterjee, Hafizur Rahaman, Santi P. Maity:
VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark. 375-376 - Soumyajit Poddar, Prasun Ghosal, Priyajit Mukherjee, Suman Samui, Hafizur Rahaman:
A Photonic Network on Chip with CDMA Links. 377-378 - Partha Sarathi Gupta, Sayan Kanungo, Hafizur Rahaman, Parthasarathi Dasgupta:
Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor. 379-380 - Prasun Ghosal, Tuhin Subhra Das:
Routing in NoC on Diametrical 2D Mesh Architecture. 381-382
Invited Talk
- Rolf Drechsler, Robert Wille:
Reversible Circuits: Recent Accomplishments and Future Challenges for an Emerging Technology - (Invited Paper). 383-392 - Farhana Rashid, Vishwani D. Agrawal:
Power Problems in VLSI Circuit Testing. 393-405
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