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ORCID20. VDAT 2016: Guwahati, India
- 20th International Symposium on VLSI Design and Test, VDAT 2016, Guwahati, India, May 24-27, 2016. IEEE 2016, ISBN 978-1-5090-1422-4
- Nidhi Batra, Anil Kumar Gundu, Mohammad S. Hashmi
, G. S. Visweswaran, Anuj Grover:
An effective test methodology enabling detection of weak bits in SRAMs: Case study in 28nm FDSOI. 1-6 - Antara Ganguly, Sangeeta Goyal, Sneha Bhatia, Anuj Grover:
New stable loadless 6T dual-port SRAM cell design. 1-6 - Procheta Chatterjee, Sougata Kar, Siddhartha Sen:
Design methodology of closed loop MEMS capacitive accelerometers based on ΣΔ modulation technique. 1-6 - Ashish Sharma, Ruby Ansar, Manoj Singh Gaur, Lava Bhargava, Vijay Laxmi:
Reducing FIFO buffer power using architectural alternatives at RTL. 1-2 - Kiran Garje, Shravan Kumar, Amitesh Tripathi, Gillela Maruthi, Madhava Kumar:
A high CMRR, high resolution bio-ASIC for ECG signals. 1-2 - Mohd. Tasleem Khan, Shaik Rafi Ahamed, Amitabh Chatterjee:
Efficient implementation of concurrent lookahead decision feedback equalizer using offset binary coding. 1-6 - Shipra Batra, Pankhuri Singh, Shashwat Kaushik, Mohammad S. Hashmi:
Frequency domain analysis of on-chip power distribution network. 1-6 - Sapna Khandelwal, Jyoti Meena, Lokesh Garg, Dharmendar Boolchandani:
Variability and reliability aware surrogate model for sensing delay analysis of SRAM sense amplifier. 1-6 - Jaynarayan T. Tudu, Satyadev Ahlawat:
Guided shifting of test pattern to minimize test time in serial scan. 1-6 - Pavan Kumar Nadimpalli, Subir K. Roy:
An efficient FPGA-based function profiler for embedded system applications. 1-6 - Manan Mewada, Mazad Zaveri:
A low-power high-speed hybrid full adder. 1-2 - Mahesh Zanwar, Subhajit Sen:
Programmable output switched capacitor step-down DC-DC converter with high accuracy using Sigma-Delta Feedback Control Loop. 1-6 - Jaynarayan T. Tudu:
JSCAN: A joint-scan DFT architecture to minimize test time, pattern volume, and power. 1-6 - Nils Heitmann, Philipp H. Kindt, Samarjit Chakraborty:
EG0N: Portable in-situ energy measurement for low-power sensor devices. 1-6 - Chetan D. Parikh, Gopal Agarwal:
New technique to improve transient response of LDO regulators without an off-chip capacitor. 1-5 - Rohini Gulve, Nihar Hage, Jaynarayan T. Tudu:
On determination of instantaneous peak and cycle peak switching using ILP. 1-6 - Krishna Kumar Movva, Syed Azeemuddin:
A novel low power 6-bit FLASH ADC using charge steering amplifier for RF applications. 1-2 - Soumik Sarkar, Gaurav Saini, Mahima Arrawatia, Maryam Shojaei Baghini:
Optimal design flow of CMOS doubler-based rectifiers. 1-6 - Ankit Gaurav, Sandeep Singh Gill, Navneet Kaur, Munish Rattan:
Density gradient quantum corrections based performance optimization of triangular TG bulk FinFETs using ANN and GA. 1-5 - Sachin Khandagale, Santanu Sarkar:
An 8-bit 500 MSPS segmented current steering DAC using Chinese abacus technique. 1-2 - Moumita Chakraborty, Amlan Chakrabarti, Partha Mitra, Debasri Saha, Krishnendu Guha:
Pre-layout module wise decap allocation for noise suppression and accurate delay estimation of SoC. 1-6 - Amit Salaskar, Nitin Chandrachoodan:
FFT/IFFT implementation using Vivado™ HLS. 1-2 - A. Purushothaman:
Analysis of regeneration time constant of dynamic latch using Adomian Decomposition method. 1-6 - Bharat Garg, V. N. S. K. Chaitanya Goteti, G. K. Sharma:
A low-cost energy efficient image scaling processor for multimedia applications. 1-6 - Rahul Shrestha, Vinay Swargam, Mahesh S. Murty:
Cognitive-radio wireless-sensor based on energy detection with improved accuracy: Performance and hardware perspectives. 1-6 - Subrata Chattopadhyay, Shiv Bhushan Tripathi, Mrinal Goswami, Bibhash Sen:
Design of fault tolerant majority voter for TMR circuit in QCA. 1-2 - Debasis Pal, Abir Pramanik, Parthasarathi Dasgupta, Debesh Kumar Das:
Double Patterning Lithography (DPL)-compliant layout construction (DCLC) with area-stitch usage tradeoff. 1-6 - Bharat Garg, Sameer Yadav, G. K. Sharma:
An area and performance aware ECG encoder design for wireless healthcare services. 1-6 - Sukarn Agarwal, Hemangee K. Kapoor:
Towards a dynamic associativity enabled write prediction based hybrid cache. 1-6 - Bikromadittya Mondal, Kushal Dey, Susanta Chakraborty:
An efficient reversible cryptographic circuit design. 1-6 - Procheta Chatterjee, Sougata Kar, Siddhartha Sen:
Design, integration and performance analysis of ΣΔ ADC for capacitive sensor interfacing. 1-2 - M. Mohamed Asan Basiri, Sandeep K. Shukla:
Hardware optimizations for crypto implementations (Invited paper). 1-6 - Aravindhan Alagarsamy, Lakshminaraynan Gopalakrishnan:
SAT: A new application mapping method for power optimization in 2D - NoC. 1-6 - Pulkit Sharma, Anil Kumar Gundu, Mohammad S. Hashmi:
Modeling and yield estimation of SRAM sub-system for different capacities subjected to parametric variations. 1-6 - Navonil Chatterjee, Priyajit Mukherjee, Santanu Chattopadhyay:
A strategy for fault tolerant reconfigurable Network-on-Chip design. 1-2 - Saurav Kumar Ghosh, Akash Mondal, Souradeep Dutta, Aritra Hazra, Soumyajit Dey:
Synthesis of scheduler automata guaranteeing stability and reliability of embedded control systems. 1-6 - Rama Prasad Acharya, Abir J. Mondal, Alak Majumder:
A method to design a comparator for sampled data processing applications. 1-6 - Pawan Sehgal, Aditi Sharma, Akhilesh C. Mishra, Rangarajan Ramanujam, Sujay Deb:
An effective and efficient algorithm to analyse and debug clock propagation issues. 1-6 - Satyadev Ahlawat, Jaynarayan T. Tudu:
On minimization of test power through modified scan flip-flop. 1-6 - Anindita Chakraborty, Rakesh Das, Chandan Bandyopadhyay, Hafizur Rahaman:
BDD based synthesis technique for design of high-speed memristor based circuits. 1-6 - Avishek Sinha Roy, N. Prasad, Anindya Sundar Dhar:
Approximate conditional carry adder for error tolerant applications. 1-6 - Prateek Pendyala, Vijaya Sankara Rao Pasupureddi:
Backward compatible MIL-STD-1553B analog transceiver upgrade for 100-Mb/s data rate. 1-5 - Ayan Palchaudhuri, Anindya Sundar Dhar:
High performance bit-sliced pipelined comparator tree for FPGAs. 1-6 - K. Nithin Sankar, Abhishek Srivastava, Baibhab Chatterjee, K. K. Rakesh, Maryam Shojaei Baghini:
FSK demodulator and FPGA based BER measurement system for low IF receivers. 1-2 - Paromita Bhattacharjee, Abir J. Mondal, Alak Majumder:
A constraint driven technique for MOS amplifier design. 1-6 - D. Celia, Nitin Chandrachoodan:
Guided multilevel approximation of less significant bits for power reduction. 1-6 - Pulkit Sharma, R. Anusha, K. Bharath, Jasmine Kaur Gulati, Preet K. Walia, Sumit Jagdish Darak:
Quantification of figures of merit of 7T and 8T SRAM cells in subthreshold region and their comparison with the conventional 6T SRAM cell. 1-2 - Bidesh Chakraborty, Mamata Dalui, Biplab K. Sikdar:
Design of coherence verification unit for CMPs realizing dragon protocol. 1-6 - Pranab Roy, Sudeshna Chakraborty, Hafizur Rahaman:
Synthesis aware sample preparation techniques using random sample sets in DMFB. 1-6 - G. Muralidhar, Dinesh Ganesan, Binsu J. Kailath:
Switched-capacitor circuit simulator in Q-V domain including nonidealities. 1-6 - Ambuj Mishra, Subir K. Roy:
Formal verification of switched capacitor DC to DC power converter using circuit simulation traces. 1-2 - Om. Prakash, Satish Maheshwaram, Mohit Sharma, Anand Bulusu, A. K. Saxena, S. K. Manhas:
A unified Verilog-A compact model for lateral Si nanowire (NW) FET incorporating parasitics for circuit simulation. 1-6 - Rajib Lochan Jana, Shashank Kuchibhotla, Soumyajit Dey, Pallab Dasgupta, Rakesh Kumar:
Planning based guided reconstruction of corner cases in architectural validation. 1-6 - Disha Arora, Anil Kumar Gundu, Mohammad S. Hashmi:
A high speed low voltage latch type sense amplifier for non-volatile memory. 1-5 - Binod Kumar, Boda Nehru, Brajesh Pandey, Jaynarayan T. Tudu:
Skip-scan: A methodology for test time reduction. 1-6 - C. B. Kushwah, Devesh Dwivedi, N. Sathisha, Krishnan S. Rengarajan:
A robust 8T FinFET SRAM cell with improved stability for low voltage applications. 1-6 - Sri Harsha Gade, Praveen Kumar, Sujay Deb:
A Pre-RTL floorplanner tool for automated CMP design space exploration with thermal awareness. 1-6 - Waikhom Mona Chanu, Vikash Prasad, Debaprasad Das:
Performance analysis of temperature dependent GNR interconnect. 1-5 - Priyanka Kimtee, Devarshi Mrinal Das, Maryam Shojaei Baghini:
A mismatch insensitive reconfigurable discrete time biosignal conditioning circuit in 180 nm MM CMOS technology. 1-2 - Surajit Das, Shirshendu Das, Hemangee K. Kapoor:
Tag only storage for capacity optimised last level cache in chip multiprocessors. 1-6 - Sandip Bhattacharya, Debaprasad Das, Hafizur Rahaman:
Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnects. 1-2 - Bharti Navlani, Pankaj U. Joshi, Raghavendra B. Deshmukh:
Data dependent spurious power reduction for fixed width multiplier. 1-2 - Abhishek Srivastava, Nithin Sankar, K. K. Rakesh, Baibhab Chatterjee, Devarshi Das, Maryam Shojaei Baghini:
Design and measurement techniques for a low noise amplifier in a receiver chain for MedRadio spectrum of 401-406 MHz frequency band. 1-6 - Chiradeep Mukherjee, Soudip Sinha Roy, Saradindu Panda, Bansibadan Maji:
T-Gate: Concept of partial polarization in Quantum Dot Cellular Automata. 1-6 - Sasha Garg, Sumit Jagdish Darak:
FPGA implementation of high speed reconfigurable filter bank for multi-standard wireless communication receivers. 1-5 - Suraj Hebbar, Vinay Kumar, M. S. Bhat, Navakanta Bhat:
Smart handheld platform for electrochemical bio sensors. 1-2 - Ramakrishna Vaikuntapu, Lava Bhargava, Vineet Sahula:
Golden IC free methodology for hardware Trojan detection using symmetric path delays. 1-2 - Rahul Ratnakumar, Satyasai Jagannath Nanda:
A FSM based approach for efficient implementation of K-means algorithm. 1-6 - Raghav Kishore, Hemanta Kumar Mondal, Sujay Deb:
Energy-efficient reconfigurable framework for evaluating hybrid NoCs. 1-2
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