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ORCIDVLSIC 2014: Honolulu, HI, USA
- Symposium on VLSI Circuits, VLSIC 2014, Digest of Technical Papers, Honolulu, HI, USA, June 10-13, 2014. IEEE 2014, ISBN 978-1-4799-3327-3
- E-Hung Chen
, Masum Hossain, Brian S. Leibowitz, Reza Navid, Jihong Ren, Chuen-Huei Adam Chou, Barry Daly, Marko Aleksic, Bruce Su, Simon Li, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 40-Gb/s serial link transceiver in 28-nm CMOS technology. 1-2 - Bendik Kleveland, Jeong Choi, Jeff Kumala, Pascal Adam, Patrick Chen, Rajesh Chopra, Antonio Cruz, Ronald B. David, Ashish Dixit, Sinan Doluca, Mark Hendrickson, Ben Lee, Ming Liu, Michael John Miller, Mike Morrison, Byeong Cheol Na, Jay Patel, Dipak K. Sikdar, Michael Sporer, Clement Szeto, Anju Tsao, Jianguang Wang, Daniel Yau, Wesley Yu:
Early detection and repair of VRT and aging DRAM bits by margined in-field BIST. 1-2 - Yi-Lin Tsai, Jian-You Chen, Bang-Cyuan Wang, Tzu-Yu Yeh, Tsung-Hsien Lin:
A 400MHz 10Mbps D-BPSK receiver with a reference-less dynamic phase-to-amplitude demodulation technique. 1-2 - Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori:
A 2.7GHz to 7GHz fractional-N LCPLL utilizing multimetal layer SoC technology in 28nm CMOS. 1-2 - Chen Sun, Michael Georgas, Jason Orcutt, Benjamin Moss, Yu-Hsin Chen, Jeffrey Shainline, Mark T. Wade, Karan Mehta, Kareem Nammari, Erman Timurdogan, Daniel L. Miller, Ofer Tehar-Zahav, Zvi Sternberg, Jonathan C. Leu, Johanna Chong, Reha Bafrali, Gurtej Sandhu, Michael Watts, Roy Meade, Milos A. Popovic, Rajeev J. Ram, Vladimir Stojanovic:
A monolithically-integrated chip-to-chip optical link in bulk CMOS. 1-2 - Wei Lin, Shao-Wei Yen, Yu-Cheng Hsu, Yu-Hsiang Lin, Li-Chun Liang, Tien-Ching Wang, Pei-Yu Shih, Kuo-Hsin Lai, Kuo-Yi Cheng, Chun-Yen Chang:
A low power and ultra high reliability LDPC error correction engine with Digital Signal Processing for embedded NAND Flash Controller in 40nm COMS. 1-2 - Takayuki Abe, Takashi Morie, Kazutoshi Satou, Daisuke Nomasaki, Shigeki Nakamura, Yoichiro Horiuchi, Koji Imamura:
An ultra-low-power 2-step wake-up receiver for IEEE 802.15.4g wireless sensor networks. 1-2 - Adesh Garg, Ullas Singh, Nick Huang, Wayne Wong, Bin Liu, Zhi Chao Huang, Afshin Momtaz, Jun Cao:
A quad-channel 112-128 Gb/s coherent transmitter in 40 nm CMOS. 1-2 - Yen-Po Chen, David T. Blaauw, Dennis Sylvester:
A 266nW multi-chopper amplifier with 1.38 noise efficiency factor for neural signal recording. 1-2 - Kailiang Chen, Hae-Seung Lee, Charles G. Sodini:
A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging. 1-2 - Jung Kuk Kim, Phil Knag, Thomas Chen, Zhengya Zhang:
A 6.67mW sparse coding ASIC enabling on-chip learning and inference. 1-2 - Mudit Bhargava, Y. K. Chong, Vincent Schuppe, Bikas Maiti, Martin Kinkade, Hsin-Yu Chen, Andy W. Chen, Sanjay Mangal, Jacek Wiatrowski, Gerald Gouya, Abhishek Baradia, Sriram Thyagarajan, Gus Yeung:
Low VMIN 20nm embedded SRAM with multi-voltage wordline control based read and write assist techniques. 1-2 - Meisam Honarvar Nazari, Muhammad Mujeeb-U.-Rahman, Axel Scherer:
An implantable continuous glucose monitoring microsystem in 0.18µm CMOS. 1-2 - Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi, Ken Takeuchi:
Application-aware solid-state drives (SSDs) with adaptive coding. 1-2 - Daniel J. Yeager, William Biederman, Nathan Narevsky, Jaclyn Leverett, Ryan Neely, Jose M. Carmena, Elad Alon, Jan M. Rabaey:
A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation. 1-2 - Li-Yue Huang, Meng-Fan Chang, Ching-Hao Chuang, Chia-Chen Kuo, Chien-Fu Chen, Geng-Hau Yang, Hsiang-Jen Tsai, Tien-Fu Chen, Shyh-Shyuan Sheu, Keng-Li Su, Frederick T. Chen, Tzu-Kun Ku, Ming-Jinn Tsai, Ming-Jer Kao:
ReRAM-based 4T2R nonvolatile TCAM with 7x NVM-stress reduction, and 4x improvement in speed-wordlength-capacity for normally-off instant-on filter-based search engines used in big-data processing. 1-2 - Maryam Tabesh, Mustafa Rangwala, Ali M. Niknejad, Amin Arbabian:
A power-harvesting pad-less mm-sized 24/60GHz passive radio with on-chip antennas. 1-2 - Hariprasath Venkatram, Taehwan Oh, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon:
A 48 fJ/CS, 74 dB SNDR, 87 dB SFDR, 85 dB THD, 30 MS/s pipelined ADC using hybrid dynamic amplifier. 1-2 - Chan-Hsiang Weng, Tzu-An Wei, Erkan Alpman, Chang-Tsung Fu, Yi-Ting Tseng, Tsung-Hsien Lin:
An 8.5MHz 67.2dB SNDR CTDSM with ELD compensation embedded twin-T SAB and circular TDC-based quantizer in 90nm CMOS. 1-2 - Takushi Hashida, Yasumoto Tomita, Yuuki Ogata, Kosuke Suzuki, Shigeto Suzuki, Takanori Nakao, Yuji Terao, Satofumi Honda, Sota Sakabayashi, Ryuichi Nishiyama, Akihiko Konmoto, Yoshitomo Ozeki, Hiroyuki Adachi, Hisakatsu Yamaguchi, Yoichi Koyanagi, Hirotaka Tamura:
A 36 Gbps 16.9 mW/Gbps transceiver in 20-nm CMOS with 1-tap DFE and quarter-rate clock distribution. 1-2 - Walker J. Turner, Rizwan Bashirullah:
A 4.7T/11.1T NMR compliant wirelessly programmable implant for bio-artificial pancreas in vivo monitoring. 1-2 - Gyouho Kim, Yoonmyung Lee, Zhiyoong Foo, Pat Pannuto, Ye-Sheng Kuo, Benjamin P. Kempke, Mohammad Hassan Ghaed, Suyoung Bang, Inhee Lee, Yejoong Kim, Seokhyeon Jeong, Prabal Dutta, Dennis Sylvester, David T. Blaauw:
A millimeter-scale wireless imaging system with continuous motion detection and energy harvesting. 1-2 - Stacy Ho, Chi-Lun Lo, Zhiyu Ru, Jialin Zhao:
A 23mW, 73dB dynamic range, 80MHz BW continuous-time delta-sigma modulator in 20nm CMOS. 1-2 - Feng-Wei Kuo, Huan-Neng Ron Chen, Kyle Yen, Hsien-Yuan Liao, Chewnpu Jou, Fu-Lung Hsueh, Masoud Babaie, Robert Bogdan Staszewski:
A 12mW all-digital PLL based on class-F DCO for 4G phones in 28nm CMOS. 1-2 - Reum Oh, Byunghyun Lee, Sang-Woong Shin, Wonil Bae, Hundai Choi, Indal Song, Yun-Sang Lee, Jung-Hwan Choi, Chi-Wook Kim, Seong-Jin Jang, Joo-Sun Choi:
Design technologies for a 1.2V 2.4Gb/s/pin high capacity DDR4 SDRAM with TSVs. 1-2 - Noriyuki Miura, Daisuke Fujimoto, Daichi Tanaka, Yu-ichi Hayashi, Naofumi Homma, Takafumi Aoki, Makoto Nagata:
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor. 1-2 - Aatmesh Shrivastava, Yogesh K. Ramadass, Sudhanshu Khanna, Steven Bartling, Benton H. Calhoun:
A 1.2µW SIMO energy harvesting and power management unit with constant peak inductor current control achieving 83-92% efficiency across wide input and output voltages. 1-2 - Yildiz Sinangil, Sabrina M. Neuman, Mahmut E. Sinangil, Nathan Ickes, George Bezerra, Eric Lau, Jason E. Miller, Henry Hoffmann, Srinivas Devadas, Anantha P. Chandrakasan:
A self-aware processor SoC using energy monitors integrated into power converters for self-adaptation. 1-2 - Edward Doller, Ameen Akel, Jeffrey Wang, Ken Curewitz, Sean Eilert:
DataCenter 2020: Near-memory acceleration for data-oriented applications. 1-4 - Ahmed Elkholy, Tejasvi Anand, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 3.7mW 3MHz bandwidth 4.5GHz digital fractional-N PLL with -106dBc/Hz In-band noise using time amplifier based TDC. 1-2 - Michael A. Inerfield, Abhishek Kamath, Feng Su, Jason Hu, Xinyu Yu, Victor Fong, Omar Alnaggar, Fang Lin, Tom Kwan:
An 11.5-ENOB 100-MS/s 8mW dual-reference SAR ADC in 28nm CMOS. 1-2 - Youn Sung Park, Yaoyu Tao, Shuanghong Sun, Zhengya Zhang:
A 4.68Gb/s belief propagation polar decoder with bit-splitting register file. 1-2 - Alan Bannon, Christopher Peter Hurrell, Derek Hummerston, Colin Lyden:
An 18 b 5 MS/s SAR ADC with 100.2 dB dynamic range. 1-2 - Charles Chih-Min Liu, Chin-Hao Chang, Honyih Tu, Calvin Yi-Ping Chao, Fu-Lung Hsueh, Szu-Ying Chen, Vincent Hsu, Jen-Cheng Liu, Dun-Nien Yaung, Shou-Gwo Wuu:
A peripheral switchable 3D stacked CMOS image sensor. 1-2 - Brian Young, Karthik Reddy, Sachin Rao, Amr Elshazly, Tejasvi Anand, Pavan Kumar Hanumolu:
A 75dB DR 50MHz BW 3rd order CT-ΔΣ modulator using VCO-based integrators. 1-2 - Joseph Sankman, Minkyu Song, Dongsheng Ma:
A 40-MHz 85.8%-peak-efficiency switching-converter-only dual-phase envelope modulator for 2-W 10-MHz LTE power amplifier. 1-2 - Mrunmay Talegaonkar, Tejasvi Anand, Ahmed Elkholy, Amr Elshazly, Romesh Kumar Nandwana, Saurabh Saxena, Brian Young, Woo-Seok Choi, Pavan Kumar Hanumolu:
A 4.4-5.4GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter. 1-2 - Abhishek Bandyopadhyay, Robert Adams, Khiem Nguyen, Paul Baginski, David Lamb, Thomas Tansley:
A 97.3 dB SNR, 600 kHz BW, 31mW multibit continuous time ΔΣ ADC. 1-2 - Kiseok Song, Unsoo Ha, Seongwook Park, Hoi-Jun Yoo:
An impedance and multi-wavelength near-infrared spectroscopy IC for non-invasive blood glucose estimation. 1-2 - Amr Elshazly, Ajay Balankutty, Yan-Yu Huang, Kai Yu, Frank O'Mahony:
A 2GHz-to-7.5GHz quadrature clock-generator using digital delay locked loops for multi-standard I/Os in 14nm CMOS. 1-2 - Neale A. W. Dutton, Luca Parmesan, Andrew J. Holmes, Lindsay A. Grant, Robert K. Henderson:
320×240 oversampled digital single photon counting image sensor. 1-2 - Wei-Hsin Tseng, Pao-Cheng Chiu:
A 960MS/s DAC with 80dB SFDR in 20nm CMOS for multi-mode baseband wireless transmitter. 1-2 - Fang-Li Yuan, Tsung-Han Yu, Dejan Markovic:
A 500MHz blind classification processor for cognitive radios in 40nm CMOS. 1-2 - Changhyuk Lee, Ben Johnson, Alyosha C. Molnar:
An on-chip 72×60 angle-sensitive single photon image sensor array for lens-less time-resolved 3-D fluorescence lifetime imaging. 1-2 - Xing Li, Chi-Ying Tsui, Wing-Hung Ki:
A 13.56MHz wireless power transfer system with reconfigurable resonant regulating rectifier and wireless power control for implantable medical devices. 1-2 - Shiyu Su, Tu-I Tsai, Praveen Kumar Sharma, Mike Shuo-Wei Chen:
A 12-bit hybrid DAC with 8GS/s unrolled pipeline delta-sigma modulator achieving >75dB SFDR over 500MHz in 65nm CMOS. 1-2 - Quan Pan, Zhengxiong Hou, Yipeng Wang, Yan Lu, Wing-Hung Ki, Keh-Chung Wang, C. Patrick Yue:
A 48-mW 18-Gb/s fully integrated CMOS optical receiver with photodetector and adaptive equalizer. 1-2 - Harsh Mehta, Gautham Krishnamurthy, Michael A. Inerfield, Fang Lin, Tom Kwan:
A 3nV/vHz programmable gain/BW mixed-signal 4th order Chebyshev high-pass filter for ADSL/VDSL analog front end in 28nm CMOS. 1-2 - Inhee Lee, Yoonmyung Lee, Dennis Sylvester, David T. Blaauw:
Low power battery supervisory circuit with adaptive battery health monitor. 1-2 - Chi-Cheng Ju, Tsu-Ming Liu, Huaide Wang, Yung-Chang Chang, Chih-Ming Wang, Chang-Lin Hsieh, Brian Liu, Hue-Min Lin, Chia-Yun Cheng, Chun-Chia Chen, Min-Hao Chiu, Sheng-Jen Wang, Ping Chao, Meng-Jye Hu, Ryan Yeh, Ted Chuang, Hsiu-Yi Lin, Chung-Hung Tsai:
A 4K×2K@60fps multi-standard TV SoC processor with integrated HDMI/MHL receiver. 1-2 - Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura:
On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs. 1-2 - Seongjong Kim, Mingoo Seok:
R-processor: 0.4V resilient processor with a voltage-scalable and low-overhead in-situ error detection and correction technique in 65nm CMOS. 1-2 - Takayuki Tsukizawa, Atsushi Yoshimoto, Hiroshi Komori, Kenji Miyanaga, Ryo Kitamura, Yohei Morishita, Masatake Irie, Yoichi Nagaso, Takeaki Watanabe, Koji Takinami, Noriaki Saito:
A PVT-variation tolerant fully integrated 60 GHz transceiver for IEEE 802.11ad. 1-2 - Hajir Hedayati, Vladimir Aparin, Kamran Entesari:
A +22dBm IIP3 and 3.5dB NF wideband receiver with RF and baseband blocker filtering techniques. 1-2 - Shunta Iguchi, Hiroshi Fuketa, Takayasu Sakurai, Makoto Takamiya:
92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator. 1-2 - Liechao Huang, Warren Rieutort-Louis, Alexandra Gualdino, Laura Teagno, Yingzhe Hu, Jaoa Mouro, Josue Sanz-Robinson, James C. Sturm, Sigurd Wagner, Virginia Chu, João Pedro Conde, Naveen Verma:
An ASIC for readout of post-processed thin-film MEMS resonators by employing capacitive interfacing and active parasitic cancellation. 1-2 - Romesh Kumar Nandwana, Tejasvi Anand, Saurabh Saxena, Seong Joong Kim, Mrunmay Talegaonkar, Ahmed Elkholy, Woo-Seok Choi, Amr Elshazly, Pavan Kumar Hanumolu:
A 4.25GHz-4.75GHz calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolator with 13.2dB phase noise improvement. 1-2 - Masum Hossain, E-Hung Chen, Reza Navid, Brian S. Leibowitz, Chuen-Huei Adam Chou, Simon Li, Myeong-Jae Park, Jihong Ren, Barry Daly, Bruce Su, Makarand Shirasgaonkar, Fred Heaton, Jared Zerbe, John C. Eble:
A 4×40 Gb/s quad-lane CDR with shared frequency tracking and data dependent jitter filtering. 1-2 - Qadeer Ahmad Khan, Seong Joong Kim, Mrunmay Talegaonkar, Amr Elshazly, Arun Rao, Nathanael Griesert, Greg Winter, William McIntyre, Pavan Kumar Hanumolu:
A 10-25MHz, 600mA buck converter using time-based PID compensator with 2µA/MHz quiescent current, 94% peak efficiency, and 1MHz BW. 1-2 - Shinji Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Toshiaki Sano, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Hirotoshi Sato:
A 512-kb 1-GHz 28-nm partially write-assisted dual-port SRAM with self-adjustable negative bias bitline. 1-2 - Wei-Chung Chen, Yung-Sheng Huang, Meng-Wei Chien, Ying-Wei Chou, Hsin-Chieh Chen, Yi-Ping Su, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee:
±3% voltage variation and 95% efficiency 28nm constant on-time controlled step-down switching regulator directly supplying to Wi-Fi systems. 1-2 - J. Takeya, Mayumi Uno:
Technology development for printed LSIs based on organic semiconductors. 1-4 - Vivek De, Hideyuki Kabuo:
Foreword: Welcome to the 2014 Symposium on VLSI Circuits. 1-2 - Yuan Zhou, Benwei Xu, Yun Chiu:
A 12b 160MS/s synchronous two-step SAR ADC achieving 20.7fJ/step FoM with opportunistic digital background calibration. 1-2 - Yu-Lun Chen, Chiro Kao, Pen-Jui Peng, Jri Lee:
A 94GHz duobinary keying wireless transceiver in 65nm CMOS. 1-2 - Xiwei Huang, Fei Wang, Jing Guo, Mei Yan, Hao Yu, Kiat Seng Yeo:
A 64×64 1200fps CMOS ion-image sensor with suppressed fixed-pattern-noise for accurate high-throughput DNA sequencing. 1-2 - Sy-Chyuan Hwu, Behzad Razavi:
A receiver architecture for intra-band carrier aggregation. 1-2 - Harish Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, George E. Matthew, Sheldon Weng, Bharani Thiruvengadam, Wayne Proefrock, Krishnan Ravichandran, Vivek De:
A 500 MHz, 68% efficient, fully on-die digitally controlled buck Voltage Regulator on 22nm Tri-Gate CMOS. 1-2 - Kiduk Kim, Sanghyub Kang, Yoon-Kyung Choi, Kyung-Hoon Lee, Choong-Hoon Lee, Jin-chul Lee, Michael Choi, Kyungjun Ko, Joonwoo Jung, Namgu Park, Ho-Jin Park, Gyoocheol Hwang:
A fully-differential capacitive touch controller with input common-mode feedback for symmetric display noise cancellation. 1-2 - Fang-Li Yuan, Dejan Markovic:
A 13.1GOPS/mW 16-core processor for software-defined radios in 40nm CMOS. 1-2 - Sohmyung Ha, Chul Kim, Jongkil Park, Siddharth Joshi, Gert Cauwenberghs:
Energy-recycling integrated 6.78-Mbps data 6.3-mW power telemetry over a single 13.56-MHz inductive link. 1-2 - Michael Georgas, Benjamin Moss, Chen Sun, Jeffrey Shainline, Jason Orcutt, Mark T. Wade, Yu-Hsin Chen, Kareem Nammari, Jonathan C. Leu, Aravind Srinivasan, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic:
A monolithically-integrated optical transmitter and receiver in a zero-change 45nm SOI process. 1-2 - Dong-Uk Lee, Kyung Whan Kim, Kwan-Weon Kim, Kang Seol Lee, Sang Jin Byeon, Jin-Hee Cho, Han Ho Jin, Sang Kyun Nam, Jaejin Lee, Jun Hyun Chun, Sung-Joo Hong:
An exact measurement and repair circuit of TSV connections for 128GB/s high-bandwidth memory(HBM) stacked DRAM. 1-2 - Takayuki Shibasaki, Win Chaivipas, Yanfei Chen, Yoshiyasu Doi, Takayuki Hamada, Hideki Takauchi, Toshihiko Mori, Yoichi Koyanagi, Hirotaka Tamura:
A 56-Gb/s receiver front-end with a CTLE and 1-tap DFE in 20-nm CMOS. 1-2 - Tim Morrison, Jason Silver, Brian Otis:
A single-chip encrypted wireless 12-lead ECG smart shirt for continuous health monitoring. 1-2 - Sechang Oh, Wanyeong Jung, Kaiyuan Yang, David T. Blaauw, Dennis Sylvester:
15.4b incremental sigma-delta capacitance-to-digital converter with zoom-in 9b asynchronous SAR. 1-2 - Erik Olieman, Anne-Johan Annema, Bram Nauta:
A 110mW, 0.04mm2, 11GS/s 9-bit interleaved DAC in 28nm FDSOI with >50dB SFDR across Nyquist. 1-2 - David Bol, Guerric de Streel, François Botman, Angelo Kuti Lusala, Numa Couniot:
A 65-nm 0.5-V 17-pJ/frame.pixel DPS CMOS image sensor for ultra-low-power SoCs achieving 40-dB dynamic range. 1-2 - Sung-Jin Kim, Taeik Kim, Hojin Park:
A 0.63ps, 12b, synchronous cyclic TDC using a time adder for on-chip jitter measurement of a SoC in 28nm CMOS technology. 1-2 - Chang-Hung Tsai, Tung-Yu Wu, Shu-Yu Hsu, Chia-Ching Chu, Fang-Ju Ku, Ying-Siou Laio, Chih-Lung Chen, Wing Hung Wong, Hsie-Chia Chang, Chen-Yi Lee:
A 7.11mJ/Gb/query data-driven machine learning processor (D2MLP) for big data analysis and applications. 1-2 - Yan-Jiun Chen, Chih-Cheng Hsieh:
A 0.4V 2.02fJ/conversion-step 10-bit hybrid SAR ADC with time-domain quantizer in 90nm CMOS. 1-2 - Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro:
7-bit 0.8-1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique. 1-2 - Bob Verbruggen, Kazuaki Deguchi, Badr Malki, Jan Craninckx:
A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS. 1-2 - Chunyang Zhai, Jeffrey Fredenburg, John Bell, Michael P. Flynn:
An N-path filter enhanced low phase noise ring VCO. 1-2 - Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. 1-2 - Mesut Meterelliyoz, Fuad H. Al-amoody, Umut Arslan, Fatih Hamzaoglu, Luke Hood, Manoj B. Lal, Jeffrey L. Miller, Anand Ramasundar, Dan Soltman, Ifar Wan, Yih Wang, Kevin Zhang:
2nd generation embedded DRAM with 4X lower self refresh power in 22nm Tri-Gate CMOS technology. 1-2 - Abdul Raziz Junaidi, Yasuhiro Take, Tadahiro Kuroda:
A 352Gb/s inductive-coupling DRAM/SoC interface using overlapping coils with phase division multiplexing and ultra-thin fan-out wafer level package. 1-2 - Jun-Chau Chien, Mekhail Anwar, Erh-Chia Yeh, Luke P. Lee, Ali M. Niknejad:
A 6.5/11/17.5/30-GHz high throughput interferometer-based reactance sensors using injection-locked oscillators and ping-pong nested chopping. 1-2 - Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Masanori Tachibana, Fukashi Morishita:
A 3.7M-pixel 1300-fps CMOS image sensor with 5.0G-pixel/s high-speed readout circuit. 1-2 - Tzu-Chi Huang, Ming-Jhe Du, Kuei-Liang Lin, Shao Siang Ng, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Tsung-Yen Tsai, Chen-Chih Huang, Chao-Cheng Lee, Jui-Lung Chen, Hung-Wei Chen:
A direct AC-DC and DC-DC cross-source energy harvesting circuit with analog iterating-based MPPT technique with 72.5% conversion efficiency and 94.6% tracking efficiency. 1-2 - Jaw-Juinn Horng, Szu-Lin Liu, Amit Kundu, Chin-Ho Chang, Chung-Hui Chen, Herman Chiang, Yung-Chow Peng:
A 0.7V resistive sensor with temperature/voltage detection function in 16nm FinFET technologies. 1-2 - Kyuho Lee, Gyeonghoon Kim, Junyoung Park, Hoi-Jun Yoo:
A Vocabulary Forest-based object matching processor with 2.07M-vec/s throughput and 13.3nJ/vector energy in full-HD resolution. 1-2 - Atsuo Isobe, Hikaru Tamura, Kiyoshi Kato, Takuro Ohmaru, Wataru Uesugi, Takahiko Ishizu, Tatsuya Onuki, Kazuaki Ohshima, Takanori Matsuzaki, Atsushi Hirose, Yasutaka Suzuki, Naoaki Tsutsui, Tomoaki Atsumi, Yutaka Shionoiri, Gensuke Goto, Jun Koyama, Masahiro Fujita, Shunpei Yamazaki:
A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor. 1-2 - Ronghua Ni, Kartikeya Mayaram, Terri S. Fiez:
A 915MHz, 6Mb/s, 80pJ/b BFSK receiver with -76dBm sensitivity for high data rate wireless sensor networks. 1-2 - Hiroki Noguchi, Kazutaka Ikegami, Naoharu Shimomura, Tetsufumi Tanamoto, Junichi Ito, Shinobu Fujita:
Highly reliable and low-power nonvolatile cache memory with advanced perpendicular STT-MRAM for high-performance CPU. 1-2 - Jun Yin, Howard C. Luong:
A 0.37-to-46.5GHz frequency synthesizer for software-defined radios in 65nm CMOS. 1-2 - Hao Li, Shuai Chen, Liqiong Yang, Rui Bai, Weiwu Hu, Freeman Y. Zhong, Samuel Palermo, Patrick Yin Chiang:
A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS. 1-2 - Yuji Satoh, Hiroyuki Kobayashi, Takeshi Miyaba, Shouhei Kousai:
A 2.9mW, +/- 85ppm accuracy reference clock generator based on RC oscillator with on-chip temperature calibration. 1-2 - Chin-Yu Lin, Tai-Cheng Lee:
A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique. 1-2
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