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ORCIDVLSI Technology and Circuits 2024: Honolulu, HI, USA
- IEEE Symposium on VLSI Technology and Circuits 2024, Honolulu, HI, USA, June 16-20, 2024. IEEE 2024, ISBN 979-8-3503-6146-9
- Min Zhou, Hong Zhou, Mengwei Si, Guangjie Gao, Xiaojin Chen, Xiaoxiao Zhu, Kui Dang, Peijun Ma, Xiaohua Ma, Xuefeng Zheng, Zhihong Liu, Jincheng Zhang, Yuhao Zhang, Yue Hao:
71 GHz-fmax β-Ga2O3-on-SiC RF Power MOSFETs with Record Pout=3.1 W/mm and PAE=50.8% at 2 GHz, Pout= 2.3 W/mm at 4 GHz, and Low Microwave Noise Figure. 1-2 - Gerui Zheng, Enze Zhang, Rami Khazaka, Kaizhen Han, Haiwen Xu, Yuxuan Wang, Hyunsoo Yang, Xiao Gong:
First Demonstration of Superconducting Nb Contact on Heavily-Doped Group IV Semiconductor. 1-2 - Jee-Eun Yang, Younjin Jang, Narae Han, Ha-Jun Sung, Jung-kyun Kim, Youngkwan Cha, Kwang-Hee Lee, Kyooho Jung, Moonil Jung, Wonsok Lee, Min Hee Cho, Sangwook Kim:
A-IGZO FETs with High Current and Remarkable Stability for Vertical Channel Transistor(VCT) / 3D DRAM Applications. 1-2 - H. Y. Cheng, Z. L. Liu, A. Majumdar, Alexander Grun, A. Ray, J. Su, Malte J. Rasch, Fabio Carta, Lynne M. Gignac, C. Lavoie
, C. W. Cheng, M. Bright Sky, H. L. Lung:
State-Independent Low Resistance Drift SiSbTe Phase Change Memory for Analog In-Memory Computing Applications. 1-2 - Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini:
Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. 1-2 - Sena Kato, Shu Date, Tao Ruoxin, Yasuto Narukiyo, Hiroki Hayashi, Keito Yuasa, Michihiro Ide, Takashi Tomura, Kenichi Okada, Atsushi Shirane:
A 28GHz 5G NR Wirelessly Powered Relay Transceiver Using Rectifier-Type 4th-Order Sub-Harmonic Mixer. 1-2 - Roberto Rangel, Xiaonong Sun, Ayandev Barman, Rahul Gulve, Savo Bajic, Jingmin Wang, Harry Wang, David B. Lindell, Kiriakos N. Kutulakos, Roman Genov:
23, 000-Exposures/s 360fps-Readout Software-Defined Image Sensor with Motion-Adaptive Spatially Varying Imaging Speed. 1-2 - Ping-Sheng Wu, Yu-Cheng Lin, Chia-Hsiang Yang:
A 99.2TOPS/W Transformer Learning Processor with Approximated Attention Score Gradient Computation and Ternary Vector-Based Speculation. 1-2 - Qiankai Cao, Juin Chuen Oh, Jie Gu:
A Mixed-signal 3D Footstep Planning SoC for Motion Control of Humanoid Robots with Embedded Zero-Moment-Point based Gait Scheduler and Neural Inverse Kinematics. 1-2 - Z. Lin, Z. Zhang, C. Niu, H. Dou, K. Xu, M. Islam, J.-Y. Lin, C. Sung, M. Hong, Daewon Ha, H. Wang, M. A. Alam, P. D. Ye:
Highly Robust All-Oxide Transistors with Ultrathin In2O3 as Channel and Thick In2O3 as Metal Gate Towards Vertical Logic and Memory. 1-2 - Geonhui Han, Youngdong Kim, Jaeseon Kim, Dongmin Kim, Yoori Seo, Chuljun Lee, Jinmyung Choi, Jinwoo Lee, Dongho Ahn, Sechung Oh, Donghwa Lee, Hyunsang Hwang:
Highly Scalable Vertical Bypass RRAM (VB-RRAM) for 3D V -NAND Memory. 1-2 - Yu-Chen Kuo, Hong-Teng Wu, Guan-Ye Chen, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li:
A 12V-to-1V 100A Inverted Pyramid Trans-Inductor Voltage Regulator Converter with 93.6% High Efficiency and Fast Transient Response. 1-2 - Kshitiz Tyagi, Behzad Razavi:
A 56-Gb/s 17-mW NRZ Receiver in 0.018 mm2. 1-2 - Ji-Hoon Suh, Haidam Choi, Yoontae Jung, Sohmyung Ha, Minkyu Je:
A 5.7kfps Fast Neural Electrical Impedance Tomography IC Based on Incremental Zoom Structure with Baseline Cancellation for Peripheral Nerve Monitoring Systems. 1-2 - Dong-Myung Choi, Yikui Dong, Roan Nicholson, Frank Liu, Wenyan Jia, Vadim Levin, Mike He, Sameer Pradhan, Jieqiong Du, Michael De Vita, Amanda Tran, Reza Navid, Sitaraman Iyer, Rui Song:
A 4.6pJ/b 64Gb/s Transceiver Enabling PCIe 6.0 and CXL 3.0 in Intel 3 CMOS Technology. 1-2 - Ichiro Somada, Akihito Hirai, Keigo Nakatani, Akinori Taira, Kazuaki Ishioka, Takuma Nishimura, Koji Yamanaka:
Terahertz Sensing with CMOS-RFIC - Feasibility Verification for Short-Range Imaging using 300GHz MIMO Radar -. 1-2 - Hiroaki Arimura, Hans Mertens, Jacopo Franco, L. Lukose, W. Maqsood, S. Brus, Thomas Chiarella, A. Impagnatiello, S. Homkar, V. K. Mootheri, C. Yin, G. Alessio Verni, M. Givens, L. Petersen Barbosa Lima, S. Biesemans, N. Horiguchi:
Vt Fine-Tuning in Multi-Vt Gate-All-Around Nanosheet nFETs Using Rare-Earth Oxide-Based Dipole-First Gate Stack Compatible with CFET Integration. 1-2 - Xiaolin Yang, Joan Aymerich, Philippe Coppejans, Wen-Yang Hsu, Chutham Sawigun, Jose Cisneros-Fernández, Andrea Lodi, Maribel Caceres Rivera, Bernardo Tacca, Matt McDonald, Hasan Mahmud-UI, Barundeb Dutta, Jan Putzeys, Carolina Mora Lopez:
A Highly-Integrated 1536-Channel Quad-Shank Monolithic Neural Probe in 55nm CMOS for Full-Band Raw-Signal Recording. 1-2 - Kiseok Lee, Hongjun Lee, Hyungeun Choi, Jeongsu Kim, Kyunghwan Kim, Moonyoung Jeong, Soohyun Bae, Hyebin Kim, Jiyun Lee, Minsoo Kim, Keunnam Kim, Huijung Kim, Sungmin Park, Taejin Park, Jin-Woo Han, Jeonghoon Oh, Yong Kwan Kim, Sungsoo Yim, Bongsoo Kim, Jemin Park, Jaihyuk Song:
Cell to Core-Periphery Overlap (C2O) Based on BCAT for Next Generation DRAM. 1-2 - Sanghoon Myung, Donggwan Shin, Kyeyeop Kim, Yunji Choi, Gijae Kang, Songyi Han, Jaehoon Jeong, Daesin Kim:
A New Industry Standard Compact Model Integrating TCAD Into SPICE. 1-2 - Tim Keller, Rosario M. Incandela, Xi Chen, Hesam Ghiasi, Mohsen Khodaee, Sina Arjmandpour, Jiawei Liao, H. Long, Tobias Götschi, Jonas Widmer, Taekwang Jang:
A 0.29pJ/Step Fully Discrete-Time Charge Domain Bridge-to-Digital Converter for Force Sensing in Spinal Implants Using RC Bridge. 1-2 - Nuriel N. M. Rozsa, Zhao Chen, Taehoon Kim, Peng Guo, Yannick Hopf, Jason D. Voorneveld, Djalma Simões dos Santos, Emile Noothout, Zu-Yao Chang, Chao Chen, Vincent A. Henneken, Nico de Jong, Hendrik J. Vos, Johan G. Bosch, Martin D. Verweij, Michiel A. P. Pertijs:
A 2000-Volumes/s 3D Ultrasound Imaging Chip with Monolithically-Integrated 11.7×23.4mm2 2048-Element CMUT Array and Arbitrary-Wave TX Beamformer. 1-2 - Matteo Dalla Longa, Francesco Conzatti, Omar Ismail, John G. Kauffman, Maurits Ortmanns:
A 470μW, 102.6dB-DR, 20kHz BW Calibration-Free ΔΣ Modulator with SFDR in Excess of 110dBc using an Intrinsically Linear 13-Level DAC. 1-2 - Nereo Markulic, Johan Nguyen, Jorge Luis Lagos-Benites, Ewout Martens, Jan Craninckx:
A 10GS/s Hierarchical Time-Interleaved ADC for RF-Sampling Applications. 1-2 - Rohan Doshi, Massimo Giordano, Justin Olah, Zhidong Cao, Moon Hyung Jang, Luke R. Upton, Athanasios Ramkaj, Boris Murmann:
Medusa: A 0.83/4.6μJ/Frame 86/91.6%-CIFAR-10 TinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS. 1-2 - Animesh Gupta, Japesh Vohra, Massimo Alioto:
CogniVision: End-to-End SoC for Always-on Smart Vision with mW Power in 40nm. 1-2 - Alan Smith, Gabriel H. Loh, John J. Wuu, Samuel Naffziger, Tyrone Huang, Hugh McIntyre, Ramon Mangaser, Wonjun Jung, Raja Swaminathan:
AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. 1-2 - Seunghwan Lee, Jeongjin Cho, Shinyoung Choi, Sung Yoon Min, Eunjung Lee, Minji Jung, Kyoungmok Son, Hyunchaul Jeong, Heetak Han, Sachoun Park, Sanghyuck Moon, Seungki Jung, Junseok Yang, Taesub Jung, Howoo Park, Bumsuk Kim, Kyungho Lee, Jesuk Lee:
A Temporal Noise Reduction via 40% Enhanced Conversion Gain in Dual-Pixel CMOS Image Sensor with Full-Depth Deep-Trench Isolation and Locally Lowered-Stack Technology. 1-2 - Qiaochu Zhang, Shiyu Su, Baishakhi Rani Biswas, Sandeep Gupta, Mike Shuo-Wei Chen:
Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. 1-2 - Yi Zhang, Minzhe Tang, Jian Pang, Zheng Li, Dongfan Xu, Dingxin Xu, Yuncheng Zhang, Kazuaki Kunihiro, Hiroyuki Sakai, Atsushi Shirane, Kenichi Okada:
A 28GHz 4-Stream Time-Division MIMO Phased-Array Receiver Utilizing Nyquist-Rate Fast Beam Switching for 5G and Beyond. 1-2 - Jorge Lagos, Pratap Tumkur Renukaswamy, Nereo Markulic, Ewout Martens, Jan Craninckx:
A Single-Channel, 1-GS/s, 10.91-ENOB, 81-dB SFDR, 9.2-fJ/conv.-step, Ringamp-Based Pipelined ADC with Background Calibration in 16nm CMOS. 1-2 - Xuchu Mu, Yang Jiang, Rui Paulo Martins, Pui-In Mak:
A Fully Integrated 48-V GaN Driver Using Parallel-Multistep-Series Reconfigurable Switched-Capacitor Bank Achieving 7.7nC/mm2 On-Chip Bootstrap Driving Density. 1-2 - Tsung-Yu Chen, Kris Chuang, Wensen Hung, Tsung-Shu Lin, Yen-Ming Chen:
Package - System Thermal Modeling and New Material. 1-2 - Po-Hsun Chu, Cheng-Tse Tsai, Yu-Siang Chou, Nitish Kumar, Shu-Ping Lin, Yu-Te Liao:
A Pulsed Electrochemistry Readout IC with Slew-rate Booting Technique and Phase-domain ΔΣ ADC for Si-Nanowire Electrical Double-layer Capacitance Measurement. 1-2 - W.-Y. Woon, J.-H. Jhang, K.-K. Hu, C.-C. Shih, J.-F. Hsu, J.-P. Lin, Y. Wu, Anna Kasperovich, Mohamadali Malakoutian, R. Soman, J. Kim, H.-K. Wei, M. Nomura, S. Chowdhury, Szuya Sandy Liao:
Integration and Characterization of High Thermal Conductivity Materials for Heat Dissipation in Stacked Devices. 1-2 - Chao Chen, Zhu Yuan, Peng Cao, Jiawei Xu, Zhiliang Hong:
A 71.5-dB SNDR 475-MS/s Ringamp-Based Pipelined SAR ADC with On-Chip Bit-Weight Calibration. 1-2 - Erik Jens Loscalzo, Martin Cochet, Joseph Zuckerman, Samira Zalias, Michael Lekas, Stephen Cahill, Tianyu Jia, Karthik Swaminathan, Maico Cassel dos Santos, Davide Giri, Hesam Sadeghi, Joseph Meyer, Noah Sturcken, David Brooks, Gu-Yeon Wei, Luca P. Carloni, Pradip Bose, Kenneth L. Shepard:
A 400-ns-Settling- Time Hybrid Dynamic Voltage Frequency Scaling Architecture and Its Application in a 22-Core Network-on-Chip SoC in 12-nm FinFET Technology. 1-2 - DongSeok Cho, Byungchoul Park, Hyun-Seung Choi, Myung-Jae Lee, Youngcheol Chae:
A 30fps 64×64 CMOS Flash LiDAR Sensor with Push-Pull Analog Counter Achieving 0.1% Depth Uncertainty at 70m Detection Range. 1-2 - Qi Jiang, Koustav Jana, Kasidit Toprasertpong, Shuhan Liu, H.-S. Philip Wong:
Positive Bias Stress Measurement Guideline and Band Analysis for Evaluating Instability of Oxide Semiconductor Transistors. 1-2 - Jinpyo Han, Houk Lee, Junhee Cho, Heesung Lee, Seong-Jin Kim, Jung-Hoon Chun, Jaehyuk Choi:
A Digital Dynamic Vision Sensor with SPAD Pixels and Multi-Event Generation for Motion/Vibration-Adaptive Detection. 1-2 - K. S. Choi, S. H. Kim, J. W. Seo, H. S. Kang, S. W. Chu, S. W. Bae, J. H. Kwon, G. S. Kim, Y. T. Park, J. H. Kwak, D. I. Song, S. M. Park, Y. T. Kim, K. C. Jang, J. S. Cho, H. S. Lee, B. H. Lee, J. W. Park, J. H. Lee, H. H. Kwon, D. S. You, C. S. Hyun, J. J. Lee, S. C. Lee, I. D. Kim, J. H. Myung, H. S. Won, J. H. Chun, K. H. Kim, J. H. Kang, S. B. Kim, K. H. Lee, S. O. Chung, S. S. Kim, I. S. Jin, B. K. Lee, C. W. Kim, J. Park, S. Y. Cha:
A Three Dimensional DRAM (3D DRAM) Technology for the Next Decades. 1-2 - Hyun-chul Hwang, Min-su Kim, Daeseong Lee, Yong-geol Kim, Byung-su Kim, Kun-hyuk Kang:
An Area-Efficient True Single-Phase Clocked and Conditional Capture Flip-Flop for Ultra-Low-Power Operations in 7nm Fin-FET Process. 1-2 - A. Sayed, Michel Vasilevski, M. T. Abdelmomen, Shadi Turk, Ahmed A. Ghoniem, C. Perez, C. Voillequin, Haralampos-G. Stratigopoulos, Marie-Minerve Louërat, E. Wantiez, Hassan Aboushady:
A 10.8GS/s, 84MHz-BW RF Bandpass ΣΔ ADC with a 89dB-SFDR and a 62dB-SNDR for LTE/5G Receivers. 1-2 - Sally Amin, Harish Krishnamurthy, Huong T. Do, Claudio Alvarez, Mike Hill, Kaladhar Radhakrishnan, Vivek De, Sheldon Weng, Krishnan Ravichandran, Jim Tschanz, Wilfred Gomes, Jonathan Douglas:
A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control. 1-2 - Ashish Pal, Sefa Dag, Pratik B. Vyas, Gregory Costrini, Vinod Reddy, Veeraraghavan Basker, Allen Yeong, Benjamin Colombeau, Bala Haran, Subi Kengeri, El Mehdi Bazizi:
Material, Process and System Level Analysis for Parasitic Reduction of Next Generation Logic Technology in Conjunction with Backside Power Delivery. 1-2 - Ye-Dam Kim, Jae-Hyun Chung, Kent Edrian Lozada, Chang-Un Park, Kun-Woo Park, Kwan-Hoon Song, Young-Hun Moon, Min-Jae Seo, Seung-Tak Ryu:
A 100kHz-BW 99dB-DR Continuous-Time Tracking-Zoom Incremental ADC with Residue-Gain Switching and Digital NC-FF. 1-2 - Pao-Shu Liu, Yu-Hsiang Huang, Chih-Cheng Hsieh:
A Low-OSR 5th-Order Noise Shaping SAR ADC Using EF-EF-CIFF Structure with PVT-Robust Differential V-T-V Converter. 1-2 - Yang Wang, Xiaolong Yang, Yubin Qin, Zhiren Zhao, Ruiqi Guo, Zhiheng Yue, Huiming Han, Shaojun Wei, Yang Hu, Shouyi Yin:
A 22nm 54.94TFLOPS/W Transformer Fine-Tuning Processor with Exponent-Stationary Re-Computing, Aggressive Linear Fitting, and Logarithmic Domain Multiplicating. 1-2 - Sungjin Park, Kwanghyun Shin, Dongkwon Lee, Minyoung Kang, Sunwoo Lee, Youngmin Park, Mingoo Seok, Dongsuk Jeon:
A 5.6µW 10-Keyword End-to-End Keyword Spotting System Using Passive-Averaging SAR ADC and Sign-Exponent-Only Layer Fusion with 92.7% Accuracy. 1-2 - Kyunghwan Min, Jahoon Jin, Soo-Min Lee, Sodam Ju, Jisu Yook, Jihoon Lee, Yunji Hong, Sungsik Park, Sang-Ho Kim, Jongwoo Lee, Hyungjong Ko:
A 20Gb/s/pin Single-Ended PAM-4 Transceiver with Pre/Post-Channel Switching Jitter Compensation and DQS-Driven Biasing for Low-Power Memory Interfaces. 1-2 - Hyungjoo Cho, Dongyoon Lee, Hoyong Sung, Heewon Choee, Ji-Hoon Suh, Injun Choi, Donghee Cho, Sohmyung Ha, Minkyu Je:
An Intra-Body-Power-Transfer System Energized by an Electromagnetic Energy Harvester for Powering Wearable Sensor Nodes. 1-2 - Maryam Rofougaran, Reza Rofougaran:
Wireless Connectivity in a Future Hyperconnected World. 1-4 - Ling Wang, Longjie Zhong, Zhangming Zhu:
A 1.5 V 132 dBSPL AOP Digital Readout Circuit for MEMS Microphone Using Self-Adaption Loop. 1-2 - Yusuke Shuto, Jun Okuno, Tsubasa Yonai, Ryo Ono, Peter Reinig, Maximilian Lederer, Konrad Seidel, Ruben Alcala, Thomas Mikolajick, Uwe Schroeder, Taku Umebayashi, Kentaro Akiyama:
HZO-based Nonvolatile SRAM Array with 100% Bit Recall Yield and Sufficient Retention Time at 85°C. 1-2 - Pratik B. Vyas, Ludovico Megalini, Ashish Pal, Joshua Holt, Archana Kumar, Stephen Weeks, Charisse Zhao, Lucien Date, Hansel Lo, Michel Khoury, Safdar Muhammad, Fabian Piallat, Ricky Fang, William Charles, Pratim Palit, Jinghe Yang, Qintao Zhang, Jang Seok Oh, Bryan Turner, Samphy Hong, Aswin Prathap Pitchiya, Benjamin Briggs, Jiao Yang, Dae Yang, Fengshou Wang, Joseph Lee, Gopal Prabhu, Dustin Ho, Carlos Caballero, Durga Chaturvedula, Zheng Yuan, Yi Zheng, David A. Britz, Stephen Krause, Raghav Sreenivasan, Michael Chudzik, Subi Kengeri, Siddarth A. Krishnan, El Mehdi Bazizi:
Novel Material, Process and Device Innovations for Next Generation Silicon Carbide (SiC) Trench MOSFET Technology. 1-2 - Adelson Chua, Aviral Pandey, Ryan Kaveh, Sina Faraji Alamouti, Justin Doong, Rikky Muller:
SPIRIT: A Seizure Prediction SoC with a 17.2nJ/cls Unsupervised Online-Learning Classifier and Zoom Analog Frontends. 1-2 - Junsang Park, Jinwoo Park, Jaemin Hong, Sun-Jae Park, Dongsuk Lee, Sungno Lee, Hyochul Shin, Kyung-Hoon Lee, Byeongwoo Koo, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 10GS/s Time-Interleaved SAR ADC with Even/Odd Channel-Correlated Absolute Error-Based Over-Nyquist Timing-Skew Calibration in 5nm FinFET. 1-2 - T. Takagi, T. Ninomiya, M. Niwa, S. Obara, T. Momose, Y. Shimogaki, M. Nomura, H. Fujioka, M. Mori, T. Kuroda:
High Thermal Conductivity AlN Films for Advanced 3D Chiplets. 1-2 - Seongkyung Kim, Junkyo Jeong, Eunyu Choi, Jinyoung Kim, Hyewon Shim, Shin-Young Chung, Paul Jung:
Hot-Carrier-Degradation Characterization for Accurate End-of-Life Prediction with 3nm GAA Logic Technology Featuring Multi-Bridge-Channel FET. 1-2 - T. V. Dinh, S.-W. Tam, A. J. Scholten, L. Tondelli, R. M. T. Pijper, S. H. Kondapalli, J. Xie, A. Wong, I. To, R. Asanovski, L. Selmi:
Assessment of the Transient Self-Heating Effect and its Impact on the Performance of Watt-Level RF Power Amplifier in a FinFET Technology. 1-2 - Zhong Tang, Haining Wang, Xiaopeng Yu, Kofi A. A. Makinwa, Nianxiong Nick Tan:
A 0.8V Capacitively-Biased BJT-Based Temperature Sensor with an Inaccuracy of ±0.4°C (3σ) from -40°C to 125°C in 22nm CMOS. 1-2 - Wei Lu, Jie Zhang, Yi-Hui Wei, Hsu-Ming Hsiao, Sih-Han Li, Chao-Kai Hsu, Chih-Cheng Hsiao, Feng-Hsiang Lo, Shyh-Shyuan Sheu, Chin-Hung Wang, Wei-Chung Lo, Shih-Chieh Chang, Hung-Ming Chen, Kuan-Neng Chen, Po-Tsang Huang:
Scalable Embedded Multi-Die Active Bridge (S-EMAB) Chips with Integrated LDOs for Low-Cost Programmable 2.5D/3.5D Packaging Technology. 1-2 - Naomi Yoshida, Ilanit Fisher, He Ren, Chi-Chou Lin, Chenfei Shen, Yongjing Lin, Yi Xu, Michael S.-. C. Chen, Mehul Naik:
Replacement Metal Gate Process Extendible Beyond 2-nm Node with Superior Gate Conductivity. 1-2 - Chi-Yu Chen, Tz-Wun Wang, Po-Jui Chiu, Sheng-Hsi Hung, Chang-Lin Go, Xiao-Quan Wu, Yu-Ting Huang, Ke-Horng Chen, Kuo-Lin Zeng, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
A Monolithic GaN-based Gate Driver for LLC-SRC with Three-Phase Startup Clamping Achieving 23.2μA IQ and 98.6% Peak Efficiency. 1-2 - Daphnée Bosch, Abygaël Viey, Tadeu Mota Frutuoso, P. Lheritier, C. Licitra, Nada Zerhouni, A. Albouy, Laurent Brunet, A. Magalhaes-Lucas, L. M. B. da Silva, H. Boutry, M. Husien Fahmy Taha Abdelrahman, F. Cristiano, R. Gassilloud, M. Ribotta, G. Romano, William Vandendaele, V. Benevent, M. Opprecht, S. Kerdilès, F. Milesi, F. Mazen, Benoit Sklénard, C. Euvrard-Colnat, Johannes Sturm, A. Lambert, C. Candebage, L. Laraignou, F. Boulard, A. Sarrazin, M. De Souza, Christoforos G. Theodorou, Xavier Garros, Perrine Batude:
Breakthrough Processes for Si CMOS Devices with BEOL Compatibility for 3D Sequential Integrated more than Moore Analog Applications. 1-2 - M. G. Gottwald, Guohan Hu, Philip Louis Trouilloud, L. Rehm, C. Safranski, G. Kim, S. L. Brown, J. Bruley, C. P. D'Emic, O. Gunawan, H. Jung, C. Lavoie, J. Lee, J. Liang, M. Robbins, J. Z. Sun, P. Hashemi, Daniel Christopher Worledge:
First Demonstration of High Retention Energy Barriers and 2 ns Switching, Using Magnetic Ordered-Alloy-Based STT MRAM Devices. 1-2 - Nathaniel Safron, Tzu-Ang Chao, Shengman Li, Shreyam Natani, San Lin Liew, Carlo Gilardi, Hsin-Yuan Chiu, Sheng-Kai Su, Andrew Bechdolt, Gilad Zeevi, Zichen Zhang, Matthias Passlack, Vincent D.-H. Hou, Harshil Kashyap, Chao-Hsin Chien, Prabhakar Bandaru, Andrew C. Kummel, H.-S. Philip Wong, Subhasish Mitra, Gregory Pitner, Iuliana P. Radu:
High Performance Transistor of Aligned Carbon Nanotubes in a Nanosheet Structure. 1-2 - Chen Kong Teh, Te Bi, Shuichi Ito, Takashi Kurihara:
730-790mA/mm2 48V-to-1V Integrated Hybrid DC-DC Converters Based on a Star-Delta Switching Network with 5x/8x Duty Expansion. 1-2 - Sander Derksen, Maël Demarets, Gerard Villar Pique, Fabio Sebastiano:
A 0.9V Rail-to-Rail Ultra-Low-Power Fully Integrated Clock Generator Achieving 23fJ/Cycle in 28nm CMOS. 1-2 - Guan Feng, Yu Li, Hao Jiang, Xiaodong Wang, Yize Sun, Yingfen Wei, Qi Liu, Ming Liu:
Comprehensive Analysis of Duty-Cycle Induced Degradations in HfxZr1-xO2-Based Ferroelectric Capacitors: Behavior, Modeling, and Optimization. 1-2 - Gyuseong Kang, Hyunjin Shin, Sanggyeong Won, Dohui Kim, Kyuseong Kim, Soohoh Seol, Sunkyu Lee, Hangil Lee, Yeonho Jung, Jaechul Shim, Kiseok Suh, Sohee Hwang, Daehyun Jang, Sangyeop Baeck, Sei Seung Yoon:
A 14nm 128Mb eMRAM Implemented with 17.88Mb/mm2 at 0.60V for Auto-G1 Applications. 1-2 - Hyungdeok Lee, Guhyun Kim, Dayeon Yun, Ilkon Kim, Yongkee Kwon, Euicheol Lim:
Cost-Effective LLM Accelerator Using Processing in Memory Technology. 1-2 - Ruichen Wan, Wei Deng, Qixiu Wu, Haikun Jia, W. Rui, Angxiao Yan, Haowen Cai, Sanming Hu, Zhihua Wang, Baoyong Chi:
A 132-to-163 GHz 4TX/4RX Distributed MIMO FMCW Radar Transceiver with Real-Time Reference-Clock Synchronization Enabling Cooperative Coherent Multistatic Imaging System. 1-2 - Sicheng Han, Yun Wang, Yunhao Li, Wen Zuo, Wei Li, Yue Lin, Hongtao Xu:
A 140-Gbps 1-to-21-GHz Ultra-Wideband LNA Achieving 1.95-to-3-dB NF Using Gm-Assisted-Feedback Noise Suppression Technique in 40nm Bulk CMOS. 1-2 - S.-C. Chang, C. Neumann, B. Granados Alpizar, S. Atanasov, J. Peck, N. Kabir, Y.-C. Liao, S. Shivaraman, Wriddhi Chakraborty, N. Haratipour, I-Cheng Tung, V. Nikitin, G. Allen, T. Hoff, A. Oni, T. Tronic, A. Roy, H. Li, F. Hamzaoglu, M. Metz, I. Young, J. Kavalieros, U. Avci:
Reliable Low-Voltage FeRAM Capacitors for High-Speed Dense Embedded Memory in Advanced CMOS. 1-2 - Sumi Lee, Chang Niu, Yizhi Zhang, Haiyan Wang, Peide D. Ye:
Positive to Negative Schottky Barrier Transition in Metal/Oxide Semiconductor Contacts by Tuning Indium Concentration in IGZO. 1-2 - Junsoo Kim, Hyun Jung Lee, Sung Ho Jang, Jun Bum Lee, Ilgweon Kim, Jeonghoon Oh, Jemin Park, Jaihyuk Song:
A Metal Dual Work-Function Gate (MDWG) for the Continuous Scaling of DRAM Cell Transistors. 1-2 - H. J. Li, K. P. Chang, C. E. Chen, W. T. Hsieh, H. H. Kuo, C. C. Huang, H. C. Chen, Z. H. Ya, H. Y. Chen, J. D. Jin, S. H. Yang, Y. W. Ting, K. C. Tseng, K. C. Huang, Harry Chuang:
A Novel Phase Change Material RF Switch with 16nm Technology to Achieve Low Voltage and Low Ron*Coff for mmWave. 1-2 - Victor Moroz, Xiaopeng Xu, Alexei Svizhenko, Xi-Wei Lin, Sergey Popov, Henry Sheng, Kenneth Larsen:
3DIC System-Technology Co-Optimization with a Focus on the Interplay of Thermal, Power, Timing, and Stress Effects. 1-2 - Sunbin Deng, Jungyoun Kwak, Junmo Lee, Dyutimoy Chakraborty, Jaewon Shin, Omkar Phadke, Sharadindu Gopal Kirtania, Chengyang Zhang, Khandker Akif Aabrar, Shimeng Yu, Suman Datta:
Demonstration of On-Chip Switched-Capacitor DC-DC Converters using BEOL Compatible Oxide Power Transistors and Superlattice MIM Capacitors. 1-2 - Qi Zhang, Jiaqi Dong, Xinwen Zhang, Yekan Chen, Zipeng Cheng, Bo Zhao, Yuxuan Luo:
A 430-μA 68.2-dB-SNR 133-dBSPL-AOP CMOS-MEMS Digital Microphone Based on Electrostatic Force Feedback Control. 1-2 - Zehao Lin, Chang Niu, Hyeongjun Jang, Taehyun Kim, Yizhi Zhang, Haiyan Wang, Changwook Jeong, Peide D. Ye:
Enhancement of In2O3 Field-Effect Mobility Up To 152 cm2.V-1·s-1Using HZO-Based Higher-k Linear Dielectric. 1-2 - Yang Feng, Dong Zhang, Chen Sun, Zijie Zheng, Yue Chen, Qiwen Kong, Gan Liu, Yuye Kang, Kaizhen Han, Zuopu Zhou, Gengchiau Liang, Kai Ni, Jixuan Wu, Jiezhi Chen, Xiao Gong:
First Demonstration of BEOL-Compatible 3D Vertical FeNOR. 1-2 - Davide Resnati, Gianpietro Carnevale, Shyam Surthi, Chris M. Carlson, Matthew Thorum, Terry Kim, Emilio Camerlenghi, Richard Hill:
A Confined Storage Nitride 3D-NAND Cell with WL Airgap for Cell-To-Cell Interference Reduction and Improved Program Performances. 1-2 - T. C. Kao, M. J. Huang, Y. R. Liu, Y. K. Wang, J. C. Guo, Steve S. Chung:
An Ultra-Low Voltage Auger-Recombination Enhanced Hot Hole Injection Scheme in Implementing a 3 Bits per Cell e-DRAM CIM Macro for Inference Accelerator. 1-2 - Bo-Jheng Shih, Yu-Ming Pan, Hao-Tung Chung, Chieh-Ling Lee, I-Chun Hsieh, Nein-Chih Lin, Chih-Chao Yang, Po-Tsang Huang, Hung-Ming Chen, Chiao-Yen Wang, Huan-Yu Chiu, Huang-Chung Cheng, Chang-Hong Shen, Wen-Fa Wu, Tuo-Hung Hou, Kuan-Neng Chen, Chenming Hu:
3DIC with Stacked FinFET, Inter-Level Metal, and Field-Size (25×33mm2) Single-Crystalline Si on SiO2 by Elevated-Epi. 1-2 - Pruek Vanna-Iampikul, Hang Yang, Jungyoun Kwak, Joyce X. Hu, Amaan Rahman, Nesara Eranna Bethur, Callie Hao, Shimeng Yu, Sung Kyu Lim:
Back-side Design Methodology for Power Delivery Network and Clock Routing. 1-2 - Chih-Sheng Lin, Bo-Cheng Chiou, Yin-Jia Yang, Jian-Wei Su, Kuo-Hua Tseng, Yun-Ting Ho, Chih-Ming Lai, Sih-Han Li, Tian-Sheuan Chang, Shan-Ming Chang, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Tuo-Hung Hou:
Empowering Local Differential Privacy: A 5718 TOPS/W Analog PUF-Based In-Memory Encryption Macro for Dynamic Edge Security. 1-2 - Taejune Jeon, Byeongseol Kim, Changuk Lee, Danbi Ahn, Daerl Park, Jaesuk Sung, Hee Young Kim, Heonjin Choi, Joonsung Bae, Youngcheol Chae:
A Wireless Neurostimulator Using Body-Coupled Link for Multisite Stimulation in Freely Behaving Animals. 1-2 - A. Divay, Olivier Valorge, Christophe Dubarry, M. Medbouhi, R. Franiatte, D. Mermin, R. Velard, Y. Gobil, F. Morisot, Erwan Morvan, Ismael Charlet, Luca Lucci, J. Lugo, Xavier Garros:
Hybrid Integration of 3D-RF Interconnects on AlGaN/GaN/Si HEMT RF Transistor featuring 2.2W/mm Psat & 41% PAE @28GHz using a Robust and Cost-Effective Chiplet Heterogeneous Bonding Technique. 1-2 - Ahmad Bahai:
Making Sense at the Edge. 1-2 - Inhwan Cho, Moo-Yeol Choi, Jaehyeok Byun, Ji-Hun Lee, Myungjin Lee, Dongsu Kim, Jongwoo Lee:
A 5.8W, 0.00086% THD+N, 118dB PSRR Class-D Audio Amplifier with Passive Output Common-Mode Compensation Technique for Wide Output Power Range. 1-2 - Hangxing Liu, Fuze Jiang, Adam Y. Wang, Zhikai Huang, Ying Kong, Marco Saif, Dongwon Lee, Thomas Burger, Jing Wang, Hua Wang:
Highly Sensitive Multimodal CMOS Antifouling Sensor Array with Multi-Use Electrodes for Single-Cell-Level Profiling of Biophysical and Biochemical Parameters. 1-2 - Jiyue Yang, Alexander Graening, Wojciech Romaszkan, Vinod K. Jacob, Puneet Gupta, Sudhakar Pamarti:
A 278-514M Event/s ADC-Less Stochastic Compute-In-Memory Convolution Accelerator for Event Camera. 1-2 - Myoungsub Kim, Yooncheol Bae, Jaehyuk Park, Jeongho Yeon, Hyungjoon Shim, Sehyun Jin, Hyunsoo Kim, Sangchul Oh, Gapsok Do, Dongyeol Yun, Hyung Dong Lee, David Ahn, Junghun Lee, Muhui Park, Junghyuk Yoon, Jeongho Yi, Taekseung Kim, Gain Park, Seoungju Chung, Junho Cheon, Sujin Chae, Namkyun Park, Kyunghoon Kim, Dongyean Oh, Jaeyun Yi, Seonyong Cha:
First Demonstration of Fully Integrated 16 nm Half-Pitch Selector Only Memory (SOM) for Emerging CXL Memory. 1-2 - Claudio Nani, Enrico Monaco, Nicola Ghittori, Alessandro Bosi, Domenico Albano, Claudio Asero, Nicola Codega, Alessio Di Pasquo, Ivan Fabiano, Marco Garampazzi, Fabio Giunco, Leonardo Daniel Herbas Burgos, Gabriele Minoia, Paolo Rossi, Marco Sosio, Leonardo Vignoli, Enrico Temporiti, Shawn Scouten, Stephen Jantzi:
A 5nm 60GS/s 7b 64-Way Time Interleaved Partial Loop Unrolled SAR ADC Achieving 34dB SNDR up to 32GHz. 1-2 - Seong Kwang Kim, Hyeongrak Lim, Jaeyong Jeong, Young-Keun Park, Jejune Park, Sungil Park, Jaehyun Park, Daewon Ha, Byung Jin Cho, Sanghyeon Kim:
Ge(110) GAA Nanosheet / Si(100) Tri-gate Nanosheet Monolithic CFETs Featuring Record-High Hole Mobility. 1-2 - Chenxin Liu, Zheng Li, Yudai Yamazaki, Hans Herdian, Chun Wang, Anyi Tian, Jun Sakamaki, Han Nie, Xi Fu, Sena Kato, Wenqian Wang, Hongye Huang, Shinsuke Hara, Akifumi Kasamatsu, Hiroyuki Sakai, Kazuaki Kunihiro, Atsushi Shirane, Kenichi Okada:
A 640-Gb/s 4×4-MIMO D-Band CMOS Transceiver Chipset. 1-2 - Jaeho Lee, Kyongsu Lee, Jae-Yoon Sim, Seon-Kyoo Lee:
A 246-fJ/b 13.3-Tb/s/mm Single-Ended Current-Mode Transceiver with Crosstalk Cancellation for Shield-Less Short-Reach Interconnect. 1-2 - Joan Aymerich, Chutham Sawigun, Jose Cisneros-Fernández, Xiaolin Yang, Carolina Mora Lopez:
A 16-Ch CMI-Tolerant Neural AFE with Inherent CM Detection and Shared CM Suppression Achieving 0.006mm2/Ch and 3.1μW/Ch. 1-2 - Cheng-Hsun Lu, Wei Tang, Jiyoon Han, Zhengya Zhang:
An 11.4mm2 40.2Gbps 17.4pJ/b/Iteration Soft-Decision Open Forward Error Correction Decoder for Optical Communications. 1-2 - Francescopaolo Mattioli Della Rocca, Edbert J. Sie, Ahmet T. Erdogan, Lars Fisher, Andrew B. Matheson, Neil Finlayson, Alistair Gorman, István Gyöngy, Hanning Mai, Thierry Lachaud, Russell Forsyth, Francesco Marsili, Robert K. Henderson:
A 512×512 SPAD Laser Speckle Autocorrelation Imager in Stacked 65/40nm CMOS. 1-2 - Kyeongtae Nam, Jaehyuk Kim, Dongil Lee, Kyuchang Kang, Sangyun Kim, ChangYoung Lee, Hyunchul Yoon, Donggeon Kim, Bokyeon Won, Jaejoon Song, Incheol Nam, Young-Hun Seo, Jeong-Don Ihm, Changsik Yoo, Sangjoon Hwang:
An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. 1-2 - Riccardo Moleri, Simone Mattia Dartizio, Michele Rossoni, Giacomo Castoro, Francesco Tesolin, Dmytro Cherniak, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino:
A 79.3fsrms Jitter Fractional-N Digital PLL Based on a DTC Chopping Technique. 1-2 - Hsing-Yen Tsai, Shi-Jun Zeng, Yu-Teng Liang, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li:
A Monolithic Low-ILEAK Cross-Coupled GaN Driver with ΔΦ-Reduced EMI-Rejecter for 21.51dBµV-EMI-Reduction and 1/10x filter-capacitor. 1-2 - J. Ganguly, Hiroaki Arimura, Romain Ritzenthaler, H. Bana, J. W. Maes, J. G. Lai, S. Brus, W. Maqsood, R. Sarkar, B. Kannan, Elena Capogreco, V. Machkaoutsan, S. Yoon, Alessio Spessot, M. Givens, Naoto Horiguchi:
DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM. 1-2 - Chongyun Zhang, Li Wang, Zilu Liu, Fuzhan Chen, Quan Pan, Xianbo Li, C. Patrick Yue:
A 48-Gb/s Half-Rate PAM4 Optical Receiver with 0.27-pJ/bit TIA Efficiency, 1.28-pJ/bit RX Efficiency, and 0.06-mm2 area in 28-nm CMOS. 1-2 - Taewon Seo, Changeon Jin, Yoonyoung Chung:
First Observation of Time Exponent Variations under Positive bias Stress on a-IGZO Transistors Utilizing Ultrafast On-the-Fly Technique with 1 μs Delay. 1-2 - Xuxu Cheng, Hongzhi Wu, Liping Zhong, Weitao Wu, Quan Pan:
A 2×56Gb/s Single-Ended Orthogonal PAM-7 Transceiver with Encoder-Based Channel-Independent Crosstalk Cancellation in 28-nm CMOS. 1-2 - Sungjin Oh, Hyunsoo Song, Jose Roberto Lopez Ruiz, Wangbo Chen, Sung-Yun Park, Michael P. Flynn, Euisik Yoon:
A 79.2dB-SNDR Slope-Adaptive Dynamic Zoom-and-Track Incremental sΔΔ Neural Recording Frontend with Resolution-Preservative 192mV/ms Transient Tracking. 1-2 - S.-H. Lin, Marko Simicic, N. Pantano, S.-H. Chen, Geert Van der Plas, Eric Beyne, Piet Wambacq:
Toward 0 V ESD Protection in 2.5D/3D Advanced Bonding Technology. 1-2 - Qiaochu Zhang, Shiyu Su, Zerui Liu, Hsiang-Chun Cheng, Zhengyi Qiu, Mayank Palaria, Jiacheng Ye, Deming Meng, Buyun Chen, Sushmit Hossain, Wei Wu, Mike Shuo-Wei Chen:
A Stochastic Analog SAT Solver in 65nm CMOS Achieving 6.6μs Average Solution Time with 100% Solvability for Hard 3-SAT Problems. 1-2 - Menggan Liu, Zhi Li, Wendong Lu, Kaifei Chen, Jiebin Niu, Fuxi Liao, Zijing Wu, Congyan Lu, Weizeng Li, Di Geng, Nianduan Lu, Chunmeng Dou, Guanhua Yang, Ling Li, Ming Liu:
First Demonstration of Monolithic Three-Dimensional Integration of Ultra-High Density Hybrid IGZO/Si SRAM and IGZO 2T0C DRAM Achieving Record-Low Latency (5000s). 1-2 - Gautam R. Gangasani, A. Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. B. Ramakrishna, U. K. Shukla:
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS. 1-2 - J.-H. Yoo, Y.-S. Jeon, S.-W. Son, I.-G. Lee, H.-B. Jo, S.-M. Choi, M.-S. Yu, W.-S. Park, H.-J. Kim, H.-J. Lee, S.-P. Son, S. K. Kim, J. Yun, J.-P. Shim, H. Jang, K. Lee, Y. Jeong, T. Kim, C.-S. Shin, T.-W. Kim, J.-H. Lee, K.-S. Seo, K. Yang, D.-H. Kim:
Single-Power-Supply Compatible Cryogenic In0.8Ga0.2As Quantum-well HEMTs with Record Combination of high-frequency and low-noise performance for quantum-computins applications. 1-2 - Zhuoyu Dai, Shengzhe Yan, Zhaori Cong, Zeyu Guo, Yifan He, Wenyu Sun, Chunmeng Dou, Feng Zhang, Jinshan Yue, Yongpan Liu, Ming Liu:
A 41.7TOPS/W@INT8 Computing-in-Memory Processor with Zig-Zag Backbone-Systolic CIM and Block/Self-Gating CAM for NN/Recommendation Applications. 1-2 - Tomotaka Tanaka, Yuichiro Ishii, Makoto Yabuuchi, Yumito Aoyagi, Masaya Hamada, Kazuto Mizutani, Koji Nii, Hidehiro Fujiwara, Isabel Wang, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang:
A 3nm Fin-FET 19.87-Mbit/mm2 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction. 1-2 - Sushil Subramanian, Todor Mladenov, Simon Schaal, Bishnu Patra, Lester Lampert, Nancy K. Robinson, Jeanette Roberts, Stefano Pellerano:
A Scalable mK Cryo-CMOS Demultiplexer Chip for Voltage Biasing and High-Speed Control of Silicon Qubit Gates. 1-2 - A. Liao, M. Jerry, K. Karda, Matthew Hollander, P. Sharma, R. Ge, T. Zhao, G. K. El Hajjam, M. Mariani, M. Calabrese, D. Raimondi, A. Rigano, T. Rossi, K. Florent, N. Tapias, C. Jacob, Alessandro Calderoni, S. Chhajed, J. Zahurak, Nirmal Ramaswamy:
4F2 Stackable Polysilicon Channel Access Device for Ultra-Dense NVDRAM. 1-3 - S. Li, Sundeep Javvaji, V. Pecanins-Martinez, E. Aydin, Robert H. M. van Veldhoven, Kofi A. A. Makinwa:
A Beyond-the-rail Audio CTΔΣM with a Passive Input Stage and 99.2dB SNDR. 1-2 - S. Mishra, Bjorn Vermeersch, Sankatali Venkateswarlu, Halil Kukner, Gioele Mirabelli, Fabian M. Bufler, Moritz Brunion, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Francky Catthoor, Pieter Weckx, Geert Hellings, James Myers, Julien Ryckaert:
Thermal Considerations for Block-Level PPA Assessment in Angstrom Era: A Comparison Study of Nanosheet FETs (A10) & Complementary FETs (A5). 1-2 - C. C. Wang, C. C. Kuo, C. H. Wu, A. Lu, H. Y. Lee, C. F. Hsu, P. J. Tzeng, T. Y. Lee, F. R. Hou, M. H. Chang, S. C. Lai, K. Goto, Shimeng Yu, C. I. Wu, C. T. Lin, Y. M. Lin, X. Y. Bao:
P-type SnO Semiconductor Transistor and Application. 1-2 - Quanrong Zhuang, Junyi Sun, Xusheng Zhang, Bo Li, Yi Shi, Hao Qiu:
A 6.78 MHz Wireless Power and Data Transfer System Achieving Simultaneous 52.6% End-to-End Efficiency and 4.0 Mb/s Forward Data Delivery with Interference-Free Rectifier. 1-2 - Edward Jongyoon Choi, Vincent Lukito, Injun Choi, Seoyoung Lee, Ik-Joon Chang, Sohmyung Ha, Minkyu Je:
A Δ-Based Spike Sorting SoC with End-to-End Implementation of Event-Driven Binary Autoencoder Neural Network in Analog CIM Achieving 94.54% Accuracy and 3.11μW/ch. 1-2 - Xiaohua Huang, Xiaolin Yang, Andrea Lodi, Chris Van Hoof, Georges G. E. Gielen, Carolina Mora Lopez:
A 3072-Channel Neural Readout IC with Multiplexed Two-Step Incremental-SAR Conversion and Bulk-DAC-Based EDO Compensation in 22nm FDSOI. 1-2 - Shuhan Liu, Shengjun Qin, Koustav Jana, Jian Chen, Kasidit Toprasertpong, H.-S. Philip Wong:
First Experimental Demonstration of Hybrid Gain Cell Memory with Si PMOS and ITO FET for High-speed On-chip Memory. 1-2 - Boyang Zhang, Zhifei Wang, Zeze Feng, Tianchen Ye, Bingyi Ye, Zixu Wang, Weixin Gai:
A 200-Gb/s PAM-4 Transmitter with 1.6-Vppd Output Swing and Clock Skew Correction in 12-nm FinFET. 1-2 - Animesh Gupta, Japesh Vohra, Viveka Konandur Rajanna, Massimo Alioto:
122.7 TOPS/W Stdcell-Based DNN Accelerator Based on Transition Density Data Representation, Clock-Less MAC Operation, Pseudo-Sparsity Exploitation in 40 nm. 1-2 - H. Terada, K. Yamaguchi, T. Yokoi, T. Sameshima, K. Suzuki, G. Nakamura, H. Nagai:
Up to 57% Reduction in Effective Resistivity of Word Lines of 3D-NAND Memory by Grain-Size Control, Material Selection, and Seam Removal. 1-2 - Arnaud Verdant, William Guicquero, David Coriat, Guillaume Moritz, Nicolas Royer, Sébastien Thuries, Anais Mollard, Vincent Teil, Yann Desprez, Gilles Monnot, Pierre Malinge, Bruno Paille, Guillaume Caubit, Arnaud Bourge, Laurent Tardif, Stephanie Bigault, Jérôme Chossat:
A 450µW@50fps Wake-Up Module Featuring Auto-Bracketed 3-Scale Log-Corrected Pattern Recognition and Motion Detection in a 1.5Mpix 8T Global Shutter Imager. 1-2 - Anshul Gupta, Shreya Kundu, Stefan Decoster, K. Sah, G. Delie, B. Truijen, Davide Tierno, Giulio Marti, O. Varela Pedreira, B. Kenens, Y. Hermans, C. Adelmann, B. de Wachter, Ivan Ciofi, G. Murdoch, A. Cross, Seongho Park, Zsolt Tokei:
Mitigating Line-Break Defectivity with a Sandwiched TiN or W Layer for Metal Pitch 18 NM Aspect Ratio 6 Semi-Damascene Interconnects. 1-2 - Haoran Lu, Yandong Ge, Xun Jiang, Jiacheng Sun, Wanyue Peng, Rui Guo, Ming Li, Yibo Lin, Runsheng Wang, Heng Wu, Ru Huang:
First Experimental Demonstration of Self-Aligned Flip FET (FFET): A Breakthrough Stacked Transistor Technology with 2.5T Design, Dual-Side Active and Interconnects. 1-2 - Fabio Giunco, Marco Sosio, Claudio Nani, Ivan Fabiano, Travis Lovitt, Victor Karam, D. Albano, C. Asero, Nicola Codega, Marco Garampazzi, Nicola Ghittori, D. Herbas, S. Ho, Enrico Monaco, Benjamín T. Reyes, P. Rossi, E. Temporiti, P. Pascale, Fernando De Bernardinis, S. Scouten, S. Jantzi:
A 800Gb/s Transceiver for PAM-4 Optical Direct-Detection Applications in 5nm FinFet Process. 1-2 - Rohit Rothe, Jungho Lee, Zichen Fan, Li-Yu Chen, Donguk Seo, Yoonmyung Lee, Dennis Sylvester, David T. Blaauw:
A uW Output Power, >100V, Single-Capacitor Switched DC-DC Up/Down Converter. 1-2 - Zefu Zhao, Yu-Rui Chen, Yu-Tsung Liao, Yun-Wen Chen, Wan-Hsuan Hsieh, Jer-Fu Wang, Yu-An Chen, Hao-Yi Lu, Wei-Teng Hsu, Dai-Ying Lee, Ming-Hsiu Lee, C. W. Liu:
Engineering HZO by Flat Amorphous TiN with 0.3nm Roughness Achieving Uniform c-Axis Alignment, Record High Breakdown Field (~10nm HZO), and Record Final 2Pr of 56 μC/cm2 with Endurance > 4E12. 1-2 - Po-Jui Chiu, Tz-Wun Wang, Chi-Yu Chen, Sheng-Hsi Hung, Yu-Ting Huang, Xiao-Quan Wu, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li:
A 15.4ppm/○C GaN-based Voltage Reference with Process-Variation-Immunity and High PSR for EV Power Systems. 1-2 - Qinjing Pan, Qi Luo, Tianxiang Qu, Liheng Liu, Xiao Li, Min Chen, Zhiliang Hong, Jiawei Xu:
A 97.3dB SNR Bioimpedance AFE with -84dB THD Segmented-ΔΣM Sinusoidal Current Generator and Passing-Through Instrumentation Amplifier. 1-2 - Yanchi Dong, Xueping Liu, Kangbo Bai, Guoxiang Li, Meng Wu, Yiqi Jing, Yihan Zhang, Pixian Zhan, Yadong Zhang, Yufei Ma, Ru Huang, Le Ye, Tianyu Jia:
A Heterogeneous TinyML SoC with Energy-Event-Performance-Aware Management and Compute-in-Memory Two-Stage Event-Driven Wakeup. 1-2 - Seongyon Hong, Wooyoung Jo, Sangjin Kim, Sangyeob Kim, Kyomin Sohn, Hoi-Jun Yoo:
Dyamond: A 1T1C DRAM In-memory Computing Accelerator with Compact MAC-SIMD and Adaptive Column Addition Dataflow. 1-2 - Juzheng Liu, Ayman Shabra, Stacy Ho, Gabriele Manganaro, Mike Shuo-Wei Chen:
A 16GS/s 10b Time-domain ADC using Pipelined-SAR TDC with Delay Variability Compensation and Background Calibration Achieving 153.8dB FoM in 4nm CMOS. 1-2 - Suman Datta, Eknath Sarkar, Khandker Akif Aabrar, Shan Deng, Jaewon Shin, Arijit Raychowdhury, Shimeng Yu, Asif Khan:
Amorphous Oxide Semiconductors for Monolithic 3D Integrated Circuits. 1-2 - Zhiqiang Huang, Fengjun Chen, Shuangfeng Kong:
A 5GHz Fractional-N PLL with 97fsrms Jitter and -255.3dB FoM. 1-2 - Khandker Akif Aabrar, Hyeonwoo Park, Sharadindu Gopal Kirtania, Eknath Sarkar, Md Abdullah Al Mamun, Sunbin Deng, Chengyang Zhang, Gilbert B. Rayner, Kyeongjae Cho, Suman Datta:
On the Reliability of High-Performance Dual Gate (DG) W-Doped In2O3 FET. 1-2 - Minjong Lee, Jin-Hyun Kim, Dan N. Le, Seojun Lee, Si-Un Song, Rino Choi, Youngbae Ahn, Seung Wook Ryu, Pil-Ryung Cha, Chang-Yong Nam, Seongbin Park, Jongmug Kang, Si Joon Kim, Jiyoung Kim:
BEOL Compatible Ultra-Low Operating Voltage (0.5 V) and Preconfigured Switching Polarization States in Effective 3 nm Ferroelectric HZO Capacitors. 1-2 - M. Otomo, Kasidit Toprasertpong, Z. Cai, Z. Liu, Mitsuru Takenaka, S. Takagi:
Revealing Mechanism of Non-Accumulative Disturb and Approach Toward Disturb Suppression in HZO/Si FeFET Memory. 1-2 - Raghavan Kumar, Sachin Taneja, Vivek De, Sanu Mathew:
A 4.7-to-5.3Gbps Fault-Injection Attack Resistant AES-256 Engine Using Isomorphic Composite Fields in Intel 4 CMOS. 1-2 - Guixu Zhu, Xiaodong Zhang, Haotian Fang, Dongdong Sun, Luyang Wang, Zujian Dai, Lizi Wei, Qiuyang Lin, Ao Li, Yufeng Min, Qiuxia Lu, Lixin He, Dongsheng Song, Yuanyuan Shi:
Single-Crystalline Monolayer Mos2 Arrays Based High-Performance Transistors via Selective-Area CVD Growth Directly on Silicon Wafers. 1-2 - Ruilong Xie, Wonhyuk Hong, Chen Zhang, Jongjin Lee, Kevin Brew, Richard Johnson, Nicholas A. Lanzillo, Hosadurga Shobha, Taesun Kim, Panjae Park, Shogo Mochizuki, Iqbal Saraf, Chanro Park, Lei Zhuang, Clifford Osborn, Wai Kin Li, Feng Liu, Muthumanickam Sankarapandian, Chung Ju Yang, Juntao Li, Lukas Tierney, Ruturaj Pujari, Yasir Sulehria, Yuncheng Song, Huimei Zhou, Miaomiao Wang, Michael Belyansky, Somnath Ghosh, Haojun Zhang, Koichi Motoyama, Debarghya Sarkar, Wukang Kim, Albert Chu, Tao Li, Fabio Carta, Oleg Gluschenkov, Joongsuk Oh, Matthew Malley, Pinlei Chu, Son Nguyen, Katherine Luedders, Joe Lee, Shahrukh Khan, Prabudhya Roy Chowdhury, Huai Huang, Abir Shadman, Stuart Sieg, Daniel Dechene, Daniel Edelstein, John Arnold, Tenko Yamashita, Kisik Choi, Kang-ill Seo, Dechao Guo, Huiming Bu:
Backside Power Distribution for Nanosheet Technologies Beyond 2nm. 1-2 - Feng-Min Lee, Po-Hao Tseng, Yu-Yu Lin, Yu-Hsuan Lin, Wei-Lun Weng, Nei-Chih Lin, Po-Jung Sung, Chien-Ting Wu, Chih-Chao Yang, Wen-Fa Wu, Chang-Hong Shen, Tuo-Hung Hou, Ming-Hsiu Lee, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu:
Bit-Cost-Scalable 3D DRAM Architecture and Unit Cell First Demonstrated with Integrated Gate-Around and Channel-Around IGZO FETs. 1-2 - Hyun-Gi Seok, Wan Kim, Sinyoung Kim, Jae-Keun Lee, Chanho Kim, Chanbin Ko, Junseong Park, Wonkang Kim, Jongpil Cho, Seungyong Bae, Youngsea Cho, Wonjun Jung, Junhyeong Kim, Sumin Kang, Hyeokju Na, Byoungjoong Kang, Honggul Han, Hoon Kang, Minki Ahn, Chiyoung Ahn, Sukjin Jung, Hyukjun Sung, Seunghyun Oh, Jae-Eun Lee, Jongwoo Lee, Joonsuk Kim:
A -96.5 dBm-Sensitivity, 14 dBm Peak Power, Self-Interference Resistant IR-UWB Radar Transceiver Supporting Child Presence Detection and Precision Positioning. 1-2 - S. Ghosh, A. Kruv, Quentin Smets, Tom Schram, D. J. Leech, T. Ding, V. Turkani, Benjamin Groven, A. Dangel, G. Probst, Thomas Uhrmann, Markus Wimplinger, Inge Asselberghs, Cesar J. Lockhart de la Rosa, Steven Brems, Gouri Sankar Kar:
EOT Scaling Via 300mm MX2 Dry Transfer - Steps Toward a Manufacturable Process Development and Device Integration. 1-2 - Dongchan Jeong, Seungkwon Kim, Seulki Park, Sanghyeon Lee, Sada-Aki Masuoka, Byungha Choi, Shincheol Min, Sanghoon Lee, Minseong Lee, Chang-Woo Sohn, Jaehun Jeong, Yuri Yasuda-Masuoka, Ja-Hum Ku:
Product Performance Aware 3rd Generation GAA Platform Transistor Design with Extreme Small Local Layout Effect and Transistor Variation. 1-2 - R. Mathur, R. Sisodia, A. Chen, A. Singh, S. Thyagarajan, A. Cubeta, C. Andrieux, A. Sowden, Y. K. Chong:
A 7GHz High-Bandwidth 1R-1RW SRAM for Arm HPC Processor in 3nm Technology. 1-2 - Hangxing Liu, Fuze Jiang, Ying Kong, Dongwon Lee, Yuguo Sheng, Adam S. Wang, Zhikai Huang, Marco Saif, Thomas Burger, Jing Wang, Hua Wang:
A Subcellular-Resolution Multimodal CMOS Biosensor Array with 16K Ion-Selective Pixels for Real-Time Monitoring Potassium Dynamics. 1-2 - Jeongmyeong Kim, Changjoo Park, Wanyeong Jung:
A 0.6-1 V $\mathrm{V}_{\text{IN}}$ Soft-Switching Low Dropout Regulator with 31.3 A/mm2 Current Density, 99.99% Current Efficiency, and 2.04 fs FoM. 1-2 - Shota Konno, Zachary J. Ellis, Anupam Golder, Sigang Ryu, Daniel Dinu, Avinash Varna, Sanu Mathew, Arijit Raychowdhury:
A 65nm Delta-Sigma ADC Based VDD-Variation-Tolerant Power-Side-Channel-Attack Monitor with Detection Capability Down to 0.25Ω. 1-2 - R. Berthelon, Olivier Weber, F. Ibars, B. Revel, C. Borowiak, J. C. Grenier, B. Dumont, S. Desmoulins, P. O. Sassoulas, P. Ferreira, S. Chouteau, S. Niel, Rossella Ranica, R. Gonella, Franck Arnaud:
Unlimited Bi-directional Back-Bias in FD-SOI Technology With New Dual Isolation Integration. 1-2 - Yiqi Wang, Zhen He, Chenggang Zhao, Zihan Wu, Mingyu Gao, Huiming Han, Shaojun Wei, Yang Hu, Fengbin Tu, Shouyi Yin:
ETCIM: An Error-Tolerant Digital-CIM Processor with Redundancy-Free Repair and Run-Time MAC and Cell Error Correction. 1-2 - H. Fukutome, J. Kim, Joonghan Shin, Youngsoo Lee, Youngsoo Park, Do-Youn Oh, Seung-Hoon Chae, B. Eom, You Nam, Minseong Lee, Sanghyun Ha, Eun-Ae Chung, Moon-Ho Jo, Sung-Hoon Lee, Sang Kim, Keun Cho, Kyung-Woo Lee, Dong Kim, H. J. Cho, Kwan Rim, SD Kwon, Jun-Ho Song:
Demonstration of Logic-Block Performance-Power Gain by 1st Generation Back Side Power Delivery Network for SoC and HPC Applications Beyond 2nm Node. 1-2 - Hiroaki Kitaike, Masaharu Inada, Mitsuru Terauchi, Hironori Tagawa, Ryosuke Nagai, Shufan Xu, Ruilin Zhang, Kunyang Liu, Kiichi Niitsu:
A 0.9-2.6pW 0.1-0.25V 22nm 2-bit Supply-to-Digital Converter Using Always-Activated Supply-Controlled Oscillator and Supply-Dependent-Activation Buffers for Bio-Fuel-Cell-Powered-and-Sensed Time-Stamped Bio-Recording. 1-2 - Chun-Wei Chang, I-Ting Lin, Chia-Hsiang Yang:
A 101mW, 280fps Scene Graph Generation Processor for Visual Context Understanding on Mobile Devices. 1-2 - Byung-Sung Kim, Subin Choi, Jung Han Lee, Kwangmuk Lee, Jisoo Park, Jiwook Kwon, Saehan Park, Kwanyoung Chun, Harsono Simka, Aravindh Kumar, Muhammed Ahosan Ul Karim, Ken Rim, Jaihyuk Song:
Expanding Design Technology Co-Optimization Potentials with Back-Side Interconnect Innovation. 1-2 - Sashank Krishnamurthy, Susnata Mondal, Junyi Qiu, Joe Kennedy, Soumya Bose, Tolga Acikalin, Shuhei Yamada, James E. Jaussi, Mozhgan Mansuri:
A 4×50Gb/s NRZ 1.5pJ/b Co-Packaged and Fiber-Terminated 4-Channel Optical RX. 1-2 - Rahul Lall, Kyoungtae Lee, Adam Cunha, Rebecca Abergel, Youngho Seo, Ali M. Niknejad, Mekhail Anwar:
A 76×55 X-Ray Energy Binning Dosimeter for Closed-Loop Cancer Radiotherapy. 1-2 - Haidam Choi, Gichan Yun, Ji-Hoon Suh, Sein Oh, Song-I Cheon, Yoontae Jung, Sohmyung Ha, Minkyu Je:
A Fully Dynamic 1st-Order Δ-ΔΣ Modulator with a 468mVpp Input Range for Electrical Impedance Tomography Systems. 1-2 - Dongjun Park, Heesung Roh, Seon-Kyoo Lee, Jae-Yoon Sim:
A $94\text{fs}_{\text{rms}}$-Jitter and -249.3dB FoM 4.0GHz Ring-Oscillator-Based MDLL with Background Calibration of Phase Offset and Injection Slope Mismatch. 1-2 - J. Luge-Alvarez, J. B. David, Alexandre Siligaris, Vincent Puyal, G. Moritz, Tadeu Mota Frutuoso, V. Lapras, Claire Fenouillet-Béranger, Laurent Brunet, P. Vincent, Didier Lattard, Xavier Garros, François Andrieu, Perrine Batude:
First Radio-Frequency Circuits Fabricated in Top-Tier of a Full 3D Sequential Integration Process at mmW for 5G Applications. 1-2 - Kazuoki Matsugatani:
Mobility Evolution: Electrification and Automation. 1-4 - Sayan Kumar, Patchara Sawakewang, Teerachot Siriburanon, Robert Bogdan Staszewski:
A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling. 1-2 - Dae-Hyeon Kim, Jeong-Hyun Cho, Hyunki Han, Hyun-Sik Kim:
A 1.8V-Input 0.2-to-1.5V-Output 2.5A 930mA/mm3 Always-Balanced Dual-Path Hybrid Buck Converter with Seamlessly All-VCR-Coverable Tri-Mode Operation. 1-2 - Byungchoul Park, Hyun-Seung Choi, Jinwoong Jeong, Jimin Cheon, Myung-Jae Lee, Youngcheol Chae:
A 7.2inch 5.5Mpixel 600mW SPAD X-Ray Detector with 116.7 dB Dynamic Range. 1-2 - Yu-Teng Liang, Shi-Jun Zeng, Yu-Tse Shih, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li:
A ±100A Auto-Calibration Current Sensor with 80V Pulse-Width Modulation Attenuation and 0.15% Gain Error. 1-2 - Nahyun Rheem, Jaeyong Jeong, Yoon-Je Suh, Chan Jik Lee, Bong Ho Kim, Joon Pyo Kim, Seong Kwang Kim, Hyeongrak Lim, Jongmin Kim, Dae-Hwan Ahn, Jae-Hoon Han, Jongwon Lee, Sanghyeon Kim:
First Heterogeneous and Monolithic 3D (HM3D) Integration of InGaAs HEMTs and InP/InGaAs DHBTs on Si CMOS for Next-Generation Wireless Communication. 1-2 - Ruixin Mao, Lin Tang, Zihan Xia, Zhaomin Zhang, Aoyu Shen, Yu Long, Jinhong Guo, Yunpeng He, Lai Zhang, Shujuan Wang, Liang Zhou, Liang Chang, Shanshan Liu, Jun Zhou:
FSNAP: An Ultra-Energy-Efficient Few-Spikes-Neuron Based Reconfigurable SNN Processor Enabling Unified On-Chip Learning and Accuracy-Driven Adaptive Time-Window Tuning. 1-2 - Jingshu Yu, Xiaosen Liu, Minxiang Gong, Nicolas Butzen, Sheldon Weng, Harish K. Krishnamurthy, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, Jim Waldemer, Christopher Pelto, James W. Tschanz, Vivek De:
A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs. 1-2 - H. Yang, Y. Li, Jianshi Tang, R. An, Y. Zhang, L. Gao, N. Gao, H. Xu, Y. Du, Z. Liu, X. Ma, G. Wang, C. Zhao, J. Xiang, J. Zhao, W. Bu, K. Zheng, J. Kang, B. Gao, H. Qian, H. Wu:
Monolithic 3D Integration of Analog RRAM-Based Fully Weight Stationary and Novel CFET 2T0C-Based Partially Weight Stationary for Accelerating Transformer. 1-2 - Sijung Yoo, Donghoon Kim, Duk-Hyun Choe, Hyun Jae Lee, Yunseong Lee, Sanghyun Jo, Yoonsang Park, Ki Hong Kim, Kyooho Jung, Moonil Jung, Kwang-Hee Lee, Jee-Eun Yang, Sangwook Kim, Seung-Geol Nam:
Highly Enhanced Memory Window of 17.8V in Ferroelectric FET with IGZO Channel via Introduction of Intermediate Oxygen-Deficient Channel and Gate Interlayer. 1-2 - Chien-Hung Lin, Jeng-Yun Hsu, Cheng-Ying Yu, Chia-Wei Hsu, Yi-Min Tsai, Kuo-Sheng Wu, Chung-Lun Huang, Meng-Han Hsieh, Tsung-Yao Lin:
A Quad-Core AI Processing Unit for Generative AI in 4nm 5G Smartphone SoC. 1-2 - T. Kuno, T. Utsugi, N. Lee, T. Mine, I. Yanagi, S. Muraoka, R. Mizokuchi, Jun Yoneda, Tetsuo Kodera, T. Nakajima, A. J. Ramsay, N. Mertig, S. Saito, D. Hisamoto, R. Tsuchiya, H. Mizuno:
Concatenated Continuous Driving for Extending Lifetime of Spin Qubits Towards a Scalable Silicon Quantum Computer. 1-2 - Chu-En Hsia, Chin-Ho Chang, Yung-Shun Chen, Po-Yu Lai, Ching Lin Jen, Yung-Chow Peng, Shenggao Li:
Current Mirrors with Tapered Stacked-Gates for Area Saving or Noise Improvement in 3nm FinFET Process. 1-2 - Seung Hyun Oh, Changhyeon Lee, Hee Tae Kim, Jeong Ik Park, Min Ju Kim, Se Jun Park, Sung Gap Im, Sung Haeng Cho, Byung Jin Cho:
Overcoming Performance Limitation of IGZO FET by iCVD Fluorine Doping. 1-2 - De-Qi You, Win-San Khwa, Jui-Jen Wu, Chuan-Jia Jhang, Guan-Yi Lin, Po-Jung Chen, Ting-Chien Chiu, Fang-Yi Chen, Andrew Lee, Yu-Cheng Hung, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang:
A 22nm Nonvolatile AI-Edge Processor with 21.4TFLOPS/W using 47.25Mb Lossless-Compressed-Computing STT-MRAM Near-Memory-Compute Macro. 1-2 - Brian Crafton, Samuel D. Spetalnick, Muya Chang, Arijit Raychowdhury:
A 28nm Approximate / Binary 6T CAM for Sequence Alignment. 1-2 - T. Fukushima, T. Kashima, S. Seto, H. Ohtori, M. Kato, K. Katou, H. Takehira, Y. Sugawara, Z. Zhu, K. Hara, R. Osanai, T. Beppu, H. Tahara, T. Ishiku, K. Takahashi, T. Ariga, Y. Ueda, Y. Matamura, Y. Mukae, N. Takeguchi, Y. Maruyama, R. Nishikawa, H. Kitagawa, J. Asakawa, Y. Uchiyama, K. Ohuchi, K. Sekine:
Fluorine-free Word Line Molybdenum Process for Enhancing Scalability and Reliability in 3D Flash Memory. 1-2 - Hang-Ah Park, Sejun Park, Min-Tai Yu, Ye-Chan Kim, Cheon Ho Park, Jung Hoon Lee, Jun Eon Jin, Dawoon Jeung, Hauk Han, Tai-Soo Lim, Min-Kyu Jeong, Mincheol Park, Bong-Tae Park, Sunghoi Hur:
Innovative Barrier Metal-Less Metal Gate Scheme Leading to Highly Reliable Cell Characteristics for 8th Generation 512Gb 3D NAND Flash Memory. 1-2 - Kent Edrian Lozada, Ye-Dam Kim, Ho-Jin Kim, Youngjae Cho, Michael Choi, Seung-Tak Ryu:
A 0.38mW 200kHz-BW 92.1dB-DR Single-Opamp 4th-Order Continuous-Time Delta-Sigma Modulator with 3rd-Order Noise Coupling. 1-2 - K. Morimoto, N. Isoda, H. Sekine, Tomoya Sasago, Y. Maehashi, S. Mikajiri, Kenzo Tojima, M. Shinohara, A. Abdelghafar, Hiroyuki Tsuchiya, K. Inoue, S. Omodani, K. Chida, A. Ehara, J. Iwata, T. Itano, Yasushi Matsuno, K. Sakurai, T. Ichikawa:
3D-Stacked 1Megapixel Time-Gated SPAD Image Sensor with 2D Interactive Gating Network for Image Alignment-Free Sensor Fusion. 1-2 - Jonghang Choi, Ingu Jeong, Seok-Won Jung, Jun-Eun Park:
A 92.8% Power Reduction Event-Driven Dual-Mode Touch Analog Front-End IC Featuring 620μW Self-Capacitance Sensing and 500fps Mutual-Capacitance Sensing. 1-2 - Mu-Shan Lin, Chien-Chun Tsai, Shenggao Li, Tze-Chiang Huang, Wen-Hung Huang, Kate Huang, Yu-Chi Chen, Alex Liu, Yu-Jie Huang, Jimmy Wang, Shu-Chun Yang, Nai-Chen Cheng, Chao-Chieh Li, Hsin-Hung Kuo, Wei-Chih Chen, Chin-Hua Wen, Kevin Lin, Po-Yi Huang, Kenny Cheng-Hsiang Hsieh, Frank Lee:
A 0.296pJ/bit 17.9Tb/s/mm2 Die-to-Die Link in 5nm/6nm FinFET on a 9μm-Pitch 3D Package Achieving 10.24Tb/s Bandwidth at 16Gb/s PAM-4. 1-2 - Liping Zhong, Yangyi Zhang, Xiongshi Luo, Hongzhi Wu, Xuxu Cheng, Weitao Wu, Zhenghao Li, Quan Pan:
A 2x112 Gb/s 0.34 pJ/b/Lane Single-Ended PAM4 Receiver with Multi-Order Crosstalk Cancellation and Signal Reutilization Technique in 28-nm CMOS. 1-2 - J. Gu, J. Ma, J. Guo, F. Guo, D. Liang, Y. Li, C. Shen, P. Gao, X. Zhang, J. Ding, M. Sorna, H. Wang, C. Cui, J. Troupe, P. Metty, Ken Chang:
A 32Gb/s 0.36pJ/bit 3nm Chiplet IO Using 2.5D CoWoS Package with Real-Time and Per-Lane CDR and Bathtub Monitoring. 1-2 - Kaito Hikake, Xingyu Huang, Sung-Hun Kim, Kota Sakai, Zhuo Li, Tomoko Mizutani, Takuya Saraya, Toshiro Hiramoto, Takanori Takahashi, Mutsunori Uenuma, Yukiharu Uraoka, Masaharu Kobayashi:
Scaling Potential of Nanosheet Oxide Semiconductor FETs for Monolithic 3D Integration-ALD Material Engineering, High-Field Transport, Statistical Variability. 1-2 - Sehoon Lee, Jieun Lee, Sungpil Jang, Sujeong Kim, Choelgyu Kim, Narae Jeong Sae-Jin Kim, Jisoo Kang, Juhee Hong, Dong-Kyu Kim, Junhee Lim, Sejun Park, Seungwan Hong, Sunghoi Hur:
Mechanical Stress Effects on Dielectric Leakage and Interconnection Integrity in 3D NAND Flash Memory. 1-2 - Dong Zhang, Yang Feng, Zijie Zheng, Chen Sun, Qiwen Kong, Gan Liu, Zuopu Zhou, Gengchiau Liang, Kai Ni, Jixuan Wu, Jiezhi Chen, Xiao Gong:
Unveiling Cryogenic Performance (4 to 300 K) Towards Ultra-Thin Ferroelectric HZO: Novel Kinetic Barrier Engineering and Underlying Mechanism. 1-2 - Jae-Hyun Kim, Yousung Park, Doyoung Kwon, Dong-Kyu Kim, Sung-Chun Park, Yongjae Lee, Jung-Bong Lee, Hyun-Sik Kim:
A 96.4%-Efficiency Single-Duty-Cycled Buck-Boost Converter Achieving 1.9mV Ripple and 2.1mV Mode-Change Fluctuation for Mobile OLED Displays. 1-2 - Haibiao Zuo, Xiaoliang Huang, Shiqiao Zhang, Chip-Hong Chang, Xiaojin Zhao:
An In-Sensor PUF Featuring Optical Reconfigurability and Near-100% Hardware Reuse Ratio for Trustworthy Sensing. 1-2 - Zeynep Toprak Deniz, Timothy O. Dickson, Martin Cochet, Jonathan E. Proesel, John F. Bulzacchelli, Herschel A. Ainspan, Matthias Brändli, Thomas Morf, Michael P. Beakes, Mounir Meghelli:
A 0.88pJ/bit 112Gb/s PAM4 Transmitter with $1\mathrm{V}_{\text{ppd}}$ Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS. 1-2 - A. Chowdhury, J. Ma, Y. Li, J. Guo, X. Zhang, P. B. Ramakrishna, J. Gu, Y. Wang, L. Liang, U. K. Shukla, K. Mohammad, H. Yan, Y. Sun, M. Lin, Z. Jiang, F. Khan, M. Yeoh, C. Su, J. Ding, M. Baecher, S. Parker, H. Wang, M. Seymour, Michael Wielgos, Ken Chang:
A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology. 1-2 - Sehwan Lee, Taeryoung Seol, Geunha Kim, Minyoung Song, Gain Kim, Jong-Hyeok Yoon, Arup K. George, Junghyup Lee:
A 97dB-PSRR 178.4dB-FOMDR Calibration-Free VCO-ΔΣ ADC Using a PVT-Insensitive Frequency-Locked Differential Regulation Scheme for Multi-Channel ExG Acquisition. 1-2 - W. Mortelmans, P. Buragohain, C. Rogan, A. Kitamura, C. J. Dorow, K. P. O'Brien, R. Ramamurthy, J. Lux, T. Zhong, S. Harlson, E. Gillispie, T. Wilson, Adedapo Oni, A. Penumatcha, M. S. Kavrik, K. Maxey, A. Kozhakhmetov, C. C. Lin, S. Lee, A. Vyatskikh, N. Arefin, P. Fischer, J. Kevek, T. Tronic, M. Metz, S. B. Clendenning, U. Avci:
Record Performance in GAA 2D NMOS and PMOS Using Monolayer MoS2 and WSe2 with Scaled Contact and Gate Length. 1-2 - Sheng-Hsi Hung, Tz-Wun Wang, Chien-Wei Cho, Po-Jui Chiu, Chi-Yu Chen, Ke-Horng Chen, Kuo-Lin Zheng, Chih-Chen Li:
Field Plate and Package Optimization for GaN Devices and Systems. 1-2 - Xuanqi Chen, Gan Liu, Wei Shi, Yuye Kang, Qiwen Kong, Yuxuan Wang, Rui Shao, Bich-Yen Nguyen, Gengchiau Liang, Kaizhen Han, Xiao Gong:
Fluorine Plasma Treatment-Enabled ITO Transistors: Excellent Reliability and Comprehensive Understanding of Temperature Dependence from 77K to 375K. 1-2 - Chen Tang, Xinyuan Lin, Zongle Huang, Wenyu Sun, Hongyang Jia, Yongpan Liu:
A 28nm 4.35TOPS/mm2 Transformer Accelerator with Basis-vector Based Ultra Storage Compression, Decomposed Computation and Unified LUT-Assisted Cores. 1-2 - Wen-Chia Wu, Terry Y. T. Hung, D. Mahaveer Sathaiya, Edward Chen, Chen-Feng Hsu, Walker Yun, Hsiang-Chi Hu, Bo-Heng Liu, T. Y. Lee, Chi-Chung Kei, Wen-Hao Chang, Jin Cai, W. Jeff, Chung-Cheng Wu, H.-S. Philip Wong, Chao-Hsin Chien, Chao-Ching Cheng, Iuliana P. Radu:
On the Extreme Scaling of Transistors with Monolayer MOS2 Channel. 1-2 - Byeongwoo Koo, Sunghan Do, Sangkyu Lee, Sang-Pil Nam, Heewook Shin, Saemin Im, Hyochul Shin, Sungno Lee, Junsang Park, Jungho Lee, Youngjae Cho, Michael Choi, Jongshin Shin:
A 12-bit 16GS/s Single-Channel RF-DAC with Hybrid Segmentation for Digital Back-Off and Code-Dependent Free Switch Driver Achieving -85dBc IMD3 in 5nm FinFET. 1-2 - Ming-Chieh Huang, Wei Wing Mar, Shankar Kanade, Boris Bai, Aditya Gayatri, Krishna Khairnar, Amy Lai, Yu-Hao Hsu, Hung-Jen Liao, Yih Wang, Tsung-Yung Jonathan Chang:
A 3.3GHz 1024X640 Multi-Bank Single-Port SRAM with Frequency Enhancing Techniques and 0.55V-1.35V Wide Voltage Range Operation in 3nm FinFET for HPC Applications. 1-2 - Gyu-Wan Lim, Gyeong-Gu Kang, Seunghwa Shin, Kihyun Kim, Yousung Park, Won Kim, Young-Bok Kim, Hyun-Kyu Jeon, Hyun-Sik Kim:
An OLED Display Driver IC Embedding -63dB CMR, 80mV/nA Sensitivity, 390pA Detectable, and Column-Parallel Pixel Current Readout for Real-Time Non-Uniformity Compensation. 1-2 - Seryeong Kim, Seokchan Song, Wonhoon Park, Junha Ryu, Sangyeob Kim, Gwangtae Park, Soyeon Kim, Hoi-Jun Yoo:
NeRF-Navi: A 93.6-202.9µJ/task Switchable Approximate-Accurate NeRF Path Planning Processor with Dual Attention Engine and Outlier Bit-Offloading Core. 1-2 - Yubin Qin, Yang Wang, Xiaolong Yang, Zhiren Zhao, Shaojun Wei, Yang Hu, Shouyi Yin:
A 52.01 TFLOPS/W Diffusion Model Processor with Inter-Time-Step Convolution-Attention-Redundancy Elimination and Bipolar Floating-Point Multiplication. 1-2 - Gan Liu, Qiwen Kong, Zuopu Zhou, X. Ying, Chen Sun, Kaizhen Han, Yuye Kang, Dong Zhang, Xiaolin Wang, Yang Feng, Wei Shi, Bich-Yen Nguyen, N. Kai, Gengchiau Liang, Xiao Gong:
Unveiling the Impact of AC PBTI on Hydrogen Formation in Oxide Semiconductor Transistors. 1-2 - Christopher Pelto, R. Aggarwal, R. Ahan, M. Armstrong, M. Bebek, M. Blount, S. Chowdhury, J. Chuah, C. Connor, T. DeBonis, B. Dhayal, A. Dougless, S. Gokhale, A. Jain, V. Javvaji, K. Kamisetty, G. Kim, J. Kpetehoto, C. Kuan, C. Lin, G. Liu, Y. Ma, G. Mcpherson, S. Mokler, Christopher Perini, R. Ramaswamy, Bernhard Sell, R. Subramaniam, James Waldemer, D. Wei, Y. Yang, Y. Yang, J. Yaung, B. Sabi, S. Natarajan:
Integration of Si-Interposer and High Density MIM Capacitor on 2.5D Foveros Face-to-Face Architecture. 1-2 - Venkateswarlu Gaddam, Junghyeon Hwang, Hunbeom Shin, Chaeheon Kim, Giuk Kim, Hyung-Jun Kim, Jooho Lee, Hyun-Cheol Kim, Bumsu Park, Suhwan Lim, Sang Yun Kim, Kwangsoo Kim, Sungho Lee, Daewon Ha, Jinho Ahn, Sanghun Jeon:
Low-Damage Processed and High-Pressure Annealed High-k Hafnium Zirconium Oxide Capacitors near Morphotropic Phase Boundary with Record-Low EOT of 2.4Å & high-k of 70 for DRAM Technology. 1-2 - Ankit Kaul, Madison Manley, James Read, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir:
Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory Accelerators. 1-2 - Tianle Chen, Hongyu Ren, Zunsong Yang, Yunbo Huang, Xianghe Meng, Weiwei Yan, Weidong Zhang, Xuqiang Zheng, Xuan Guo, Tetsuya Iizuka, Pui-In Mak, Yong Chen, Bo Li:
A 6.5-to-6.9-GHz SSPLL with Configurable Differential Dual-Edge SSPD Achieving 44-fs RMS Jitter, -260.7-dB FOMJitter, and -76.5-dBc Reference Spur. 1-2 - Jiayi Wang, Ziheng Bai, Kuo Zhang, Zhicheng Wu, Di Geng, Yang Xu, Nannan You, Yuxuan Li, Guanhua Yang, Ling Li, Shengkai Wang, Ming Liu:
Ge-doped In2O3: First Demonstration of Utlizing Ge as Oxygen Vacancy Consumer to Break the Mobility/Reliability Tradeoff for High Performance Oxide TFTs. 1-2 - Yun Zhou, S. C. Song, Halil Kükner, Giuliano Sisto, Sheng Yang, Anita Farokhnejad, Mohamed Naeim, Moritz Brunion, Ji-Yung Lin, Odysseas Zografos, Pieter Weckx, Shashank Ekbote, Nick Stevens-Yu, David Greenlaw, Steve Molloy, Geert Hellings, Julien Ryckaert:
Backside Power Delivery in High Density and High Performance Context: IR-Drop and Block-Level Power-Performance-Area Benefits. 1-2 - Joosung Oh, Jaehyeon Park, Kiseok Suh, Kangmoon Lee, Sohee Hwang, Myeongjun Bak, Honghyun Kim, Baeseong Kwon, DongKyu Lee, Minkwan Kim, Seungmo Noh, Jongmin Lee, Soomin Cho, Gyuseong Kang, Hyun-Jin Shin, Yongsung Ji, Atsushi Okada, Ung-Hwan Pi, Kwangseok Kim, Younghyun Kim, Jeong-Heon Park, Seungpil Ko, Tae-Young Lee, Kyungtae Nam, Minkwon Cho, Boyoung Seo, Shinhee Han, Yoonjong Song, Kangho Lee, Ja-Hum Ku:
14nm FinFET Node Embedded MRAM Technology for Automotive Non-Volatile RAM Applications with Endurance Over 1E12-Cycles. 1-2 - Zhaomeng Gao, Tianjiao Xin, D. Kai, Qiwendong Zhao, Yiwei Wang, Cheng Liu, Yilin Xu, Rui Wang, Guangjie Shi, Yunzhe Zheng, Yonghui Zheng, Yan Cheng, Hangbing Lyu:
Polar Axis Orientation Control of Hafnium-Based Ferroelectric Capacitors with in-Situ AC Electric Bias During Rapid Thermal Annealing. 1-2 - Ziyi Liu, Yiwei Du, Renrong Liang, Zhigang Zhang, Liyang Pan, Jianshi Tang, Renrong Liang, Bin Gao, Qi Hu, Jun Xu, He Qian, Huaqiang Wu, Yuegang Zhang:
A Dual-Gate Vertical Channel IGZO Transistor for BEOL Stackable 3D Parallel Integration for Memory and Computing Applications. 1-2 - Yue Cao, Honghu Yang, Jianguo Yang, Qi Liu, Ming Liu:
A 67F2 Reconfigurable PUF Using 1T2R RRAM Switching Competition in 28nm CMOS with 5e-9 Bit Error Rate. 1-2 - Yingjie Zhu, Yiqing Lan, Humiao Li, Haoran Lyu, Zhen Kong, Jian Zhao, Yida Li, Guoxing Wang, Jiamin Li, Longyang Lin:
A 0.72nW, 0.006mm2 32kHz Crystal Oscillator with Adaptive Sub-Harmonic Pulse Injection from -40°C to 125°C in 22nm FDSOI. 1-2 - Y. Maeda, Y. Ebiko, H. Terada, Ryo Tetsuya, S. Maeda, Y. Yasu, Takemasa Tamanuki, M. Kamata, K. Hirotani, S. Suyama, K. Yamamoto, S. Nawa, Riku Kubota, Toshihiko Baba:
High-Resolution and Compact Integrated FMCW-LiDAR Chip with 128 Channels of Slow Light Grating Antennas. 1-2 - Hidehiro Tsukano:
Photonics-Electronics Convergence Technology to Accelerate IOWN. 1-5 - Jung-Soo Ko, Alex Shearer, Sol Lee, Kathryn M. Neilson, Marc Jaikissoon, Kwanpyo Kim, Stacey Bent, Krishna Saraswat, Eric Pop:
Achieving 1-nm-Scale Equivalent Oxide Thickness Top Gate Dielectric on Monolayer Transition Metal Dichalcogenide Transistors with CMOS-Friendly Approaches. 1-2 - Giuk Kim, Hyojun Choi, Hunbeom Shin, Sangho Lee, Sangmok Lee, Yunseok Nam, Minhyun Jung, Ilho Myeong, Kijoon Kim, Jongho Woo, Suhwan Lim, Kwangsoo Kim, Wanki Kim, Daewon Ha, Jinho Ahn, Sanghun Jeon:
In-depth Analysis of the Hafnia Ferroelectrics as a Key Enabler for Low Voltage & QLC 3D VNAND Beyond 1K Layers: Experimental Demonstration and Modeling. 1-2 - S. W. Yoo, Y. Lee, W. J. Jung, H. Kim, S. Byeon, M. Kim, J. Lee, T. Lee, M. J. Hong, Y. G. Song, S. Lee, M. Terai, K. J. Yoo, C. Sung, W. Lee, M. H. Cho, D. Kim, D. Ha, S. Ahn, J. H. Song:
A Novel Method for Extracting Asymmetric Source and Drain Resistance in IGZO Vertical Channel Transistors. 1-2 - Vinayak Honkote, Ragh Kuttappa, Jainaveen Sundaram, Satish Yada, Chinnusamy Kalimuthu, Juhi Patil, Richard Lee, Cristan Paulino, Paolo A. Aseron, Trang Nguyen, Amreesh Rao, Dileep Kurian, Mingming Xu, Yan Song, Tanay Karnik, Anuradha Srinivasan, Vivek De:
A 3.2GHz-15GHz Low Jitter Resonant Clock Featuring Rotary Traveling Wave Oscillators in Intel 4 CMOS for 3D Heterogeneous Multi-Die Systems. 1-2 - Anil Kumar Gundu, Luigi Fassio, Massimo Alioto:
E-Textile Battery-Less Walking Step Counting System with <23 pW Power, Dual-Function Harvesting from Breathing, and No High-Voltage CMOS Process. 1-2 - Jaehyun Park, Juhun Park, Kyuman Hwang, Jinchan Yun, Dahye Kim, Sungil Park, Jejune Park, Jinwook Yang, Jae Won Jeong, Chuljin Yun, Jinho Bae, Sam Park, Daihong Huh, Sanghyeon Kim, Seungeun Baek, Suk Yang, Inhae Zoh, Junghan Lee, Tae-sun Kim, Younsu Ha, Sun-Jung Lee, Sang Wuk Park, Bong Jin Kuh, Daewon Ha, Sangjin Hyun, Sujin Ahn, Jaihyuk Song:
Highly manufacturable Self-Aigned Direct Backside Contact (SA-DBC) and Backside Gate Contact (BGC) for 3-dimensional Stacked FET at 48nm gate pitch. 1-2 - Pavan Bhargava, Daniel Jeong, Eric Jan, Derek Van Orden, Derek Kita, Hayk Gevorgyan, Sidney Buchbinder, Anatoly Khilo, Woorham Bae, Sung-Jin Kim, John Michael Fini, Norman Chan, Chen Sun:
A 256Gbps Microring-Based WDM Transceiver with Error-Free Wide Temperature Operation for Co-Packaged Optical I/O Chiplets. 1-2 - Farrukh Yasin, A. Palomino, A. Kumar, Valerio Pica, Simon Van Beek, Giacomo Talmelli, Van D. Nguyen, Stefan Cosemans, D. Crotti, Kurt Wostyn, Gouri Sankar Kar, Sebastien Couet:
Extremely Scaled Perpendicular SOT-MRAM Array Integration on 300mm Wafer. 1-2 - Jaehyung Jang, Jongchae Kim, Sunho Oh, Kyungsu Byun, Dahwan Park, Jihee Han, Hanseung Lee, Suhyun Yi, Hoonmoo Choi, Jongeun Kim, Namil Kim, Yongtae Gim, Minkyu Kim, Sangyoung Lee, Hansang Kim, Eunchang Lee, Minsang Yu, Jeongjoon Hwang, Seunghyun Yoon, Kwang Hwangbo, Heesang Kim, Ahyoung Cho, Taejun Baek, Sooyoung Park, Kwangjun Cho, Wonje Park, Kyung-Do Kim, Hoesam Jeong, Hoon Sang Oh, Changrock Song:
A 336 x 240 Backside-Illuminated 3D-Stacked 7μm SPAD for LiDAR Sensor with PDE 28% at 940nm and under 0.4% Depth Accuracy Up to 10m. 1-2 - Shoichi Kabuyanagi, Takamasa Hamai, Masayuki Murase, Takeru Maeda, Masumi Saitoh, Shosuke Fujii:
A Vertical Channel-All-Around FeFET with Thermally Stable Oxide Semiconductor Achieving High ΔIon> 2µA/cell for 3D Stackable 4F2 High Speed Memory. 1-2 - Ruiqi Guo, Xiaofeng Chen, Lei Wang, Fengbin Tu, Shaojun Wei, Yang Hu, Shouyi Yin:
A 28nm 4170-TFLOPS/W/b and 195-TFLOPS/mm2/b Multiply-Free Fully-Digital Floating-Point Compute-In-Memory Macro with Mitchell's Approximation. 1-2 - Walid M. Hafez, D. Abanulo, M. Abdelkader, S. An, C. Auth, D. Bahr, V. Balakrishnan, Rohan Bambery, M. Beck, M. Bhargava, S. Bhowmick, J. Biggs-houck, J. Birdsall, D. Caselli, H.-Y. Chang, Y. Chang, R. Chaudhuri, S. Chauhan, C. Chen, V. Chikarmane, K. Chikkadi, T. Chu, C. Connor, R. De Alba, Y. Deng, C. Destefano, D. Diana, Y. Dong, P. Elfick, Tyler Elko-Hansen, B. Fallahazad, Y. Fang, D. Gala, D. Garg, C. Geppert, S. Govindaraju, W. Grimm, H. Grunes, L. Guler, Z. Guo, A. Gupta, M. Hattendorf, S. Havelia, J. Hazra, A. Islam, A. Jain, S. Jaloviar, M. Jamil, M. Jang, M. Kabir, J. Kameswaran, Eric Karl, S. Kelgeri, A. Kennedy, C. Kilroy, J. Kim, Y. Kim, D. Krishnan, G. Lee, H.-P. Lee, Q. Li, H. Lin, A. Luk, Y. Luo, P. Macfarlane, A. Mamun, K. Marla, D. Mayeri, E. Mckenna, A. Miah, K. Mistry, M. Mleczko, S. Moon, D. Nardi, S. Natarajan, J. Nathawat, C. Nolph, C. Nugroho, P. Nyhus, A. Oni, P. Packan, D. Pak, A. Paliwal, R. Pandey, I. Paredes, K. Park, L. Paulson, A. Pierre, P. Plekhanov, C. Prasad, R. Ramaswamy, J. Riley, Johann Rode, R. Russell, S. Ryu, H. Saavedra, T. Salisbury, Justin Sandford, F. Shah, K. Shang, P. Shekhar, A. Shu, E. Skoug, J. Sohn, J. Song, M. Sprinkle, J. Su, A. Tan, T. Troeger, R. Tsao, A. Vaidya, C. Wallace, X. Wang, H. Wang, C. Ward, S. Wickramaratne, M. Wills, T. Wu, Z. Xia-hua, S. Xu, P. Yashar, J. Yaung, Y. Yu, M. Zilm, Bernhard Sell:
An Intel 3 Advanced FinFET Platform Technology for High Performance Computing and SOC Product Applications. 1-2 - Wei-Chih Chien, J. X. Zheng, C. W. Yeh, Lynne M. Gignac, H. Y. Cheng, Z. L. Liu, Alexander Grun, C. L. Sung, E. K. Lai, S. Cheng, C. W. Cheng, L. Buzi, A. Ray, Douglas M. Bishop, Robert L. Bruce, M. J. BrightSky, H. L. Lung:
A Novel Chalcogenide Based CuGeSe Selector Only Memory (SOM) for 3D Xpoint and 3D Vertical Memory Applications. 1-2 - Xiangjian Kong, Kai Xu, Robert Bogdan Staszewski, Mingchao Jian, Chunbing Guo:
A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement. 1-2 - Kyosuk Chae, Taiuk Rim, Youngwoo Son, Heejae Choi, Jin-Seong Lee, Shinwoo Jeong, Jieun Lee, Dongin Lee, Byunghyun Lee, Dongsoo Woo, Seguen Park, Sangjun Hwang:
Single Metal BCAT Breakthrough to Open a New Era of 12 nm DRAM and Beyond. 1-2 - Steven Demuynck, Victor Vega-Gonzalez, C. Toledo de Carvalho Cavalcante, L. Petersen Barbosa Lima, K. Stiers, C. Sheng, A. Vandooren, M. Hosseini, X. Zhou, Hans Mertens, Thomas Chiarella, Jürgen Bömmels, Roger Loo, E. Rosseel, Clement Porret, Y. Shimura, A. Akula, G. Mannaert, S. Choudhury, V. Brissonneau, E. Dupuy, T. Sarkar, Nathali Franchina-Vergel, A. Peter, Nicolas Jourdan, J. P. Soulie, Kevin Vandersmissen, F. Sebaai, P. Puttarame Gowda, K. Lai, A. Mingardi, S. Sumar Sarkar, K. D'Have, B. T. Chan, A. Sepulveda Marquez, R. Langer, I. Gyo Koo, E. Altamirano Sanchez, Katia Devriendt, P. Rincon Delgadillo, F. Lazzarino, Jérôme Mitard, J. Geypen, E. Grieten, D. Batuk, Y.-F. Chen, F. Verbeek, F. Holsteyns, S. Subramanian, N. Horiguchi, S. Biesemans:
Monolithic Complementary Field Effect Transistors (CFET) Demonstrated using Middle Dielectric Isolation and Stacked Contacts. 1-2 - P. Zhao, Liesbeth Witters, Anne Jourdain, Michele Stucchi, Nicolas Jourdan, J. W. Maes, H. Bana, C. Zhu, R. Chukka, F. Sebaai, Kevin Vandersmissen, N. Heylen, D. Montero, S. Wang, K. D'Have, F. Schleicher, J. De Vos, Gerald Beyer, A. Miller, Eric Beyne:
Backside Power Delivery with relaxed overlay for backside patterning using extreme wafer thinning and Molybdenum-filled slit nano Through Silicon Vias. 1-2 - Siddharth Agarwal, Gaël Pillonnet, Hongyu Lu, Nader Sherif Kassem Fathy, Patrick P. Mercier:
A Current-Source-Free Constant-Current Wireless Adiabatic Neural Stimulator Achieving a 5.5-27.7x Improved RF-to-Electrode Stimulation Efficiency Factor. 1-2 - Heesung Roh, Hyun Jin Yoo, Si-Youl Yoo, Seung Hee Pyen, Cheonhoo Jeon, Jae-Yoon Sim:
A Smart Contact Lens System with 433MHz Wireless Power and Data Transfer at a Modulation Index Down to 0.02%. 1-2 - Kartik Prabhu, Robert M. Radway, Y. Jeffrey, Kai Bartolone, Massimo Giordano, Fabian Peddinghaus, Yonatan Urman, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Subhasish Mitra, Priyanka Raina:
MINOTAUR: An Edge Transformer Inference and Training Accelerator with 12 MBytes On-Chip Resistive RAM and Fine-Grained Spatiotemporal Power Gating. 1-2 - Kalhan Koul, Maxwell Strange, Jackson Melchert, Alex Carsello, Yuchen Mei, Olivia Hsu, Taeyoung Kong, Po-Han Chen, Huifeng Ke, Keyi Zhang, Qiaoyi Liu, Gedeon Nyengele, Akhilesh Balasingam, Jayashree Adivarahan, Ritvik Sharma, Zhouhua Xie, Christopher Torng, Joel S. Emer, Fredrik Kjolstad, Mark Horowitz, Priyanka Raina:
Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications. 1-2 - Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Niranjan Gowda, Brent R. Carlton:
A PVT Robust 8-Bit Signed Analog Compute-In-Memory Accelerator with Integrated Activation Functions for AI Applications. 1-2 - Tsung-Che Lu, Chin-Ming Fu, Wei-Hsiang Wang, Fred Kuo, Chih-Hsien Chang, Kenny Hsieh, King-Ho Tam, Tze-Chiang Huang, Tom Chen, Mei Wong, Wei-pin Changchien, Frank Lee:
An On-Chip Current-Sink-Free Adaptive-Timing Power Impedance Measurement (PIM) Unit for 3D-IC in 5nm FinFET Technology. 1-2 - Chi-Cheng Lai, Yu-Wen Chiu, I-Hsiang Wang, Ting Tsai, Jhih-Wei Chen, Yen-Hsiang Wang, Mau-Chung Frank Chang, Horng-Chih Lin, Pei-Wen Li:
Photon-Mediated Charge Transport and Stability of Physically-Defined and Self-Organized Germanium Quantum Dots/SON Barriers in Few-Hole Regime at T>10K. 1-2 - Florian Bucheli, Oscar Castañeda, Gian Marti, Christoph Studer:
A Jammer-Mitigating 267 Mb/s 3.78mm2 583 mW 32×8 Multi-User MIMO Receiver in 22FDX. 1-2
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