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ORCIDIEEE Computer Architecture Letters, Volume 16
Volume 16, Number 1, January - June 2017
- Nathan Beckmann, Daniel Sánchez:
Cache Calculus: Modeling Caches through Differential Equations. 1-5 - Xin Zhan, Reza Azimi, Svilen Kanev, David M. Brooks, Sherief Reda:
CARB: A C-State Power Management Arbiter for Latency-Critical Workloads. 6-9 - Dong-Ik Jeon
, Ki-Seok Chung:
CasHMC: A Cycle-Accurate Simulator for Hybrid Memory Cube. 10-13 - Hao Wu, Fangfei Liu, Ruby B. Lee:
Cloud Server Benchmark Suite for Evaluating New Hardware Architectures. 14-17 - Seyed Mohammad Seyedzadeh, Alex K. Jones, Rami G. Melhem:
Counter-Based Tree Structure for Row Hammering Mitigation in DRAM. 18-21 - Hoda Naghibi Jouybari, Nael B. Abu-Ghazaleh:
Covert Channels on GPGPUs. 22-25 - WonJun Song, Hyungjoon Jung, Jung Ho Ahn, Jae W. Lee, John Kim:
Evaluation of Performance Unfairness in NUMA System Architecture. 26-29 - Uri Verner, Avi Mendelson, Assaf Schuster:
Extending Amdahl's Law for Multicores with Turbo Boost. 30-33 - Hiroshi Sasaki, Fang-Hsiang Su, Teruo Tanimoto, Simha Sethumadhavan:
Heavy Tails in Program Structure. 34-37 - Liang Feng, Hao Liang, Sharad Sinha, Wei Zhang:
HeteroSim: A Heterogeneous CPU-FPGA Simulator. 38-41 - Xia Zhao, Yuxi Liu, Almutaz Adileh, Lieven Eeckhout:
LA-LLC: Inter-Core Locality-Aware Last-Level Cache to Exploit Many-to-Many Traffic in GPGPUs. 42-45 - Amirali Boroumand, Saugata Ghose, Minesh Patel, Hasan Hassan, Brandon Lucia, Kevin Hsieh, Krishna T. Malladi, Hongzhong Zheng, Onur Mutlu:
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory. 46-50 - Mark Gottscho, Mohammed Shoaib, Sriram Govindan, Bikash Sharma, Di Wang, Puneet Gupta:
Measuring the Impact of Memory Errors on Application Performance. 51-55 - Almutaz Adileh, Stijn Eyerman, Aamer Jaleel, Lieven Eeckhout:
Mind The Power Holes: Sifting Operating Points in Power-Limited Heterogeneous Multicores. 56-59 - Hiroshi Sasaki, Alper Buyuktosunoglu, Augusto Vega, Pradip Bose:
Mitigating Power Contention: A Scheduling Based Approach. 60-63 - David A. González Márquez, Adrián Cristal Kestelman, Esteban E. Mocskos:
Mth: Codesigned Hardware/Software Support for Fine Grain Threads. 64-67 - Tomer Y. Morad, Gil Shomron, Mattan Erez, Avinoam Kolodny, Uri C. Weiser:
Optimizing Read-Once Data Flow in Big-Data Applications. 68-71 - Ali Yasoubi, Reza Hojabr, Mehdi Modarressi:
Power-Efficient Accelerator Design for Neural Networks Using Computation Reuse. 72-75 - Young Hoon Son, Hyunyoon Cho, Yuhwan Ro, Jae W. Lee, Jung Ho Ahn:
SALAD: Achieving Symmetric Access Latency with Asymmetric DRAM Architecture. 76-79 - Patrick Judd, Jorge Albericio, Andreas Moshovos:
Stripes: Bit-Serial Deep Neural Network Computing. 80-83 - Gokul Subramanian Ravi, Mikko H. Lipasti:
Timing Speculation in Multi-Cycle Data Paths. 84-87
Volume 16, Number 2, July - December 2017
- Samira Manabi Khan, Chris Wilkerson, Donghyuk Lee, Alaa R. Alameldeen, Onur Mutlu:
A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM. 88-93 - Sparsh Mittal, Jeffrey S. Vetter, Lei Jiang:
Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication. 94-98 - Mohammad Bakhshalipour, Pejman Lotfi-Kamran, Hamid Sarbazi-Azad:
An Efficient Temporal Data Prefetcher for L1 Caches. 99-102 - Jorge A. Martínez, Juan Antonio Maestro, Pedro Reviriego:
A Scheme to Improve the Intrinsic Error Detection of the Instruction Set Architecture. 103-106 - Rujia Wang, Sparsh Mittal, Youtao Zhang, Jun Yang:
Decongest: Accelerating Super-Dense PCM Under Write Disturbance by Hot Page Remapping. 107-110 - Teruo Tanimoto, Takatsugu Ono, Koji Inoue, Hiroshi Sasaki:
Enhanced Dependence Graph Model for Critical Path Analysis on Modern Out-of-Order Processors. 111-114 - Junghee Lee, Kalidas Ganesh, Hyuk-Jun Lee, Youngjae Kim:
FeSSD: A Fast Encrypted SSD Employing On-Chip Access-Control Memory. 115-118 - Abdel-Hameed A. Badawy, Donald Yeung:
Guiding Locality Optimizations for Graph Computations via Reuse Distance Analysis. 119-122 - Yue Zha, Jing Li:
IMEC: A Fully Morphable In-Memory Computing Fabric Enabled by Resistive Crossbar. 123-126 - Li-Jhan Chen, Hsiang-Yun Cheng, Po-Han Wang, Chia-Lin Yang:
Improving GPGPU Performance via Cache Locality Aware Thread Block Scheduling. 127-131 - James Garland, David Gregg:
Low Complexity Multiply Accumulate Unit for Weight-Sharing Convolutional Neural Networks. 132-135 - Myoungsoo Jung:
NearZero: An Integration of Phase Change Memory with Multi-Core Coprocessor. 136-140 - Leonid Yavits, Uri C. Weiser, Ran Ginosar:
Resistive Address Decoder. 141-144 - Madhavan Manivannan, Miquel Pericàs, Vassilis Papaefstathiou, Per Stenström:
Runtime-Assisted Global Cache Management for Task-Based Parallel Programs. 145-148 - Arthur Perais, André Seznec:
Storage-Free Memory Dependency Prediction. 149-152 - Amirhossein Mirhosseini, Aditya Agrawal, Josep Torrellas:
Survive: Pointer-Based In-DRAM Incremental Checkpointing for Low-Cost Data Persistence and Rollback-Recovery. 153-157 - Sandro Pinto, Jorge Pereira, Tiago Gomes, Mongkol Ekpanyapong, Adriano Tavares:
Towards a TrustZone-Assisted Hypervisor for Real-Time Embedded Systems. 158-161 - Trevor E. Carlson, Kim-Anh Tran, Alexandra Jimborean, Konstantinos Koukos, Magnus Själander, Stefanos Kaxiras:
Transcending Hardware Limits with Software Out-of-Order Processing. 162-165 - Hossein Ahmadvand, Maziar Goudarzi:
Using Data Variety for Efficient Progressive Big Data Processing in Warehouse-Scale Computers. 166-169 - Dan Zhang, Xiaoyu Ma, Derek Chiou:
Worklist-Directed Prefetching. 170-173
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