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Computer Architecture Letters, Volume 6

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Volume 6, Number 1, January - June 2007

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Miquel Moretó, Francisco J. Cazorla, Alex Ramírez, Mateo Valero:
Explaining Dynamic Cache Partitioning Speed Ups. 1-4
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Natalie D. Enright Jerger, Mikko H. Lipasti, Li-Shiuan Peh:
Circuit-Switched Coherence. 5-8
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Sreekumar V. Kodakara, Jinpyo Kim, David J. Lilja, Douglas M. Hawkins, Wei-Chung Hsu, Pen-Chung Yew:
CIM: A Reliable Metric for Evaluating Program Phase Classifications. 9-12
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William R. Dieter, A. Kaveti, Henry G. Dietz:
Low-Cost Microarchitectural Support for Improved Floating-Point Accuracy. 13-16
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Yoav Etsion, Dror G. Feitelson:
Probabilistic Prediction of Temporal Locality. 17-20
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Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. Weiser:
Nahalal: Cache Organization for Chip Multiprocessors. 21-24

Volume 6, Number 2, July - December 2007

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José A. Joao, Onur Mutlu, Hyesoon Kim, Yale N. Patt:
Dynamic Predication of Indirect Jumps. 25-28
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Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph Zambreno, Alok N. Choudhary:
Microarchitectures for Managing Chip Revenues under Process Variations. 29-32
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Jason Zebchuk, Andreas Moshovos:
A Building Block for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. 33-36
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John Kim, James D. Balfour, William J. Dally:
Flattened Butterfly Topology for On-Chip Networks. 37-40
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Xiang Xiao, Jaehwan John Lee:
A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip. 41-44
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David I. August, Jonathan Chang, Sylvain Girbal, Daniel Gracia Pérez, Gilles Mouchard, David A. Penry, Olivier Temam, Neil Vachharajani:
UNISIM: An Open Simulation Environment and Library for Complex Architecture Design and Collaborative Development. 45-48
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Resit Sendag, Joshua J. Yi, Peng-fei Chuang:
Branch Misprediction Prediction: Complementary Branch Predictors. 49-52
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Gulay Yalcin, Oguz Ergin:
Using Tag-Match Comparators for Detecting Soft Errors. 53-56

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