default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDDesign Automation for Embedded Systems, Volume 5
Volume 5, Number 1, February 2000
- Xiaobo Hu
, Rajeshkumar S. Sambandam:
Multi-Valued Performance Metrics for Real-Time Embedded Systems. 5-28 - Anne Mignotte, Jean-Michel Muller, Olivier Peyran:
Synthesis for Mixed Arithmetic. 29-60 - Gustavo de Veciana, Margarida F. Jacome, Jian-Huei Guo:
Assessing Probabilistic Timing Constraints on System Performance. 61-81 - Axel Jantsch, Johann Notbauer, Thomas W. Albrecht:
Functional Validation of Mixed Hardware/Software Systems based on Specification, Partitioning, and Simulation of Test Cases. 83-113
Volume 5, Number 2, June 2000
- Hiroto Yasuura:
Editorial. 127 - Sungjoo Yoo, Kiyoung Choi:
Optimizing Timed Cosimulation by Hybrid Synchronization. 129-152 - Ing-Jer Huang, Wen-Fu Kao:
A Machine State Transition Approach to Instruction Retargeting for Embedded Microprocessors. 153-177 - Akihiko Inoue, Tohru Ishihara, Hiroto Yasuura:
Flexible System LSI for Embedded Systems and Its Optimization Techniques. 179-205
Volume 5, Numbers 3-4, August 2000
- Klaus D. Müller-Glaser, Fabrice Kordon, Alexander Burst:
Guest Editorial. 213 - Klaus Buchenrieder:
Rapid Prototyping of Embedded Hardware/Software Systems. 215-221 - Fabiano Hessel, Pascal Coste, Philippe Le Marrec, Nacer-Eddine Zergainoh, Gabriela Nicolescu, Jean-Marc Daveau, Ahmed Amine Jerraya:
Interlanguage Communication Synthesis for Heterogeneous Specifications. 223-236 - Stefan M. Petters, Annette Muth, Thomas Kolloch, Thomas Hopfner, Franz Fischer, Georg Färber:
The REAR Framework for Emulation and Analysis of Embedded Hard Real-Time Systems. 237-250 - Valdis Berzins, Man-tak Shing, Luqi, Michael Saluto, Julian Williams:
Architectural Re-engineering of Janus using Object Modeling and Rapid Prototyping. 251-263 - Alexander Burst, Michael Wolff, Bernhard Spitzer, Klaus D. Müller-Glaser:
Scheduling for Concept-Oriented Rapid Prototyping. 265-280 - Karam S. Chatha, Ranga Vemuri:
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling. 281-293 - Ahmed Hemani, Abhijit K. Deb, Johnny Öberg, Adam Postula, Dan Lindqvist, Björn Fjellborg:
System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach. 295-311 - Tanja Van Achteren, Marleen Adé, Rudy Lauwereins, Marc Proesmans, Luc Van Gool, Jan Bormans, Francky Catthoor:
Transformations of a 3D Image Reconstruction Algorithm for Data Transfer and Storage Optimisation. 313-327 - Kia Bazargan, Ryan Kastner, Majid Sarrafzadeh:
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems. 329-338 - Vijay K. Jain, S. Shrivastava:
Rapid System Prototyping for High Performance Reconfigurable Computing. 339-350 - Frank-Michael Renner, Jürgen Becker, Manfred Glesner:
Communication Performance Models for Architecture-Precise Prototyping of Real-Time Embedded Systems. 351-363
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2025-11-26 07:56 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
