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ORCIDIEEE Embedded Systems Letters, Volume 14
Volume 14, Number 1, March 2022
- Preeti Ranjan Panda
:
Editorial. 1-2
- Sofiane Chetoui, Sherief Reda:
CasCon: Cascaded Thermal and Electrical Current Throttling for Mobile Devices. 3-6 - Liu Yang, Qi Wang, Qianhui Li, Xiaolei Yu, Jing He, Zongliang Huo:
Gradual Channel Estimation Method for TLC NAND Flash Memory. 7-10 - Wei Chen, Peng Hao, Dake Liu, Yong Bai:
Compilation of Parallel Data Access for Vector Processor in Radio Base Stations. 11-14 - Eunjin Jeong, Jangryul Kim, Samnieng Tan, Jaeseong Lee, Soonhoi Ha:
Deep Learning Inference Parallelization on Heterogeneous Processors With TensorRT. 15-18 - Francisco Pajuelo-Holguera, José M. Granado Criado, Juan Antonio Gómez Pulido:
Fast Montgomery Modular Multiplier Using FPGAs. 19-22 - Liping Wang, Saideep Tiku, Sudeep Pasricha:
CHISEL: Compression-Aware High-Accuracy Embedded Indoor Localization With Deep Learning. 23-26 - Mohammed Zubair M. Shamim, Sattam Alotaibi, Hany S. Hussein, Mohammed Farrag, Mohammad Shiblee:
Diagnostic Accuracy of Smartphone-Connected Electrophysiological Biosensors for Prediction of Blood Glucose Level in a Type-2 Diabetic Patient Using Machine Learning: A Pilot Study. 27-30 - Raja Sekar Kumaresan, Marshal Raj, G. Lakshminarayanan:
High-Speed Serial-Parallel Multiplier in Quantum-Dot Cellular Automata. 31-34 - Ali Zahir, Anees Ullah, Pedro Reviriego, Syed Riaz Ul Hassnain:
Efficient Leading Zero Count (LZC) Implementations for Xilinx FPGAs. 35-38 - Mohammad Ashjaei, Lejla Murselovic, Saad Mubeen:
Implications of Various Preemption Configurations in TSN Networks. 39-42 - Michael Barrow, Francesco Restuccia, Mustafa S. Gobulukoglu, Enrico Rossi, Ryan Kastner:
A Remote Control System for Emergency Ventilators During SARS-CoV-2. 43-46 - Mahmood Rafiee, Nabiollah Shiri, Ayoub Sadeghi:
High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures. 47-50 - A. Alper Goksoy, Anish Krishnakumar, Md Sahil Hassan, Allen-Jasmin Farcas, Ali Akoglu, Radu Marculescu, Ümit Y. Ogras:
DAS: Dynamic Adaptive Scheduling for Energy-Efficient Heterogeneous SoCs. 51-54
Volume 14, Number 2, June 2022
- Hoon Sung Chwa, Jinkyu Lee:
Infeasibility Test for Fixed-Priority Scheduling on Multiprocessor Platforms. 55-58 - Uppugunduru Anil Kumar, Sumit K. Chatterjee, Syed Ershad Ahmed:
Low-Power Compressor-Based Approximate Multipliers With Error Correcting Module. 59-62 - Muhammad Irfan, Hasan Erdem Yantir, Zahid Ullah, Ray C. C. Cheung:
Comp-TCAM: An Adaptable Composite Ternary Content-Addressable Memory on FPGAs. 63-66 - Surajit Das, Chandan Karfa:
Arc Model and DDG: Deadlock Avoidance and Detection in Torus NoC. 67-70 - Prabuddha Chakraborty, Jonathan Cruz, Christopher Posada, Sandip Ray, Swarup Bhunia:
HASTE: Software Security Analysis for Timing Attacks on Clear Hardware Assumption. 71-74 - Thomas Newton, James Timothy Meech, Phillip Stanley-Marbell:
Machine Learning for Sensor Transducer Conversion Routines. 75-78 - Luca Cassano, Antonio Miele, Francesco Mione, Nicola Tonellotto, Carlo Vallati:
Design of Fault-Tolerant Distributed Cyber-Physical Systems for Smart Environments. 79-82 - Myungsun Kim:
Guaranteeing That Multilevel Prioritized DNN Models on an Embedded GPU Have Inference Performance Proportional to Respective Priorities. 83-86 - Seongtae Lee, Sanghyeok Park, Jinkyu Lee:
Improved Low Time-Complexity Schedulability Test for Nonpreemptive EDF on a Multiprocessor. 87-90 - Boris Dreyer, Christian Hochberger, Simon Wegener:
Call String Sensitivity for Hardware-Based Hybrid WCET Analysis. 91-94 - Ming Ling, Hongxi Li, Xiang Yu:
A Quantitative Analysis and Optimization on the Cache Behavior Influenced by Literal Pools. 95-98 - Ignacio M. Delgado-Lozano, Erica Tena-Sánchez, Juan Núñez, Antonio J. Acosta:
Gate-Level Design Methodology for Side-Channel Resistant Logic Styles Using TFETs. 99-102 - Nikhil Rangarajan, Johann Knechtel, Dinesh Rajasekharan, Ozgur Sinanoglu:
SuperVAULT: Superparamagnetic Volatile Auxiliary Tamper-Proof Storage. 103-106 - Giulio Galderisi, Thomas Mikolajick, Jens Trommer:
Reconfigurable Field Effect Transistors Design Solutions for Delay-Invariant Logic Gates. 107-110
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