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Formal Methods in System Design, Volume 9

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Volume 9, Number 1/2, August 1996

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Kurt Jensen:
Condensed State Spaces for Symmetrical Coloured Petri Nets. 7-40
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C. Norris Ip, David L. Dill:
Better Verification Through Symmetry. 41-75
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Edmund M. Clarke, Somesh Jha, Reinhard Enders, Thomas Filkorn:
Exploiting Symmetry in Temporal Logic Model Checking. 77-104
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E. Allen Emerson, A. Prasad Sistla:
Symmetry and Model Checking. 105-131

Volume 9, Number 3, 1996

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Alexandre Yakovlev, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli:
A Unified Signal Transition Graph Model for Asynchronous Control Circuit Synthesis. 139-188
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Alexandre Yakovlev, Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Marta Pietkiewicz-Koutny:
On the Models for Asynchronous Circuit Behaviour with OR Causality. 189-233
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Leo Marcus:
The Incorporation of Testing into Formal Verification: Direct, Modular, and Hierarchical Correctness Degrees. 235-261
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Tommaso Bolognesi:
Regrouping Parallel Processes. 263-302

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