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ORCIDIET Computers & Digital Techniques, Volume 14
Volume 14, Number 1, 2020
- Ihsen Alouani
, Hamzeh Ahangari, Ozcan Ozturk, Smaïl Niar:
Power-efficient reliable register file for aggressive-environment applications. 1-8 - Pinar Kullu, Yilmaz Ar, Suleyman Tosun, Suat Ozdemir:
Mapping application-specific topology to mesh topology with reconfigurable switches. 9-16 - Golnaz Taheri, Ahmad Khonsari, Reza Entezari-Maleki, Leonel Sousa:
Temperature-aware core management in MPSoCs: modelling and evaluation using MRMs. 17-26 - Leonel Hernández Martínez, S. Saqib Khursheed, Sudhakar M. Reddy:
LFSR generation for high test coverage and low hardware overhead. 27-36 - Pradeepa Parthiban, Pushpalakshmi Raman:
Multi-objective constraint and hybrid optimisation-based VM migration in a community cloud. 37-45
Volume 14, Number 2, 2020
- Anakhi Hazarika, Soumyajit Poddar, Hafizur Rahaman:
Survey on memory management techniques in heterogeneous computing systems. 47-60 - Irith Pomeranz:
LFSR-based generation of boundary-functional broadside tests. 61-68 - Bahram Rashidi:
Efficient and flexible hardware structures of the 128 bit CLEFIA block cipher. 69-79 - Jie Li, Shanshan Liu, Pedro Reviriego, Liyi Xiao, Fabrizio Lombardi:
Scheme for periodical concurrent fault detection in parallel CRC circuits. 80-85
Volume 14, Number 3, 2020
- Sandeep Mishra, Telajala Venkata Mahendra, Sheikh Wasmir Hussain, Anup Dandapat:
The analogy of matchline sensing techniques for content addressable memory (CAM). 87-96 - Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei:
Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches. 97-106 - Vaithiyanathan Dhandapani, Ravindra Kumar, Ashima Rai, Khushboo Sharma:
Performance analysis of dynamic CMOS circuit based on node-discharger and twist-connected transistors. 107-113 - Rohit Lorenzo, Roy Pailly:
Single bit-line 11T SRAM cell for low power and improved stability. 114-121 - Gokulkrishnan Vadakkeveedu, Kamakoti Veezhinathan, Nitin Chandrachoodan, Seetal Potluri:
Scalable pseudo-exhaustive methodology for testing and diagnosis in flow-based microfluidic biochips. 122-131
Volume 14, Number 4, 2020
- Mohammed A. Noaman Al-Hayanni, Fei Xia, Ashur Rafiev, Alexander B. Romanovsky, Rishad A. Shafik, Alex Yakovlev:
Amdahl's law in the context of heterogeneous many-core systems - a survey. 133-148 - Yasir Ali Shah, Khalid Javeed, Muhammad Imran Shehzad, Shoaib Azmat:
LUT-based high-speed point multiplier for Goldilocks-Curve448. 149-157 - Sreeja Rajendran, Mary Lourde Regeena:
Sensitivity analysis of testability parameters for secure IC design. 158-165 - Nooshin Azimi, Reza Faghih Mirzaee, Keivan Navi, Amir Masoud Rahmani:
Ternary DDCVSL: a combined dynamic logic style for standard ternary logic with single power source. 166-175 - Smita Singhal, Anu Mehra, Upendra Tripathi:
V th and dual-T ox assignment in 16 nm CMOS technology Design topologies with dual-V th and dual-T ox assignment in 16 nm CMOS technology. 176-186
Volume 14, Number 5, 2020
- Nevena R. Brnovic, Veselin N. Ivanovic, Igor Djurovic, Marko Simeunovic:
Multi-core hardware realisation of the quasi maximum likelihood PPS estimator. 187-192 - Ganesh Kumar Ganjikunta, Subhendu Kumar Sahoo:
Area and power-efficient variable-length fast Fourier transform for MR-OFDM physical layer of IEEE 802.15.4-g. 193-200 - Wei Li, Jun Liang, Yunquan Zhang, Haipeng Jia, Lin Xiao, Qing Li:
Accelerated LiDAR data processing algorithm for self-driving cars on the heterogeneous computing platform. 201-209 - Raj Kumar Maity, Sayan Tripathi, Jagannath Samanta, Jaydeb Bhaumik:
Lower complexity error location detection block of adjacent error correcting decoder for SRAMs. 210-216 - Vikas Pathak, Satyasai Jagannath Nanda, Amit Mahesh Joshi, Sitanshu Sekhar Sahu:
VLSI implementation of anti-notch lattice structure for identification of exon regions in Eukaryotic genes. 217-229
Volume 14, Number 6, November 2020
- Mingfu Xue, Chongyan Gu, Weiqiang Liu, Shichao Yu, Máire O'Neill:
Ten years of hardware Trojans: a survey from the attacker's perspective. 231-246 - M. Mohamed Asan Basiri:
Efficient VLSI architectures of lifting based 3D discrete wavelet transform. 247-255 - Nejmeddine Bahri, Randa Khemiri:
Optimised HEVC encoder intra-only configuration. 256-262 - Khokan Mondal, Subhajit Das, Tuhina Samanta:
Rectilinear routing algorithm for crosstalk minimisation in 2D and 3D IC. 263-271 - Weng Xiaodong, Liu Yi, Yintang Yang:
Network-on-chip heuristic mapping algorithm based on isomorphism elimination for NoC optimisation. 272-280 - Lalengmawia Chhangte, Alok Chakrabarty:
Technique for two-dimensional nearest neighbour realisation of quantum circuits using weighted look-ahead. 281-289 - Sagar Reddy Vumanthala, Kalagadda Bikshalu:
Real-time speech enhancement using optimised empirical mode decomposition and non-local means estimation. 290-298 - Sumitra Velayudham, Sivakumar Rajagopal, Yeragudipati Venkata Ramana Rao, Seok-Bum Ko:
Power efficient error correction coding for on-chip interconnection links. 299-312 - Mahdi Abbasi, Milad Rafiee:
Efficient parallelisation of the packet classification algorithms on multi-core central processing units using multi-threading application program interfaces. 313-321 - Rajib Lochan Jana, Soumyajit Dey, Arijit Mondal, Pallab Dasgupta:
Automated planning for finding alternative bug traces. 322-335 - Mrinal Goswami, Jayanta Pal, Mayukh Roy Choudhury, Pritam P. Chougule, Bibhash Sen:
In memory computation using quantum-dot cellular automata. 336-343 - Karim Shahbazi, Seok-Bum Ko:
High throughput and area-efficient FPGA implementation of AES for high-traffic applications. 344-352 - Xiaokun Yang, Shi Sha, Ishaq Unwala, Jiang Lu:
Towards IP integration on SoC: a case study of high-throughput and low-cost wrapper design on a novel IBUS architecture. 353-362
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